1 /**************************************************************************
2 *
3 * Copyright 2013 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <unistd.h>
35
36 #include "util/u_memory.h"
37 #include "util/u_video.h"
38
39 #include "vl/vl_defines.h"
40 #include "vl/vl_video_buffer.h"
41
42 #include "r600_pipe_common.h"
43 #include "radeon_video.h"
44 #include "radeon_vce.h"
45
46 #define UVD_FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
47
48 /* generate an stream handle */
rvid_alloc_stream_handle()49 unsigned rvid_alloc_stream_handle()
50 {
51 static unsigned counter = 0;
52 unsigned stream_handle = 0;
53 unsigned pid = getpid();
54 int i;
55
56 for (i = 0; i < 32; ++i)
57 stream_handle |= ((pid >> i) & 1) << (31 - i);
58
59 stream_handle ^= ++counter;
60 return stream_handle;
61 }
62
63 /* create a buffer in the winsys */
rvid_create_buffer(struct pipe_screen * screen,struct rvid_buffer * buffer,unsigned size,unsigned usage)64 bool rvid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
65 unsigned size, unsigned usage)
66 {
67 memset(buffer, 0, sizeof(*buffer));
68 buffer->usage = usage;
69
70 /* Hardware buffer placement restrictions require the kernel to be
71 * able to move buffers around individually, so request a
72 * non-sub-allocated buffer.
73 */
74 buffer->res = (struct r600_resource *)
75 pipe_buffer_create(screen, PIPE_BIND_SHARED,
76 usage, size);
77
78 return buffer->res != NULL;
79 }
80
81 /* destroy a buffer */
rvid_destroy_buffer(struct rvid_buffer * buffer)82 void rvid_destroy_buffer(struct rvid_buffer *buffer)
83 {
84 r600_resource_reference(&buffer->res, NULL);
85 }
86
87 /* reallocate a buffer, preserving its content */
rvid_resize_buffer(struct pipe_screen * screen,struct radeon_winsys_cs * cs,struct rvid_buffer * new_buf,unsigned new_size)88 bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
89 struct rvid_buffer *new_buf, unsigned new_size)
90 {
91 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
92 struct radeon_winsys* ws = rscreen->ws;
93 unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
94 struct rvid_buffer old_buf = *new_buf;
95 void *src = NULL, *dst = NULL;
96
97 if (!rvid_create_buffer(screen, new_buf, new_size, new_buf->usage))
98 goto error;
99
100 src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
101 if (!src)
102 goto error;
103
104 dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
105 if (!dst)
106 goto error;
107
108 memcpy(dst, src, bytes);
109 if (new_size > bytes) {
110 new_size -= bytes;
111 dst += bytes;
112 memset(dst, 0, new_size);
113 }
114 ws->buffer_unmap(new_buf->res->buf);
115 ws->buffer_unmap(old_buf.res->buf);
116 rvid_destroy_buffer(&old_buf);
117 return true;
118
119 error:
120 if (src)
121 ws->buffer_unmap(old_buf.res->buf);
122 rvid_destroy_buffer(new_buf);
123 *new_buf = old_buf;
124 return false;
125 }
126
127 /* clear the buffer with zeros */
rvid_clear_buffer(struct pipe_context * context,struct rvid_buffer * buffer)128 void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
129 {
130 struct r600_common_context *rctx = (struct r600_common_context*)context;
131
132 rctx->dma_clear_buffer(context, &buffer->res->b.b, 0,
133 buffer->res->buf->size, 0);
134 context->flush(context, NULL, 0);
135 }
136
137 /**
138 * join surfaces into the same buffer with identical tiling params
139 * sumup their sizes and replace the backend buffers with a single bo
140 */
rvid_join_surfaces(struct r600_common_context * rctx,struct pb_buffer ** buffers[VL_NUM_COMPONENTS],struct radeon_surf * surfaces[VL_NUM_COMPONENTS])141 void rvid_join_surfaces(struct r600_common_context *rctx,
142 struct pb_buffer** buffers[VL_NUM_COMPONENTS],
143 struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
144 {
145 struct radeon_winsys* ws;
146 unsigned best_tiling, best_wh, off;
147 unsigned size, alignment;
148 struct pb_buffer *pb;
149 unsigned i, j;
150
151 ws = rctx->ws;
152
153 for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
154 unsigned wh;
155
156 if (!surfaces[i])
157 continue;
158
159 /* choose the smallest bank w/h for now */
160 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
161 if (wh < best_wh) {
162 best_wh = wh;
163 best_tiling = i;
164 }
165 }
166
167 for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
168 if (!surfaces[i])
169 continue;
170
171 /* adjust the texture layer offsets */
172 off = align(off, surfaces[i]->surf_alignment);
173
174 /* copy the tiling parameters */
175 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
176 surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
177 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
178 surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
179
180 for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
181 surfaces[i]->u.legacy.level[j].offset += off;
182
183 off += surfaces[i]->surf_size;
184 }
185
186 for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
187 if (!buffers[i] || !*buffers[i])
188 continue;
189
190 size = align(size, (*buffers[i])->alignment);
191 size += (*buffers[i])->size;
192 alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
193 }
194
195 if (!size)
196 return;
197
198 /* TODO: 2D tiling workaround */
199 alignment *= 2;
200
201 pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM,
202 RADEON_FLAG_GTT_WC);
203 if (!pb)
204 return;
205
206 for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
207 if (!buffers[i] || !*buffers[i])
208 continue;
209
210 pb_reference(buffers[i], pb);
211 }
212
213 pb_reference(&pb, NULL);
214 }
215
rvid_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)216 int rvid_get_video_param(struct pipe_screen *screen,
217 enum pipe_video_profile profile,
218 enum pipe_video_entrypoint entrypoint,
219 enum pipe_video_cap param)
220 {
221 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
222 enum pipe_video_format codec = u_reduce_video_profile(profile);
223 struct radeon_info info;
224
225 rscreen->ws->query_info(rscreen->ws, &info);
226
227 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
228 switch (param) {
229 case PIPE_VIDEO_CAP_SUPPORTED:
230 return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
231 rvce_is_fw_version_supported(rscreen);
232 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
233 return 1;
234 case PIPE_VIDEO_CAP_MAX_WIDTH:
235 return 2048;
236 case PIPE_VIDEO_CAP_MAX_HEIGHT:
237 return 1152;
238 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
239 return PIPE_FORMAT_NV12;
240 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
241 return false;
242 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
243 return false;
244 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
245 return true;
246 case PIPE_VIDEO_CAP_STACKED_FRAMES:
247 return 1;
248 default:
249 return 0;
250 }
251 }
252
253 switch (param) {
254 case PIPE_VIDEO_CAP_SUPPORTED:
255 switch (codec) {
256 case PIPE_VIDEO_FORMAT_MPEG12:
257 return profile != PIPE_VIDEO_PROFILE_MPEG1;
258 case PIPE_VIDEO_FORMAT_MPEG4:
259 /* no support for MPEG4 on older hw */
260 return rscreen->family >= CHIP_PALM;
261 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
262 return true;
263 case PIPE_VIDEO_FORMAT_VC1:
264 return true;
265 case PIPE_VIDEO_FORMAT_HEVC:
266 return false;
267 case PIPE_VIDEO_FORMAT_JPEG:
268 return false;
269 default:
270 return false;
271 }
272 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
273 return 1;
274 case PIPE_VIDEO_CAP_MAX_WIDTH:
275 return 2048;
276 case PIPE_VIDEO_CAP_MAX_HEIGHT:
277 return 1152;
278 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
279 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
280 return PIPE_FORMAT_P016;
281 else
282 return PIPE_FORMAT_NV12;
283
284 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
285 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
286 if (rscreen->family < CHIP_PALM) {
287 /* MPEG2 only with shaders and no support for
288 interlacing on R6xx style UVD */
289 return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
290 rscreen->family > CHIP_RV770;
291 } else {
292 enum pipe_video_format format = u_reduce_video_profile(profile);
293
294 if (format == PIPE_VIDEO_FORMAT_HEVC)
295 return false; //The firmware doesn't support interlaced HEVC.
296 else if (format == PIPE_VIDEO_FORMAT_JPEG)
297 return false;
298 return true;
299 }
300 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
301 return true;
302 case PIPE_VIDEO_CAP_MAX_LEVEL:
303 switch (profile) {
304 case PIPE_VIDEO_PROFILE_MPEG1:
305 return 0;
306 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
307 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
308 return 3;
309 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
310 return 3;
311 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
312 return 5;
313 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
314 return 1;
315 case PIPE_VIDEO_PROFILE_VC1_MAIN:
316 return 2;
317 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
318 return 4;
319 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
320 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
321 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
322 return 41;
323 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
324 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
325 return 186;
326 default:
327 return 0;
328 }
329 default:
330 return 0;
331 }
332 }
333
rvid_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint)334 boolean rvid_is_format_supported(struct pipe_screen *screen,
335 enum pipe_format format,
336 enum pipe_video_profile profile,
337 enum pipe_video_entrypoint entrypoint)
338 {
339 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
340 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
341 return (format == PIPE_FORMAT_NV12) ||
342 (format == PIPE_FORMAT_P016);
343
344 /* we can only handle this one with UVD */
345 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
346 return format == PIPE_FORMAT_NV12;
347
348 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
349 }
350