Searched defs:saddlp (Results 1 – 5 of 5) sorted by relevance
/external/vixl/test/aarch64/ |
D | test-trace-aarch64.cc | 1385 __ saddlp(v10.V1D(), v25.V2S()); in GenerateTestSequenceNEON() local 1386 __ saddlp(v15.V2D(), v16.V4S()); in GenerateTestSequenceNEON() local 1387 __ saddlp(v18.V2S(), v10.V4H()); in GenerateTestSequenceNEON() local 1388 __ saddlp(v29.V4H(), v26.V8B()); in GenerateTestSequenceNEON() local 1389 __ saddlp(v10.V4S(), v1.V8H()); in GenerateTestSequenceNEON() local 1390 __ saddlp(v0.V8H(), v21.V16B()); in GenerateTestSequenceNEON() local
|
/external/v8/src/arm64/ |
D | assembler-arm64.cc | 2384 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) { in saddlp() function in v8::internal::Assembler
|
D | simulator-logic-arm64.cc | 1957 LogicVRegister Simulator::saddlp(VectorFormat vform, LogicVRegister dst, in saddlp() function in v8::internal::Simulator
|
/external/vixl/src/aarch64/ |
D | assembler-aarch64.cc | 4467 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) { in saddlp() function in vixl::aarch64::Assembler
|
D | logic-aarch64.cc | 2185 LogicVRegister Simulator::saddlp(VectorFormat vform, in saddlp() function in vixl::aarch64::Simulator
|