1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "compiler/glsl/ir.h"
25 #include "brw_fs.h"
26 #include "brw_fs_surface_builder.h"
27 #include "brw_nir.h"
28
29 using namespace brw;
30 using namespace brw::surface_access;
31
32 void
emit_nir_code()33 fs_visitor::emit_nir_code()
34 {
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
37 */
38 nir_setup_outputs();
39 nir_setup_uniforms();
40 nir_emit_system_values();
41
42 /* get the main function and emit it */
43 nir_foreach_function(function, nir) {
44 assert(strcmp(function->name, "main") == 0);
45 assert(function->impl);
46 nir_emit_impl(function->impl);
47 }
48 }
49
50 void
nir_setup_outputs()51 fs_visitor::nir_setup_outputs()
52 {
53 if (stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_FRAGMENT)
54 return;
55
56 unsigned vec4s[VARYING_SLOT_TESS_MAX] = { 0, };
57
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
61 */
62 nir_foreach_variable(var, &nir->outputs) {
63 const int loc = var->data.driver_location;
64 const unsigned var_vec4s =
65 var->data.compact ? DIV_ROUND_UP(glsl_get_length(var->type), 4)
66 : type_size_vec4(var->type);
67 vec4s[loc] = MAX2(vec4s[loc], var_vec4s);
68 }
69
70 nir_foreach_variable(var, &nir->outputs) {
71 const int loc = var->data.driver_location;
72 if (outputs[loc].file == BAD_FILE) {
73 fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_F, 4 * vec4s[loc]);
74 for (unsigned i = 0; i < vec4s[loc]; i++) {
75 outputs[loc + i] = offset(reg, bld, 4 * i);
76 }
77 }
78 }
79 }
80
81 void
nir_setup_uniforms()82 fs_visitor::nir_setup_uniforms()
83 {
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc) {
86 assert(pull_constant_loc);
87 return;
88 }
89
90 uniforms = nir->num_uniforms / 4;
91
92 if (stage == MESA_SHADER_COMPUTE) {
93 /* Add a uniform for the thread local id. It must be the last uniform
94 * on the list.
95 */
96 assert(uniforms == prog_data->nr_params);
97 uint32_t *param = brw_stage_prog_data_add_params(prog_data, 1);
98 *param = BRW_PARAM_BUILTIN_SUBGROUP_ID;
99 subgroup_id = fs_reg(UNIFORM, uniforms++, BRW_REGISTER_TYPE_UD);
100 }
101 }
102
103 static bool
emit_system_values_block(nir_block * block,fs_visitor * v)104 emit_system_values_block(nir_block *block, fs_visitor *v)
105 {
106 fs_reg *reg;
107
108 nir_foreach_instr(instr, block) {
109 if (instr->type != nir_instr_type_intrinsic)
110 continue;
111
112 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
113 switch (intrin->intrinsic) {
114 case nir_intrinsic_load_vertex_id:
115 unreachable("should be lowered by lower_vertex_id().");
116
117 case nir_intrinsic_load_vertex_id_zero_base:
118 case nir_intrinsic_load_base_vertex:
119 case nir_intrinsic_load_instance_id:
120 case nir_intrinsic_load_base_instance:
121 case nir_intrinsic_load_draw_id:
122 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
123
124 case nir_intrinsic_load_invocation_id:
125 if (v->stage == MESA_SHADER_TESS_CTRL)
126 break;
127 assert(v->stage == MESA_SHADER_GEOMETRY);
128 reg = &v->nir_system_values[SYSTEM_VALUE_INVOCATION_ID];
129 if (reg->file == BAD_FILE) {
130 const fs_builder abld = v->bld.annotate("gl_InvocationID", NULL);
131 fs_reg g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
132 fs_reg iid = abld.vgrf(BRW_REGISTER_TYPE_UD, 1);
133 abld.SHR(iid, g1, brw_imm_ud(27u));
134 *reg = iid;
135 }
136 break;
137
138 case nir_intrinsic_load_sample_pos:
139 assert(v->stage == MESA_SHADER_FRAGMENT);
140 reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_POS];
141 if (reg->file == BAD_FILE)
142 *reg = *v->emit_samplepos_setup();
143 break;
144
145 case nir_intrinsic_load_sample_id:
146 assert(v->stage == MESA_SHADER_FRAGMENT);
147 reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_ID];
148 if (reg->file == BAD_FILE)
149 *reg = *v->emit_sampleid_setup();
150 break;
151
152 case nir_intrinsic_load_sample_mask_in:
153 assert(v->stage == MESA_SHADER_FRAGMENT);
154 assert(v->devinfo->gen >= 7);
155 reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_MASK_IN];
156 if (reg->file == BAD_FILE)
157 *reg = *v->emit_samplemaskin_setup();
158 break;
159
160 case nir_intrinsic_load_work_group_id:
161 assert(v->stage == MESA_SHADER_COMPUTE);
162 reg = &v->nir_system_values[SYSTEM_VALUE_WORK_GROUP_ID];
163 if (reg->file == BAD_FILE)
164 *reg = *v->emit_cs_work_group_id_setup();
165 break;
166
167 case nir_intrinsic_load_helper_invocation:
168 assert(v->stage == MESA_SHADER_FRAGMENT);
169 reg = &v->nir_system_values[SYSTEM_VALUE_HELPER_INVOCATION];
170 if (reg->file == BAD_FILE) {
171 const fs_builder abld =
172 v->bld.annotate("gl_HelperInvocation", NULL);
173
174 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
175 * pixel mask is in g1.7 of the thread payload.
176 *
177 * We move the per-channel pixel enable bit to the low bit of each
178 * channel by shifting the byte containing the pixel mask by the
179 * vector immediate 0x76543210UV.
180 *
181 * The region of <1,8,0> reads only 1 byte (the pixel masks for
182 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
183 * masks for 2 and 3) in SIMD16.
184 */
185 fs_reg shifted = abld.vgrf(BRW_REGISTER_TYPE_UW, 1);
186 abld.SHR(shifted,
187 stride(byte_offset(retype(brw_vec1_grf(1, 0),
188 BRW_REGISTER_TYPE_UB), 28),
189 1, 8, 0),
190 brw_imm_v(0x76543210));
191
192 /* A set bit in the pixel mask means the channel is enabled, but
193 * that is the opposite of gl_HelperInvocation so we need to invert
194 * the mask.
195 *
196 * The negate source-modifier bit of logical instructions on Gen8+
197 * performs 1's complement negation, so we can use that instead of
198 * a NOT instruction.
199 */
200 fs_reg inverted = negate(shifted);
201 if (v->devinfo->gen < 8) {
202 inverted = abld.vgrf(BRW_REGISTER_TYPE_UW);
203 abld.NOT(inverted, shifted);
204 }
205
206 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
207 * with 1 and negating.
208 */
209 fs_reg anded = abld.vgrf(BRW_REGISTER_TYPE_UD, 1);
210 abld.AND(anded, inverted, brw_imm_uw(1));
211
212 fs_reg dst = abld.vgrf(BRW_REGISTER_TYPE_D, 1);
213 abld.MOV(dst, negate(retype(anded, BRW_REGISTER_TYPE_D)));
214 *reg = dst;
215 }
216 break;
217
218 default:
219 break;
220 }
221 }
222
223 return true;
224 }
225
226 void
nir_emit_system_values()227 fs_visitor::nir_emit_system_values()
228 {
229 nir_system_values = ralloc_array(mem_ctx, fs_reg, SYSTEM_VALUE_MAX);
230 for (unsigned i = 0; i < SYSTEM_VALUE_MAX; i++) {
231 nir_system_values[i] = fs_reg();
232 }
233
234 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
235 * never end up using it.
236 */
237 {
238 const fs_builder abld = bld.annotate("gl_SubgroupInvocation", NULL);
239 fs_reg ® = nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION];
240 reg = abld.vgrf(BRW_REGISTER_TYPE_UW);
241
242 const fs_builder allbld8 = abld.group(8, 0).exec_all();
243 allbld8.MOV(reg, brw_imm_v(0x76543210));
244 if (dispatch_width > 8)
245 allbld8.ADD(byte_offset(reg, 16), reg, brw_imm_uw(8u));
246 if (dispatch_width > 16) {
247 const fs_builder allbld16 = abld.group(16, 0).exec_all();
248 allbld16.ADD(byte_offset(reg, 32), reg, brw_imm_uw(16u));
249 }
250 }
251
252 nir_foreach_function(function, nir) {
253 assert(strcmp(function->name, "main") == 0);
254 assert(function->impl);
255 nir_foreach_block(block, function->impl) {
256 emit_system_values_block(block, this);
257 }
258 }
259 }
260
261 /*
262 * Returns a type based on a reference_type (word, float, half-float) and a
263 * given bit_size.
264 *
265 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
266 *
267 * @FIXME: 64-bit return types are always DF on integer types to maintain
268 * compability with uses of DF previously to the introduction of int64
269 * support.
270 */
271 static brw_reg_type
brw_reg_type_from_bit_size(const unsigned bit_size,const brw_reg_type reference_type)272 brw_reg_type_from_bit_size(const unsigned bit_size,
273 const brw_reg_type reference_type)
274 {
275 switch(reference_type) {
276 case BRW_REGISTER_TYPE_HF:
277 case BRW_REGISTER_TYPE_F:
278 case BRW_REGISTER_TYPE_DF:
279 switch(bit_size) {
280 case 16:
281 return BRW_REGISTER_TYPE_HF;
282 case 32:
283 return BRW_REGISTER_TYPE_F;
284 case 64:
285 return BRW_REGISTER_TYPE_DF;
286 default:
287 unreachable("Invalid bit size");
288 }
289 case BRW_REGISTER_TYPE_W:
290 case BRW_REGISTER_TYPE_D:
291 case BRW_REGISTER_TYPE_Q:
292 switch(bit_size) {
293 case 16:
294 return BRW_REGISTER_TYPE_W;
295 case 32:
296 return BRW_REGISTER_TYPE_D;
297 case 64:
298 return BRW_REGISTER_TYPE_Q;
299 default:
300 unreachable("Invalid bit size");
301 }
302 case BRW_REGISTER_TYPE_UW:
303 case BRW_REGISTER_TYPE_UD:
304 case BRW_REGISTER_TYPE_UQ:
305 switch(bit_size) {
306 case 16:
307 return BRW_REGISTER_TYPE_UW;
308 case 32:
309 return BRW_REGISTER_TYPE_UD;
310 case 64:
311 return BRW_REGISTER_TYPE_UQ;
312 default:
313 unreachable("Invalid bit size");
314 }
315 default:
316 unreachable("Unknown type");
317 }
318 }
319
320 void
nir_emit_impl(nir_function_impl * impl)321 fs_visitor::nir_emit_impl(nir_function_impl *impl)
322 {
323 nir_locals = ralloc_array(mem_ctx, fs_reg, impl->reg_alloc);
324 for (unsigned i = 0; i < impl->reg_alloc; i++) {
325 nir_locals[i] = fs_reg();
326 }
327
328 foreach_list_typed(nir_register, reg, node, &impl->registers) {
329 unsigned array_elems =
330 reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
331 unsigned size = array_elems * reg->num_components;
332 const brw_reg_type reg_type =
333 brw_reg_type_from_bit_size(reg->bit_size, BRW_REGISTER_TYPE_F);
334 nir_locals[reg->index] = bld.vgrf(reg_type, size);
335 }
336
337 nir_ssa_values = reralloc(mem_ctx, nir_ssa_values, fs_reg,
338 impl->ssa_alloc);
339
340 nir_emit_cf_list(&impl->body);
341 }
342
343 void
nir_emit_cf_list(exec_list * list)344 fs_visitor::nir_emit_cf_list(exec_list *list)
345 {
346 exec_list_validate(list);
347 foreach_list_typed(nir_cf_node, node, node, list) {
348 switch (node->type) {
349 case nir_cf_node_if:
350 nir_emit_if(nir_cf_node_as_if(node));
351 break;
352
353 case nir_cf_node_loop:
354 nir_emit_loop(nir_cf_node_as_loop(node));
355 break;
356
357 case nir_cf_node_block:
358 nir_emit_block(nir_cf_node_as_block(node));
359 break;
360
361 default:
362 unreachable("Invalid CFG node block");
363 }
364 }
365 }
366
367 void
nir_emit_if(nir_if * if_stmt)368 fs_visitor::nir_emit_if(nir_if *if_stmt)
369 {
370 /* first, put the condition into f0 */
371 fs_inst *inst = bld.MOV(bld.null_reg_d(),
372 retype(get_nir_src(if_stmt->condition),
373 BRW_REGISTER_TYPE_D));
374 inst->conditional_mod = BRW_CONDITIONAL_NZ;
375
376 bld.IF(BRW_PREDICATE_NORMAL);
377
378 nir_emit_cf_list(&if_stmt->then_list);
379
380 /* note: if the else is empty, dead CF elimination will remove it */
381 bld.emit(BRW_OPCODE_ELSE);
382
383 nir_emit_cf_list(&if_stmt->else_list);
384
385 bld.emit(BRW_OPCODE_ENDIF);
386 }
387
388 void
nir_emit_loop(nir_loop * loop)389 fs_visitor::nir_emit_loop(nir_loop *loop)
390 {
391 bld.emit(BRW_OPCODE_DO);
392
393 nir_emit_cf_list(&loop->body);
394
395 bld.emit(BRW_OPCODE_WHILE);
396 }
397
398 void
nir_emit_block(nir_block * block)399 fs_visitor::nir_emit_block(nir_block *block)
400 {
401 nir_foreach_instr(instr, block) {
402 nir_emit_instr(instr);
403 }
404 }
405
406 void
nir_emit_instr(nir_instr * instr)407 fs_visitor::nir_emit_instr(nir_instr *instr)
408 {
409 const fs_builder abld = bld.annotate(NULL, instr);
410
411 switch (instr->type) {
412 case nir_instr_type_alu:
413 nir_emit_alu(abld, nir_instr_as_alu(instr));
414 break;
415
416 case nir_instr_type_intrinsic:
417 switch (stage) {
418 case MESA_SHADER_VERTEX:
419 nir_emit_vs_intrinsic(abld, nir_instr_as_intrinsic(instr));
420 break;
421 case MESA_SHADER_TESS_CTRL:
422 nir_emit_tcs_intrinsic(abld, nir_instr_as_intrinsic(instr));
423 break;
424 case MESA_SHADER_TESS_EVAL:
425 nir_emit_tes_intrinsic(abld, nir_instr_as_intrinsic(instr));
426 break;
427 case MESA_SHADER_GEOMETRY:
428 nir_emit_gs_intrinsic(abld, nir_instr_as_intrinsic(instr));
429 break;
430 case MESA_SHADER_FRAGMENT:
431 nir_emit_fs_intrinsic(abld, nir_instr_as_intrinsic(instr));
432 break;
433 case MESA_SHADER_COMPUTE:
434 nir_emit_cs_intrinsic(abld, nir_instr_as_intrinsic(instr));
435 break;
436 default:
437 unreachable("unsupported shader stage");
438 }
439 break;
440
441 case nir_instr_type_tex:
442 nir_emit_texture(abld, nir_instr_as_tex(instr));
443 break;
444
445 case nir_instr_type_load_const:
446 nir_emit_load_const(abld, nir_instr_as_load_const(instr));
447 break;
448
449 case nir_instr_type_ssa_undef:
450 /* We create a new VGRF for undefs on every use (by handling
451 * them in get_nir_src()), rather than for each definition.
452 * This helps register coalescing eliminate MOVs from undef.
453 */
454 break;
455
456 case nir_instr_type_jump:
457 nir_emit_jump(abld, nir_instr_as_jump(instr));
458 break;
459
460 default:
461 unreachable("unknown instruction type");
462 }
463 }
464
465 /**
466 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
467 * match instr.
468 */
469 bool
optimize_extract_to_float(nir_alu_instr * instr,const fs_reg & result)470 fs_visitor::optimize_extract_to_float(nir_alu_instr *instr,
471 const fs_reg &result)
472 {
473 if (!instr->src[0].src.is_ssa ||
474 !instr->src[0].src.ssa->parent_instr)
475 return false;
476
477 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
478 return false;
479
480 nir_alu_instr *src0 =
481 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
482
483 if (src0->op != nir_op_extract_u8 && src0->op != nir_op_extract_u16 &&
484 src0->op != nir_op_extract_i8 && src0->op != nir_op_extract_i16)
485 return false;
486
487 nir_const_value *element = nir_src_as_const_value(src0->src[1].src);
488 assert(element != NULL);
489
490 /* Element type to extract.*/
491 const brw_reg_type type = brw_int_type(
492 src0->op == nir_op_extract_u16 || src0->op == nir_op_extract_i16 ? 2 : 1,
493 src0->op == nir_op_extract_i16 || src0->op == nir_op_extract_i8);
494
495 fs_reg op0 = get_nir_src(src0->src[0].src);
496 op0.type = brw_type_for_nir_type(devinfo,
497 (nir_alu_type)(nir_op_infos[src0->op].input_types[0] |
498 nir_src_bit_size(src0->src[0].src)));
499 op0 = offset(op0, bld, src0->src[0].swizzle[0]);
500
501 set_saturate(instr->dest.saturate,
502 bld.MOV(result, subscript(op0, type, element->u32[0])));
503 return true;
504 }
505
506 bool
optimize_frontfacing_ternary(nir_alu_instr * instr,const fs_reg & result)507 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
508 const fs_reg &result)
509 {
510 if (!instr->src[0].src.is_ssa ||
511 instr->src[0].src.ssa->parent_instr->type != nir_instr_type_intrinsic)
512 return false;
513
514 nir_intrinsic_instr *src0 =
515 nir_instr_as_intrinsic(instr->src[0].src.ssa->parent_instr);
516
517 if (src0->intrinsic != nir_intrinsic_load_front_face)
518 return false;
519
520 nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
521 if (!value1 || fabsf(value1->f32[0]) != 1.0f)
522 return false;
523
524 nir_const_value *value2 = nir_src_as_const_value(instr->src[2].src);
525 if (!value2 || fabsf(value2->f32[0]) != 1.0f)
526 return false;
527
528 fs_reg tmp = vgrf(glsl_type::int_type);
529
530 if (devinfo->gen >= 6) {
531 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
532 fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
533
534 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
535 *
536 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
537 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
538 *
539 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
540 *
541 * This negation looks like it's safe in practice, because bits 0:4 will
542 * surely be TRIANGLES
543 */
544
545 if (value1->f32[0] == -1.0f) {
546 g0.negate = true;
547 }
548
549 bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1),
550 g0, brw_imm_uw(0x3f80));
551 } else {
552 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
553 fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
554
555 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
556 *
557 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
558 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
559 *
560 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
561 *
562 * This negation looks like it's safe in practice, because bits 0:4 will
563 * surely be TRIANGLES
564 */
565
566 if (value1->f32[0] == -1.0f) {
567 g1_6.negate = true;
568 }
569
570 bld.OR(tmp, g1_6, brw_imm_d(0x3f800000));
571 }
572 bld.AND(retype(result, BRW_REGISTER_TYPE_D), tmp, brw_imm_d(0xbf800000));
573
574 return true;
575 }
576
577 static void
emit_find_msb_using_lzd(const fs_builder & bld,const fs_reg & result,const fs_reg & src,bool is_signed)578 emit_find_msb_using_lzd(const fs_builder &bld,
579 const fs_reg &result,
580 const fs_reg &src,
581 bool is_signed)
582 {
583 fs_inst *inst;
584 fs_reg temp = src;
585
586 if (is_signed) {
587 /* LZD of an absolute value source almost always does the right
588 * thing. There are two problem values:
589 *
590 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
591 * 0. However, findMSB(int(0x80000000)) == 30.
592 *
593 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
594 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
595 *
596 * For a value of zero or negative one, -1 will be returned.
597 *
598 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
599 * findMSB(-(1<<x)) should return x-1.
600 *
601 * For all negative number cases, including 0x80000000 and
602 * 0xffffffff, the correct value is obtained from LZD if instead of
603 * negating the (already negative) value the logical-not is used. A
604 * conditonal logical-not can be achieved in two instructions.
605 */
606 temp = bld.vgrf(BRW_REGISTER_TYPE_D);
607
608 bld.ASR(temp, src, brw_imm_d(31));
609 bld.XOR(temp, temp, src);
610 }
611
612 bld.LZD(retype(result, BRW_REGISTER_TYPE_UD),
613 retype(temp, BRW_REGISTER_TYPE_UD));
614
615 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
616 * from the LSB side. Subtract the result from 31 to convert the MSB
617 * count into an LSB count. If no bits are set, LZD will return 32.
618 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
619 */
620 inst = bld.ADD(result, retype(result, BRW_REGISTER_TYPE_D), brw_imm_d(31));
621 inst->src[0].negate = true;
622 }
623
624 static brw_rnd_mode
brw_rnd_mode_from_nir_op(const nir_op op)625 brw_rnd_mode_from_nir_op (const nir_op op) {
626 switch (op) {
627 case nir_op_f2f16_rtz:
628 return BRW_RND_MODE_RTZ;
629 case nir_op_f2f16_rtne:
630 return BRW_RND_MODE_RTNE;
631 default:
632 unreachable("Operation doesn't support rounding mode");
633 }
634 }
635
636 void
nir_emit_alu(const fs_builder & bld,nir_alu_instr * instr)637 fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
638 {
639 struct brw_wm_prog_key *fs_key = (struct brw_wm_prog_key *) this->key;
640 fs_inst *inst;
641
642 fs_reg result = get_nir_dest(instr->dest.dest);
643 result.type = brw_type_for_nir_type(devinfo,
644 (nir_alu_type)(nir_op_infos[instr->op].output_type |
645 nir_dest_bit_size(instr->dest.dest)));
646
647 fs_reg op[4];
648 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
649 op[i] = get_nir_src(instr->src[i].src);
650 op[i].type = brw_type_for_nir_type(devinfo,
651 (nir_alu_type)(nir_op_infos[instr->op].input_types[i] |
652 nir_src_bit_size(instr->src[i].src)));
653 op[i].abs = instr->src[i].abs;
654 op[i].negate = instr->src[i].negate;
655 }
656
657 /* We get a bunch of mov's out of the from_ssa pass and they may still
658 * be vectorized. We'll handle them as a special-case. We'll also
659 * handle vecN here because it's basically the same thing.
660 */
661 switch (instr->op) {
662 case nir_op_imov:
663 case nir_op_fmov:
664 case nir_op_vec2:
665 case nir_op_vec3:
666 case nir_op_vec4: {
667 fs_reg temp = result;
668 bool need_extra_copy = false;
669 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
670 if (!instr->src[i].src.is_ssa &&
671 instr->dest.dest.reg.reg == instr->src[i].src.reg.reg) {
672 need_extra_copy = true;
673 temp = bld.vgrf(result.type, 4);
674 break;
675 }
676 }
677
678 for (unsigned i = 0; i < 4; i++) {
679 if (!(instr->dest.write_mask & (1 << i)))
680 continue;
681
682 if (instr->op == nir_op_imov || instr->op == nir_op_fmov) {
683 inst = bld.MOV(offset(temp, bld, i),
684 offset(op[0], bld, instr->src[0].swizzle[i]));
685 } else {
686 inst = bld.MOV(offset(temp, bld, i),
687 offset(op[i], bld, instr->src[i].swizzle[0]));
688 }
689 inst->saturate = instr->dest.saturate;
690 }
691
692 /* In this case the source and destination registers were the same,
693 * so we need to insert an extra set of moves in order to deal with
694 * any swizzling.
695 */
696 if (need_extra_copy) {
697 for (unsigned i = 0; i < 4; i++) {
698 if (!(instr->dest.write_mask & (1 << i)))
699 continue;
700
701 bld.MOV(offset(result, bld, i), offset(temp, bld, i));
702 }
703 }
704 return;
705 }
706 default:
707 break;
708 }
709
710 /* At this point, we have dealt with any instruction that operates on
711 * more than a single channel. Therefore, we can just adjust the source
712 * and destination registers for that channel and emit the instruction.
713 */
714 unsigned channel = 0;
715 if (nir_op_infos[instr->op].output_size == 0) {
716 /* Since NIR is doing the scalarizing for us, we should only ever see
717 * vectorized operations with a single channel.
718 */
719 assert(_mesa_bitcount(instr->dest.write_mask) == 1);
720 channel = ffs(instr->dest.write_mask) - 1;
721
722 result = offset(result, bld, channel);
723 }
724
725 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
726 assert(nir_op_infos[instr->op].input_sizes[i] < 2);
727 op[i] = offset(op[i], bld, instr->src[i].swizzle[channel]);
728 }
729
730 switch (instr->op) {
731 case nir_op_i2f32:
732 case nir_op_u2f32:
733 if (optimize_extract_to_float(instr, result))
734 return;
735 inst = bld.MOV(result, op[0]);
736 inst->saturate = instr->dest.saturate;
737 break;
738
739 case nir_op_f2f16_rtne:
740 case nir_op_f2f16_rtz:
741 bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
742 brw_imm_d(brw_rnd_mode_from_nir_op(instr->op)));
743 /* fallthrough */
744
745 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
746 * on the HW gen, it is a special hw opcode or just a MOV, and
747 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
748 *
749 * But if we want to use that opcode, we need to provide support on
750 * different optimizations and lowerings. As right now HF support is
751 * only for gen8+, it will be better to use directly the MOV, and use
752 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
753 */
754
755 case nir_op_f2f16_undef:
756 case nir_op_i2i16:
757 case nir_op_u2u16: {
758 /* TODO: Fixing aligment rules for conversions from 32-bits to
759 * 16-bit types should be moved to lower_conversions
760 */
761 fs_reg tmp = bld.vgrf(op[0].type, 1);
762 tmp = subscript(tmp, result.type, 0);
763 inst = bld.MOV(tmp, op[0]);
764 inst->saturate = instr->dest.saturate;
765 inst = bld.MOV(result, tmp);
766 inst->saturate = instr->dest.saturate;
767 break;
768 }
769
770 case nir_op_f2f64:
771 case nir_op_f2i64:
772 case nir_op_f2u64:
773 case nir_op_i2f64:
774 case nir_op_i2i64:
775 case nir_op_u2f64:
776 case nir_op_u2u64:
777 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
778 *
779 * "When source or destination is 64b (...), regioning in Align1
780 * must follow these rules:
781 *
782 * 1. Source and destination horizontal stride must be aligned to
783 * the same qword.
784 * (...)"
785 *
786 * This means that 32-bit to 64-bit conversions need to have the 32-bit
787 * data elements aligned to 64-bit. This restriction does not apply to
788 * BDW and later.
789 */
790 if (nir_dest_bit_size(instr->dest.dest) == 64 &&
791 nir_src_bit_size(instr->src[0].src) == 32 &&
792 (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
793 fs_reg tmp = bld.vgrf(result.type, 1);
794 tmp = subscript(tmp, op[0].type, 0);
795 inst = bld.MOV(tmp, op[0]);
796 inst = bld.MOV(result, tmp);
797 inst->saturate = instr->dest.saturate;
798 break;
799 }
800 /* fallthrough */
801 case nir_op_f2f32:
802 case nir_op_f2i32:
803 case nir_op_f2u32:
804 case nir_op_i2i32:
805 case nir_op_u2u32:
806 inst = bld.MOV(result, op[0]);
807 inst->saturate = instr->dest.saturate;
808 break;
809
810 case nir_op_fsign: {
811 if (op[0].abs) {
812 /* Straightforward since the source can be assumed to be
813 * non-negative.
814 */
815 set_condmod(BRW_CONDITIONAL_NZ, bld.MOV(result, op[0]));
816 set_predicate(BRW_PREDICATE_NORMAL, bld.MOV(result, brw_imm_f(1.0f)));
817
818 } else if (type_sz(op[0].type) < 8) {
819 /* AND(val, 0x80000000) gives the sign bit.
820 *
821 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
822 * zero.
823 */
824 bld.CMP(bld.null_reg_f(), op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);
825
826 fs_reg result_int = retype(result, BRW_REGISTER_TYPE_UD);
827 op[0].type = BRW_REGISTER_TYPE_UD;
828 result.type = BRW_REGISTER_TYPE_UD;
829 bld.AND(result_int, op[0], brw_imm_ud(0x80000000u));
830
831 inst = bld.OR(result_int, result_int, brw_imm_ud(0x3f800000u));
832 inst->predicate = BRW_PREDICATE_NORMAL;
833 if (instr->dest.saturate) {
834 inst = bld.MOV(result, result);
835 inst->saturate = true;
836 }
837 } else {
838 /* For doubles we do the same but we need to consider:
839 *
840 * - 2-src instructions can't operate with 64-bit immediates
841 * - The sign is encoded in the high 32-bit of each DF
842 * - We need to produce a DF result.
843 */
844
845 fs_reg zero = vgrf(glsl_type::double_type);
846 bld.MOV(zero, setup_imm_df(bld, 0.0));
847 bld.CMP(bld.null_reg_df(), op[0], zero, BRW_CONDITIONAL_NZ);
848
849 bld.MOV(result, zero);
850
851 fs_reg r = subscript(result, BRW_REGISTER_TYPE_UD, 1);
852 bld.AND(r, subscript(op[0], BRW_REGISTER_TYPE_UD, 1),
853 brw_imm_ud(0x80000000u));
854
855 set_predicate(BRW_PREDICATE_NORMAL,
856 bld.OR(r, r, brw_imm_ud(0x3ff00000u)));
857
858 if (instr->dest.saturate) {
859 inst = bld.MOV(result, result);
860 inst->saturate = true;
861 }
862 }
863 break;
864 }
865
866 case nir_op_isign:
867 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
868 * -> non-negative val generates 0x00000000.
869 * Predicated OR sets 1 if val is positive.
870 */
871 assert(nir_dest_bit_size(instr->dest.dest) < 64);
872 bld.CMP(bld.null_reg_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_G);
873 bld.ASR(result, op[0], brw_imm_d(31));
874 inst = bld.OR(result, result, brw_imm_d(1));
875 inst->predicate = BRW_PREDICATE_NORMAL;
876 break;
877
878 case nir_op_frcp:
879 inst = bld.emit(SHADER_OPCODE_RCP, result, op[0]);
880 inst->saturate = instr->dest.saturate;
881 break;
882
883 case nir_op_fexp2:
884 inst = bld.emit(SHADER_OPCODE_EXP2, result, op[0]);
885 inst->saturate = instr->dest.saturate;
886 break;
887
888 case nir_op_flog2:
889 inst = bld.emit(SHADER_OPCODE_LOG2, result, op[0]);
890 inst->saturate = instr->dest.saturate;
891 break;
892
893 case nir_op_fsin:
894 inst = bld.emit(SHADER_OPCODE_SIN, result, op[0]);
895 inst->saturate = instr->dest.saturate;
896 break;
897
898 case nir_op_fcos:
899 inst = bld.emit(SHADER_OPCODE_COS, result, op[0]);
900 inst->saturate = instr->dest.saturate;
901 break;
902
903 case nir_op_fddx:
904 if (fs_key->high_quality_derivatives) {
905 inst = bld.emit(FS_OPCODE_DDX_FINE, result, op[0]);
906 } else {
907 inst = bld.emit(FS_OPCODE_DDX_COARSE, result, op[0]);
908 }
909 inst->saturate = instr->dest.saturate;
910 break;
911 case nir_op_fddx_fine:
912 inst = bld.emit(FS_OPCODE_DDX_FINE, result, op[0]);
913 inst->saturate = instr->dest.saturate;
914 break;
915 case nir_op_fddx_coarse:
916 inst = bld.emit(FS_OPCODE_DDX_COARSE, result, op[0]);
917 inst->saturate = instr->dest.saturate;
918 break;
919 case nir_op_fddy:
920 if (fs_key->high_quality_derivatives) {
921 inst = bld.emit(FS_OPCODE_DDY_FINE, result, op[0]);
922 } else {
923 inst = bld.emit(FS_OPCODE_DDY_COARSE, result, op[0]);
924 }
925 inst->saturate = instr->dest.saturate;
926 break;
927 case nir_op_fddy_fine:
928 inst = bld.emit(FS_OPCODE_DDY_FINE, result, op[0]);
929 inst->saturate = instr->dest.saturate;
930 break;
931 case nir_op_fddy_coarse:
932 inst = bld.emit(FS_OPCODE_DDY_COARSE, result, op[0]);
933 inst->saturate = instr->dest.saturate;
934 break;
935
936 case nir_op_iadd:
937 case nir_op_fadd:
938 inst = bld.ADD(result, op[0], op[1]);
939 inst->saturate = instr->dest.saturate;
940 break;
941
942 case nir_op_fmul:
943 inst = bld.MUL(result, op[0], op[1]);
944 inst->saturate = instr->dest.saturate;
945 break;
946
947 case nir_op_imul:
948 assert(nir_dest_bit_size(instr->dest.dest) < 64);
949 bld.MUL(result, op[0], op[1]);
950 break;
951
952 case nir_op_imul_high:
953 case nir_op_umul_high:
954 assert(nir_dest_bit_size(instr->dest.dest) < 64);
955 bld.emit(SHADER_OPCODE_MULH, result, op[0], op[1]);
956 break;
957
958 case nir_op_idiv:
959 case nir_op_udiv:
960 assert(nir_dest_bit_size(instr->dest.dest) < 64);
961 bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
962 break;
963
964 case nir_op_uadd_carry:
965 unreachable("Should have been lowered by carry_to_arith().");
966
967 case nir_op_usub_borrow:
968 unreachable("Should have been lowered by borrow_to_arith().");
969
970 case nir_op_umod:
971 case nir_op_irem:
972 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
973 * appears that our hardware just does the right thing for signed
974 * remainder.
975 */
976 assert(nir_dest_bit_size(instr->dest.dest) < 64);
977 bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
978 break;
979
980 case nir_op_imod: {
981 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
982 bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
983
984 /* Math instructions don't support conditional mod */
985 inst = bld.MOV(bld.null_reg_d(), result);
986 inst->conditional_mod = BRW_CONDITIONAL_NZ;
987
988 /* Now, we need to determine if signs of the sources are different.
989 * When we XOR the sources, the top bit is 0 if they are the same and 1
990 * if they are different. We can then use a conditional modifier to
991 * turn that into a predicate. This leads us to an XOR.l instruction.
992 *
993 * Technically, according to the PRM, you're not allowed to use .l on a
994 * XOR instruction. However, emperical experiments and Curro's reading
995 * of the simulator source both indicate that it's safe.
996 */
997 fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D);
998 inst = bld.XOR(tmp, op[0], op[1]);
999 inst->predicate = BRW_PREDICATE_NORMAL;
1000 inst->conditional_mod = BRW_CONDITIONAL_L;
1001
1002 /* If the result of the initial remainder operation is non-zero and the
1003 * two sources have different signs, add in a copy of op[1] to get the
1004 * final integer modulus value.
1005 */
1006 inst = bld.ADD(result, result, op[1]);
1007 inst->predicate = BRW_PREDICATE_NORMAL;
1008 break;
1009 }
1010
1011 case nir_op_flt:
1012 case nir_op_fge:
1013 case nir_op_feq:
1014 case nir_op_fne: {
1015 fs_reg dest = result;
1016 if (nir_src_bit_size(instr->src[0].src) > 32) {
1017 dest = bld.vgrf(BRW_REGISTER_TYPE_DF, 1);
1018 }
1019 brw_conditional_mod cond;
1020 switch (instr->op) {
1021 case nir_op_flt:
1022 cond = BRW_CONDITIONAL_L;
1023 break;
1024 case nir_op_fge:
1025 cond = BRW_CONDITIONAL_GE;
1026 break;
1027 case nir_op_feq:
1028 cond = BRW_CONDITIONAL_Z;
1029 break;
1030 case nir_op_fne:
1031 cond = BRW_CONDITIONAL_NZ;
1032 break;
1033 default:
1034 unreachable("bad opcode");
1035 }
1036 bld.CMP(dest, op[0], op[1], cond);
1037 if (nir_src_bit_size(instr->src[0].src) > 32) {
1038 bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
1039 }
1040 break;
1041 }
1042
1043 case nir_op_ilt:
1044 case nir_op_ult:
1045 case nir_op_ige:
1046 case nir_op_uge:
1047 case nir_op_ieq:
1048 case nir_op_ine: {
1049 fs_reg dest = result;
1050 if (nir_src_bit_size(instr->src[0].src) > 32) {
1051 dest = bld.vgrf(BRW_REGISTER_TYPE_UQ, 1);
1052 }
1053
1054 brw_conditional_mod cond;
1055 switch (instr->op) {
1056 case nir_op_ilt:
1057 case nir_op_ult:
1058 cond = BRW_CONDITIONAL_L;
1059 break;
1060 case nir_op_ige:
1061 case nir_op_uge:
1062 cond = BRW_CONDITIONAL_GE;
1063 break;
1064 case nir_op_ieq:
1065 cond = BRW_CONDITIONAL_Z;
1066 break;
1067 case nir_op_ine:
1068 cond = BRW_CONDITIONAL_NZ;
1069 break;
1070 default:
1071 unreachable("bad opcode");
1072 }
1073 bld.CMP(dest, op[0], op[1], cond);
1074 if (nir_src_bit_size(instr->src[0].src) > 32) {
1075 bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
1076 }
1077 break;
1078 }
1079
1080 case nir_op_inot:
1081 if (devinfo->gen >= 8) {
1082 op[0] = resolve_source_modifiers(op[0]);
1083 }
1084 bld.NOT(result, op[0]);
1085 break;
1086 case nir_op_ixor:
1087 if (devinfo->gen >= 8) {
1088 op[0] = resolve_source_modifiers(op[0]);
1089 op[1] = resolve_source_modifiers(op[1]);
1090 }
1091 bld.XOR(result, op[0], op[1]);
1092 break;
1093 case nir_op_ior:
1094 if (devinfo->gen >= 8) {
1095 op[0] = resolve_source_modifiers(op[0]);
1096 op[1] = resolve_source_modifiers(op[1]);
1097 }
1098 bld.OR(result, op[0], op[1]);
1099 break;
1100 case nir_op_iand:
1101 if (devinfo->gen >= 8) {
1102 op[0] = resolve_source_modifiers(op[0]);
1103 op[1] = resolve_source_modifiers(op[1]);
1104 }
1105 bld.AND(result, op[0], op[1]);
1106 break;
1107
1108 case nir_op_fdot2:
1109 case nir_op_fdot3:
1110 case nir_op_fdot4:
1111 case nir_op_ball_fequal2:
1112 case nir_op_ball_iequal2:
1113 case nir_op_ball_fequal3:
1114 case nir_op_ball_iequal3:
1115 case nir_op_ball_fequal4:
1116 case nir_op_ball_iequal4:
1117 case nir_op_bany_fnequal2:
1118 case nir_op_bany_inequal2:
1119 case nir_op_bany_fnequal3:
1120 case nir_op_bany_inequal3:
1121 case nir_op_bany_fnequal4:
1122 case nir_op_bany_inequal4:
1123 unreachable("Lowered by nir_lower_alu_reductions");
1124
1125 case nir_op_fnoise1_1:
1126 case nir_op_fnoise1_2:
1127 case nir_op_fnoise1_3:
1128 case nir_op_fnoise1_4:
1129 case nir_op_fnoise2_1:
1130 case nir_op_fnoise2_2:
1131 case nir_op_fnoise2_3:
1132 case nir_op_fnoise2_4:
1133 case nir_op_fnoise3_1:
1134 case nir_op_fnoise3_2:
1135 case nir_op_fnoise3_3:
1136 case nir_op_fnoise3_4:
1137 case nir_op_fnoise4_1:
1138 case nir_op_fnoise4_2:
1139 case nir_op_fnoise4_3:
1140 case nir_op_fnoise4_4:
1141 unreachable("not reached: should be handled by lower_noise");
1142
1143 case nir_op_ldexp:
1144 unreachable("not reached: should be handled by ldexp_to_arith()");
1145
1146 case nir_op_fsqrt:
1147 inst = bld.emit(SHADER_OPCODE_SQRT, result, op[0]);
1148 inst->saturate = instr->dest.saturate;
1149 break;
1150
1151 case nir_op_frsq:
1152 inst = bld.emit(SHADER_OPCODE_RSQ, result, op[0]);
1153 inst->saturate = instr->dest.saturate;
1154 break;
1155
1156 case nir_op_b2i:
1157 case nir_op_b2f:
1158 bld.MOV(result, negate(op[0]));
1159 break;
1160
1161 case nir_op_i2b:
1162 case nir_op_f2b:
1163 if (nir_src_bit_size(instr->src[0].src) == 64) {
1164 /* two-argument instructions can't take 64-bit immediates */
1165 fs_reg zero;
1166 fs_reg tmp;
1167
1168 if (instr->op == nir_op_f2b) {
1169 zero = vgrf(glsl_type::double_type);
1170 tmp = vgrf(glsl_type::double_type);
1171 bld.MOV(zero, setup_imm_df(bld, 0.0));
1172 } else {
1173 zero = vgrf(glsl_type::int64_t_type);
1174 tmp = vgrf(glsl_type::int64_t_type);
1175 bld.MOV(zero, brw_imm_q(0));
1176 }
1177
1178 /* A SIMD16 execution needs to be split in two instructions, so use
1179 * a vgrf instead of the flag register as dst so instruction splitting
1180 * works
1181 */
1182 bld.CMP(tmp, op[0], zero, BRW_CONDITIONAL_NZ);
1183 bld.MOV(result, subscript(tmp, BRW_REGISTER_TYPE_UD, 0));
1184 } else {
1185 if (instr->op == nir_op_f2b) {
1186 bld.CMP(result, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);
1187 } else {
1188 bld.CMP(result, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ);
1189 }
1190 }
1191 break;
1192
1193 case nir_op_ftrunc:
1194 inst = bld.RNDZ(result, op[0]);
1195 inst->saturate = instr->dest.saturate;
1196 break;
1197
1198 case nir_op_fceil: {
1199 op[0].negate = !op[0].negate;
1200 fs_reg temp = vgrf(glsl_type::float_type);
1201 bld.RNDD(temp, op[0]);
1202 temp.negate = true;
1203 inst = bld.MOV(result, temp);
1204 inst->saturate = instr->dest.saturate;
1205 break;
1206 }
1207 case nir_op_ffloor:
1208 inst = bld.RNDD(result, op[0]);
1209 inst->saturate = instr->dest.saturate;
1210 break;
1211 case nir_op_ffract:
1212 inst = bld.FRC(result, op[0]);
1213 inst->saturate = instr->dest.saturate;
1214 break;
1215 case nir_op_fround_even:
1216 inst = bld.RNDE(result, op[0]);
1217 inst->saturate = instr->dest.saturate;
1218 break;
1219
1220 case nir_op_fquantize2f16: {
1221 fs_reg tmp16 = bld.vgrf(BRW_REGISTER_TYPE_D);
1222 fs_reg tmp32 = bld.vgrf(BRW_REGISTER_TYPE_F);
1223 fs_reg zero = bld.vgrf(BRW_REGISTER_TYPE_F);
1224
1225 /* The destination stride must be at least as big as the source stride. */
1226 tmp16.type = BRW_REGISTER_TYPE_W;
1227 tmp16.stride = 2;
1228
1229 /* Check for denormal */
1230 fs_reg abs_src0 = op[0];
1231 abs_src0.abs = true;
1232 bld.CMP(bld.null_reg_f(), abs_src0, brw_imm_f(ldexpf(1.0, -14)),
1233 BRW_CONDITIONAL_L);
1234 /* Get the appropriately signed zero */
1235 bld.AND(retype(zero, BRW_REGISTER_TYPE_UD),
1236 retype(op[0], BRW_REGISTER_TYPE_UD),
1237 brw_imm_ud(0x80000000));
1238 /* Do the actual F32 -> F16 -> F32 conversion */
1239 bld.emit(BRW_OPCODE_F32TO16, tmp16, op[0]);
1240 bld.emit(BRW_OPCODE_F16TO32, tmp32, tmp16);
1241 /* Select that or zero based on normal status */
1242 inst = bld.SEL(result, zero, tmp32);
1243 inst->predicate = BRW_PREDICATE_NORMAL;
1244 inst->saturate = instr->dest.saturate;
1245 break;
1246 }
1247
1248 case nir_op_imin:
1249 case nir_op_umin:
1250 case nir_op_fmin:
1251 inst = bld.emit_minmax(result, op[0], op[1], BRW_CONDITIONAL_L);
1252 inst->saturate = instr->dest.saturate;
1253 break;
1254
1255 case nir_op_imax:
1256 case nir_op_umax:
1257 case nir_op_fmax:
1258 inst = bld.emit_minmax(result, op[0], op[1], BRW_CONDITIONAL_GE);
1259 inst->saturate = instr->dest.saturate;
1260 break;
1261
1262 case nir_op_pack_snorm_2x16:
1263 case nir_op_pack_snorm_4x8:
1264 case nir_op_pack_unorm_2x16:
1265 case nir_op_pack_unorm_4x8:
1266 case nir_op_unpack_snorm_2x16:
1267 case nir_op_unpack_snorm_4x8:
1268 case nir_op_unpack_unorm_2x16:
1269 case nir_op_unpack_unorm_4x8:
1270 case nir_op_unpack_half_2x16:
1271 case nir_op_pack_half_2x16:
1272 unreachable("not reached: should be handled by lower_packing_builtins");
1273
1274 case nir_op_unpack_half_2x16_split_x:
1275 inst = bld.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, result, op[0]);
1276 inst->saturate = instr->dest.saturate;
1277 break;
1278 case nir_op_unpack_half_2x16_split_y:
1279 inst = bld.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, result, op[0]);
1280 inst->saturate = instr->dest.saturate;
1281 break;
1282
1283 case nir_op_pack_64_2x32_split:
1284 bld.emit(FS_OPCODE_PACK, result, op[0], op[1]);
1285 break;
1286
1287 case nir_op_unpack_64_2x32_split_x:
1288 case nir_op_unpack_64_2x32_split_y: {
1289 if (instr->op == nir_op_unpack_64_2x32_split_x)
1290 bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UD, 0));
1291 else
1292 bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UD, 1));
1293 break;
1294 }
1295
1296 case nir_op_fpow:
1297 inst = bld.emit(SHADER_OPCODE_POW, result, op[0], op[1]);
1298 inst->saturate = instr->dest.saturate;
1299 break;
1300
1301 case nir_op_bitfield_reverse:
1302 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1303 bld.BFREV(result, op[0]);
1304 break;
1305
1306 case nir_op_bit_count:
1307 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1308 bld.CBIT(result, op[0]);
1309 break;
1310
1311 case nir_op_ufind_msb: {
1312 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1313 emit_find_msb_using_lzd(bld, result, op[0], false);
1314 break;
1315 }
1316
1317 case nir_op_ifind_msb: {
1318 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1319
1320 if (devinfo->gen < 7) {
1321 emit_find_msb_using_lzd(bld, result, op[0], true);
1322 } else {
1323 bld.FBH(retype(result, BRW_REGISTER_TYPE_UD), op[0]);
1324
1325 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1326 * count from the LSB side. If FBH didn't return an error
1327 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1328 * count into an LSB count.
1329 */
1330 bld.CMP(bld.null_reg_d(), result, brw_imm_d(-1), BRW_CONDITIONAL_NZ);
1331
1332 inst = bld.ADD(result, result, brw_imm_d(31));
1333 inst->predicate = BRW_PREDICATE_NORMAL;
1334 inst->src[0].negate = true;
1335 }
1336 break;
1337 }
1338
1339 case nir_op_find_lsb:
1340 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1341
1342 if (devinfo->gen < 7) {
1343 fs_reg temp = vgrf(glsl_type::int_type);
1344
1345 /* (x & -x) generates a value that consists of only the LSB of x.
1346 * For all powers of 2, findMSB(y) == findLSB(y).
1347 */
1348 fs_reg src = retype(op[0], BRW_REGISTER_TYPE_D);
1349 fs_reg negated_src = src;
1350
1351 /* One must be negated, and the other must be non-negated. It
1352 * doesn't matter which is which.
1353 */
1354 negated_src.negate = true;
1355 src.negate = false;
1356
1357 bld.AND(temp, src, negated_src);
1358 emit_find_msb_using_lzd(bld, result, temp, false);
1359 } else {
1360 bld.FBL(result, op[0]);
1361 }
1362 break;
1363
1364 case nir_op_ubitfield_extract:
1365 case nir_op_ibitfield_extract:
1366 unreachable("should have been lowered");
1367 case nir_op_ubfe:
1368 case nir_op_ibfe:
1369 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1370 bld.BFE(result, op[2], op[1], op[0]);
1371 break;
1372 case nir_op_bfm:
1373 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1374 bld.BFI1(result, op[0], op[1]);
1375 break;
1376 case nir_op_bfi:
1377 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1378 bld.BFI2(result, op[0], op[1], op[2]);
1379 break;
1380
1381 case nir_op_bitfield_insert:
1382 unreachable("not reached: should have been lowered");
1383
1384 case nir_op_ishl:
1385 case nir_op_ishr:
1386 case nir_op_ushr: {
1387 fs_reg shift_count = op[1];
1388
1389 if (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo)) {
1390 if (op[1].file == VGRF &&
1391 (result.type == BRW_REGISTER_TYPE_Q ||
1392 result.type == BRW_REGISTER_TYPE_UQ)) {
1393 shift_count = fs_reg(VGRF, alloc.allocate(dispatch_width / 4),
1394 BRW_REGISTER_TYPE_UD);
1395 shift_count.stride = 2;
1396 bld.MOV(shift_count, op[1]);
1397 }
1398 }
1399
1400 switch (instr->op) {
1401 case nir_op_ishl:
1402 bld.SHL(result, op[0], shift_count);
1403 break;
1404 case nir_op_ishr:
1405 bld.ASR(result, op[0], shift_count);
1406 break;
1407 case nir_op_ushr:
1408 bld.SHR(result, op[0], shift_count);
1409 break;
1410 default:
1411 unreachable("not reached");
1412 }
1413 break;
1414 }
1415
1416 case nir_op_pack_half_2x16_split:
1417 bld.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, result, op[0], op[1]);
1418 break;
1419
1420 case nir_op_ffma:
1421 inst = bld.MAD(result, op[2], op[1], op[0]);
1422 inst->saturate = instr->dest.saturate;
1423 break;
1424
1425 case nir_op_flrp:
1426 inst = bld.LRP(result, op[0], op[1], op[2]);
1427 inst->saturate = instr->dest.saturate;
1428 break;
1429
1430 case nir_op_bcsel:
1431 if (optimize_frontfacing_ternary(instr, result))
1432 return;
1433
1434 bld.CMP(bld.null_reg_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ);
1435 inst = bld.SEL(result, op[1], op[2]);
1436 inst->predicate = BRW_PREDICATE_NORMAL;
1437 break;
1438
1439 case nir_op_extract_u8:
1440 case nir_op_extract_i8: {
1441 nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
1442 assert(byte != NULL);
1443
1444 /* The PRMs say:
1445 *
1446 * BDW+
1447 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1448 * Use two instructions and a word or DWord intermediate integer type.
1449 */
1450 if (nir_dest_bit_size(instr->dest.dest) == 64) {
1451 const brw_reg_type type = brw_int_type(2, instr->op == nir_op_extract_i8);
1452
1453 if (instr->op == nir_op_extract_i8) {
1454 /* If we need to sign extend, extract to a word first */
1455 fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W);
1456 bld.MOV(w_temp, subscript(op[0], type, byte->u32[0]));
1457 bld.MOV(result, w_temp);
1458 } else {
1459 /* Otherwise use an AND with 0xff and a word type */
1460 bld.AND(result, subscript(op[0], type, byte->u32[0] / 2), brw_imm_uw(0xff));
1461 }
1462 } else {
1463 const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8);
1464 bld.MOV(result, subscript(op[0], type, byte->u32[0]));
1465 }
1466 break;
1467 }
1468
1469 case nir_op_extract_u16:
1470 case nir_op_extract_i16: {
1471 const brw_reg_type type = brw_int_type(2, instr->op == nir_op_extract_i16);
1472 nir_const_value *word = nir_src_as_const_value(instr->src[1].src);
1473 assert(word != NULL);
1474 bld.MOV(result, subscript(op[0], type, word->u32[0]));
1475 break;
1476 }
1477
1478 default:
1479 unreachable("unhandled instruction");
1480 }
1481
1482 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1483 * to sign extend the low bit to 0/~0
1484 */
1485 if (devinfo->gen <= 5 &&
1486 (instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
1487 fs_reg masked = vgrf(glsl_type::int_type);
1488 bld.AND(masked, result, brw_imm_d(1));
1489 masked.negate = true;
1490 bld.MOV(retype(result, BRW_REGISTER_TYPE_D), masked);
1491 }
1492 }
1493
1494 void
nir_emit_load_const(const fs_builder & bld,nir_load_const_instr * instr)1495 fs_visitor::nir_emit_load_const(const fs_builder &bld,
1496 nir_load_const_instr *instr)
1497 {
1498 const brw_reg_type reg_type =
1499 brw_reg_type_from_bit_size(instr->def.bit_size, BRW_REGISTER_TYPE_D);
1500 fs_reg reg = bld.vgrf(reg_type, instr->def.num_components);
1501
1502 switch (instr->def.bit_size) {
1503 case 32:
1504 for (unsigned i = 0; i < instr->def.num_components; i++)
1505 bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i32[i]));
1506 break;
1507
1508 case 64:
1509 assert(devinfo->gen >= 7);
1510 if (devinfo->gen == 7) {
1511 /* We don't get 64-bit integer types until gen8 */
1512 for (unsigned i = 0; i < instr->def.num_components; i++) {
1513 bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_DF),
1514 setup_imm_df(bld, instr->value.f64[i]));
1515 }
1516 } else {
1517 for (unsigned i = 0; i < instr->def.num_components; i++)
1518 bld.MOV(offset(reg, bld, i), brw_imm_q(instr->value.i64[i]));
1519 }
1520 break;
1521
1522 default:
1523 unreachable("Invalid bit size");
1524 }
1525
1526 nir_ssa_values[instr->def.index] = reg;
1527 }
1528
1529 fs_reg
get_nir_src(const nir_src & src)1530 fs_visitor::get_nir_src(const nir_src &src)
1531 {
1532 fs_reg reg;
1533 if (src.is_ssa) {
1534 if (src.ssa->parent_instr->type == nir_instr_type_ssa_undef) {
1535 const brw_reg_type reg_type =
1536 brw_reg_type_from_bit_size(src.ssa->bit_size, BRW_REGISTER_TYPE_D);
1537 reg = bld.vgrf(reg_type, src.ssa->num_components);
1538 } else {
1539 reg = nir_ssa_values[src.ssa->index];
1540 }
1541 } else {
1542 /* We don't handle indirects on locals */
1543 assert(src.reg.indirect == NULL);
1544 reg = offset(nir_locals[src.reg.reg->index], bld,
1545 src.reg.base_offset * src.reg.reg->num_components);
1546 }
1547
1548 if (nir_src_bit_size(src) == 64 && devinfo->gen == 7) {
1549 /* The only 64-bit type available on gen7 is DF, so use that. */
1550 reg.type = BRW_REGISTER_TYPE_DF;
1551 } else {
1552 /* To avoid floating-point denorm flushing problems, set the type by
1553 * default to an integer type - instructions that need floating point
1554 * semantics will set this to F if they need to
1555 */
1556 reg.type = brw_reg_type_from_bit_size(nir_src_bit_size(src),
1557 BRW_REGISTER_TYPE_D);
1558 }
1559
1560 return reg;
1561 }
1562
1563 /**
1564 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1565 *
1566 * This function should not be called on any value which may be 64 bits.
1567 * We could theoretically support 64-bit on gen8+ but we choose not to
1568 * because it wouldn't work in general (no gen7 support) and there are
1569 * enough restrictions in 64-bit immediates that you can't take the return
1570 * value and treat it the same as the result of get_nir_src().
1571 */
1572 fs_reg
get_nir_src_imm(const nir_src & src)1573 fs_visitor::get_nir_src_imm(const nir_src &src)
1574 {
1575 nir_const_value *val = nir_src_as_const_value(src);
1576 assert(nir_src_bit_size(src) == 32);
1577 return val ? fs_reg(brw_imm_d(val->i32[0])) : get_nir_src(src);
1578 }
1579
1580 fs_reg
get_nir_dest(const nir_dest & dest)1581 fs_visitor::get_nir_dest(const nir_dest &dest)
1582 {
1583 if (dest.is_ssa) {
1584 const brw_reg_type reg_type =
1585 brw_reg_type_from_bit_size(dest.ssa.bit_size, BRW_REGISTER_TYPE_F);
1586 nir_ssa_values[dest.ssa.index] =
1587 bld.vgrf(reg_type, dest.ssa.num_components);
1588 return nir_ssa_values[dest.ssa.index];
1589 } else {
1590 /* We don't handle indirects on locals */
1591 assert(dest.reg.indirect == NULL);
1592 return offset(nir_locals[dest.reg.reg->index], bld,
1593 dest.reg.base_offset * dest.reg.reg->num_components);
1594 }
1595 }
1596
1597 fs_reg
get_nir_image_deref(const nir_deref_var * deref)1598 fs_visitor::get_nir_image_deref(const nir_deref_var *deref)
1599 {
1600 fs_reg image(UNIFORM, deref->var->data.driver_location / 4,
1601 BRW_REGISTER_TYPE_UD);
1602 fs_reg indirect;
1603 unsigned indirect_max = 0;
1604
1605 for (const nir_deref *tail = &deref->deref; tail->child;
1606 tail = tail->child) {
1607 const nir_deref_array *deref_array = nir_deref_as_array(tail->child);
1608 assert(tail->child->deref_type == nir_deref_type_array);
1609 const unsigned size = glsl_get_length(tail->type);
1610 const unsigned element_size = type_size_scalar(deref_array->deref.type);
1611 const unsigned base = MIN2(deref_array->base_offset, size - 1);
1612 image = offset(image, bld, base * element_size);
1613
1614 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
1615 fs_reg tmp = vgrf(glsl_type::uint_type);
1616
1617 /* Accessing an invalid surface index with the dataport can result
1618 * in a hang. According to the spec "if the index used to
1619 * select an individual element is negative or greater than or
1620 * equal to the size of the array, the results of the operation
1621 * are undefined but may not lead to termination" -- which is one
1622 * of the possible outcomes of the hang. Clamp the index to
1623 * prevent access outside of the array bounds.
1624 */
1625 bld.emit_minmax(tmp, retype(get_nir_src(deref_array->indirect),
1626 BRW_REGISTER_TYPE_UD),
1627 brw_imm_ud(size - base - 1), BRW_CONDITIONAL_L);
1628
1629 indirect_max += element_size * (tail->type->length - 1);
1630
1631 bld.MUL(tmp, tmp, brw_imm_ud(element_size * 4));
1632 if (indirect.file == BAD_FILE) {
1633 indirect = tmp;
1634 } else {
1635 bld.ADD(indirect, indirect, tmp);
1636 }
1637 }
1638 }
1639
1640 if (indirect.file == BAD_FILE) {
1641 return image;
1642 } else {
1643 /* Emit a pile of MOVs to load the uniform into a temporary. The
1644 * dead-code elimination pass will get rid of what we don't use.
1645 */
1646 fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, BRW_IMAGE_PARAM_SIZE);
1647 for (unsigned j = 0; j < BRW_IMAGE_PARAM_SIZE; j++) {
1648 bld.emit(SHADER_OPCODE_MOV_INDIRECT,
1649 offset(tmp, bld, j), offset(image, bld, j),
1650 indirect, brw_imm_ud((indirect_max + 1) * 4));
1651 }
1652 return tmp;
1653 }
1654 }
1655
1656 void
emit_percomp(const fs_builder & bld,const fs_inst & inst,unsigned wr_mask)1657 fs_visitor::emit_percomp(const fs_builder &bld, const fs_inst &inst,
1658 unsigned wr_mask)
1659 {
1660 for (unsigned i = 0; i < 4; i++) {
1661 if (!((wr_mask >> i) & 1))
1662 continue;
1663
1664 fs_inst *new_inst = new(mem_ctx) fs_inst(inst);
1665 new_inst->dst = offset(new_inst->dst, bld, i);
1666 for (unsigned j = 0; j < new_inst->sources; j++)
1667 if (new_inst->src[j].file == VGRF)
1668 new_inst->src[j] = offset(new_inst->src[j], bld, i);
1669
1670 bld.emit(new_inst);
1671 }
1672 }
1673
1674 /**
1675 * Get the matching channel register datatype for an image intrinsic of the
1676 * specified GLSL image type.
1677 */
1678 static brw_reg_type
get_image_base_type(const glsl_type * type)1679 get_image_base_type(const glsl_type *type)
1680 {
1681 switch ((glsl_base_type)type->sampled_type) {
1682 case GLSL_TYPE_UINT:
1683 return BRW_REGISTER_TYPE_UD;
1684 case GLSL_TYPE_INT:
1685 return BRW_REGISTER_TYPE_D;
1686 case GLSL_TYPE_FLOAT:
1687 return BRW_REGISTER_TYPE_F;
1688 default:
1689 unreachable("Not reached.");
1690 }
1691 }
1692
1693 /**
1694 * Get the appropriate atomic op for an image atomic intrinsic.
1695 */
1696 static unsigned
get_image_atomic_op(nir_intrinsic_op op,const glsl_type * type)1697 get_image_atomic_op(nir_intrinsic_op op, const glsl_type *type)
1698 {
1699 switch (op) {
1700 case nir_intrinsic_image_atomic_add:
1701 return BRW_AOP_ADD;
1702 case nir_intrinsic_image_atomic_min:
1703 return (get_image_base_type(type) == BRW_REGISTER_TYPE_D ?
1704 BRW_AOP_IMIN : BRW_AOP_UMIN);
1705 case nir_intrinsic_image_atomic_max:
1706 return (get_image_base_type(type) == BRW_REGISTER_TYPE_D ?
1707 BRW_AOP_IMAX : BRW_AOP_UMAX);
1708 case nir_intrinsic_image_atomic_and:
1709 return BRW_AOP_AND;
1710 case nir_intrinsic_image_atomic_or:
1711 return BRW_AOP_OR;
1712 case nir_intrinsic_image_atomic_xor:
1713 return BRW_AOP_XOR;
1714 case nir_intrinsic_image_atomic_exchange:
1715 return BRW_AOP_MOV;
1716 case nir_intrinsic_image_atomic_comp_swap:
1717 return BRW_AOP_CMPWR;
1718 default:
1719 unreachable("Not reachable.");
1720 }
1721 }
1722
1723 static fs_inst *
emit_pixel_interpolater_send(const fs_builder & bld,enum opcode opcode,const fs_reg & dst,const fs_reg & src,const fs_reg & desc,glsl_interp_mode interpolation)1724 emit_pixel_interpolater_send(const fs_builder &bld,
1725 enum opcode opcode,
1726 const fs_reg &dst,
1727 const fs_reg &src,
1728 const fs_reg &desc,
1729 glsl_interp_mode interpolation)
1730 {
1731 struct brw_wm_prog_data *wm_prog_data =
1732 brw_wm_prog_data(bld.shader->stage_prog_data);
1733 fs_inst *inst;
1734 fs_reg payload;
1735 int mlen;
1736
1737 if (src.file == BAD_FILE) {
1738 /* Dummy payload */
1739 payload = bld.vgrf(BRW_REGISTER_TYPE_F, 1);
1740 mlen = 1;
1741 } else {
1742 payload = src;
1743 mlen = 2 * bld.dispatch_width() / 8;
1744 }
1745
1746 inst = bld.emit(opcode, dst, payload, desc);
1747 inst->mlen = mlen;
1748 /* 2 floats per slot returned */
1749 inst->size_written = 2 * dst.component_size(inst->exec_size);
1750 inst->pi_noperspective = interpolation == INTERP_MODE_NOPERSPECTIVE;
1751
1752 wm_prog_data->pulls_bary = true;
1753
1754 return inst;
1755 }
1756
1757 /**
1758 * Computes 1 << x, given a D/UD register containing some value x.
1759 */
1760 static fs_reg
intexp2(const fs_builder & bld,const fs_reg & x)1761 intexp2(const fs_builder &bld, const fs_reg &x)
1762 {
1763 assert(x.type == BRW_REGISTER_TYPE_UD || x.type == BRW_REGISTER_TYPE_D);
1764
1765 fs_reg result = bld.vgrf(x.type, 1);
1766 fs_reg one = bld.vgrf(x.type, 1);
1767
1768 bld.MOV(one, retype(brw_imm_d(1), one.type));
1769 bld.SHL(result, one, x);
1770 return result;
1771 }
1772
1773 void
emit_gs_end_primitive(const nir_src & vertex_count_nir_src)1774 fs_visitor::emit_gs_end_primitive(const nir_src &vertex_count_nir_src)
1775 {
1776 assert(stage == MESA_SHADER_GEOMETRY);
1777
1778 struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
1779
1780 if (gs_compile->control_data_header_size_bits == 0)
1781 return;
1782
1783 /* We can only do EndPrimitive() functionality when the control data
1784 * consists of cut bits. Fortunately, the only time it isn't is when the
1785 * output type is points, in which case EndPrimitive() is a no-op.
1786 */
1787 if (gs_prog_data->control_data_format !=
1788 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT) {
1789 return;
1790 }
1791
1792 /* Cut bits use one bit per vertex. */
1793 assert(gs_compile->control_data_bits_per_vertex == 1);
1794
1795 fs_reg vertex_count = get_nir_src(vertex_count_nir_src);
1796 vertex_count.type = BRW_REGISTER_TYPE_UD;
1797
1798 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1799 * vertex n, 0 otherwise. So all we need to do here is mark bit
1800 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1801 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1802 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1803 *
1804 * Note that if EndPrimitive() is called before emitting any vertices, this
1805 * will cause us to set bit 31 of the control_data_bits register to 1.
1806 * That's fine because:
1807 *
1808 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1809 * output, so the hardware will ignore cut bit 31.
1810 *
1811 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1812 * last vertex, so setting cut bit 31 has no effect (since the primitive
1813 * is automatically ended when the GS terminates).
1814 *
1815 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1816 * control_data_bits register to 0 when the first vertex is emitted.
1817 */
1818
1819 const fs_builder abld = bld.annotate("end primitive");
1820
1821 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1822 fs_reg prev_count = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1823 abld.ADD(prev_count, vertex_count, brw_imm_ud(0xffffffffu));
1824 fs_reg mask = intexp2(abld, prev_count);
1825 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1826 * attention to the lower 5 bits of its second source argument, so on this
1827 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1828 * ((vertex_count - 1) % 32).
1829 */
1830 abld.OR(this->control_data_bits, this->control_data_bits, mask);
1831 }
1832
1833 void
emit_gs_control_data_bits(const fs_reg & vertex_count)1834 fs_visitor::emit_gs_control_data_bits(const fs_reg &vertex_count)
1835 {
1836 assert(stage == MESA_SHADER_GEOMETRY);
1837 assert(gs_compile->control_data_bits_per_vertex != 0);
1838
1839 struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
1840
1841 const fs_builder abld = bld.annotate("emit control data bits");
1842 const fs_builder fwa_bld = bld.exec_all();
1843
1844 /* We use a single UD register to accumulate control data bits (32 bits
1845 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1846 * at a time.
1847 *
1848 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1849 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1850 * use the Channel Mask phase to enable/disable which DWord within that
1851 * group to write. (Remember, different SIMD8 channels may have emitted
1852 * different numbers of vertices, so we may need per-slot offsets.)
1853 *
1854 * Channel masking presents an annoying problem: we may have to replicate
1855 * the data up to 4 times:
1856 *
1857 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1858 *
1859 * To avoid penalizing shaders that emit a small number of vertices, we
1860 * can avoid these sometimes: if the size of the control data header is
1861 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1862 * land in the same 128-bit group, so we can skip per-slot offsets.
1863 *
1864 * Similarly, if the control data header is <= 32 bits, there is only one
1865 * DWord, so we can skip channel masks.
1866 */
1867 enum opcode opcode = SHADER_OPCODE_URB_WRITE_SIMD8;
1868
1869 fs_reg channel_mask, per_slot_offset;
1870
1871 if (gs_compile->control_data_header_size_bits > 32) {
1872 opcode = SHADER_OPCODE_URB_WRITE_SIMD8_MASKED;
1873 channel_mask = vgrf(glsl_type::uint_type);
1874 }
1875
1876 if (gs_compile->control_data_header_size_bits > 128) {
1877 opcode = SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT;
1878 per_slot_offset = vgrf(glsl_type::uint_type);
1879 }
1880
1881 /* Figure out which DWord we're trying to write to using the formula:
1882 *
1883 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1884 *
1885 * Since bits_per_vertex is a power of two, and is known at compile
1886 * time, this can be optimized to:
1887 *
1888 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1889 */
1890 if (opcode != SHADER_OPCODE_URB_WRITE_SIMD8) {
1891 fs_reg dword_index = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1892 fs_reg prev_count = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1893 abld.ADD(prev_count, vertex_count, brw_imm_ud(0xffffffffu));
1894 unsigned log2_bits_per_vertex =
1895 util_last_bit(gs_compile->control_data_bits_per_vertex);
1896 abld.SHR(dword_index, prev_count, brw_imm_ud(6u - log2_bits_per_vertex));
1897
1898 if (per_slot_offset.file != BAD_FILE) {
1899 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1900 * the appropriate OWord within the control data header.
1901 */
1902 abld.SHR(per_slot_offset, dword_index, brw_imm_ud(2u));
1903 }
1904
1905 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1906 * write to the appropriate DWORD within the OWORD.
1907 */
1908 fs_reg channel = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1909 fwa_bld.AND(channel, dword_index, brw_imm_ud(3u));
1910 channel_mask = intexp2(fwa_bld, channel);
1911 /* Then the channel masks need to be in bits 23:16. */
1912 fwa_bld.SHL(channel_mask, channel_mask, brw_imm_ud(16u));
1913 }
1914
1915 /* Store the control data bits in the message payload and send it. */
1916 int mlen = 2;
1917 if (channel_mask.file != BAD_FILE)
1918 mlen += 4; /* channel masks, plus 3 extra copies of the data */
1919 if (per_slot_offset.file != BAD_FILE)
1920 mlen++;
1921
1922 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, mlen);
1923 fs_reg *sources = ralloc_array(mem_ctx, fs_reg, mlen);
1924 int i = 0;
1925 sources[i++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
1926 if (per_slot_offset.file != BAD_FILE)
1927 sources[i++] = per_slot_offset;
1928 if (channel_mask.file != BAD_FILE)
1929 sources[i++] = channel_mask;
1930 while (i < mlen) {
1931 sources[i++] = this->control_data_bits;
1932 }
1933
1934 abld.LOAD_PAYLOAD(payload, sources, mlen, mlen);
1935 fs_inst *inst = abld.emit(opcode, reg_undef, payload);
1936 inst->mlen = mlen;
1937 /* We need to increment Global Offset by 256-bits to make room for
1938 * Broadwell's extra "Vertex Count" payload at the beginning of the
1939 * URB entry. Since this is an OWord message, Global Offset is counted
1940 * in 128-bit units, so we must set it to 2.
1941 */
1942 if (gs_prog_data->static_vertex_count == -1)
1943 inst->offset = 2;
1944 }
1945
1946 void
set_gs_stream_control_data_bits(const fs_reg & vertex_count,unsigned stream_id)1947 fs_visitor::set_gs_stream_control_data_bits(const fs_reg &vertex_count,
1948 unsigned stream_id)
1949 {
1950 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1951
1952 /* Note: we are calling this *before* increasing vertex_count, so
1953 * this->vertex_count == vertex_count - 1 in the formula above.
1954 */
1955
1956 /* Stream mode uses 2 bits per vertex */
1957 assert(gs_compile->control_data_bits_per_vertex == 2);
1958
1959 /* Must be a valid stream */
1960 assert(stream_id < MAX_VERTEX_STREAMS);
1961
1962 /* Control data bits are initialized to 0 so we don't have to set any
1963 * bits when sending vertices to stream 0.
1964 */
1965 if (stream_id == 0)
1966 return;
1967
1968 const fs_builder abld = bld.annotate("set stream control data bits", NULL);
1969
1970 /* reg::sid = stream_id */
1971 fs_reg sid = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1972 abld.MOV(sid, brw_imm_ud(stream_id));
1973
1974 /* reg:shift_count = 2 * (vertex_count - 1) */
1975 fs_reg shift_count = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1976 abld.SHL(shift_count, vertex_count, brw_imm_ud(1u));
1977
1978 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1979 * attention to the lower 5 bits of its second source argument, so on this
1980 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1981 * stream_id << ((2 * (vertex_count - 1)) % 32).
1982 */
1983 fs_reg mask = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1984 abld.SHL(mask, sid, shift_count);
1985 abld.OR(this->control_data_bits, this->control_data_bits, mask);
1986 }
1987
1988 void
emit_gs_vertex(const nir_src & vertex_count_nir_src,unsigned stream_id)1989 fs_visitor::emit_gs_vertex(const nir_src &vertex_count_nir_src,
1990 unsigned stream_id)
1991 {
1992 assert(stage == MESA_SHADER_GEOMETRY);
1993
1994 struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
1995
1996 fs_reg vertex_count = get_nir_src(vertex_count_nir_src);
1997 vertex_count.type = BRW_REGISTER_TYPE_UD;
1998
1999 /* Haswell and later hardware ignores the "Render Stream Select" bits
2000 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2001 * and instead sends all primitives down the pipeline for rasterization.
2002 * If the SOL stage is enabled, "Render Stream Select" is honored and
2003 * primitives bound to non-zero streams are discarded after stream output.
2004 *
2005 * Since the only purpose of primives sent to non-zero streams is to
2006 * be recorded by transform feedback, we can simply discard all geometry
2007 * bound to these streams when transform feedback is disabled.
2008 */
2009 if (stream_id > 0 && !nir->info.has_transform_feedback_varyings)
2010 return;
2011
2012 /* If we're outputting 32 control data bits or less, then we can wait
2013 * until the shader is over to output them all. Otherwise we need to
2014 * output them as we go. Now is the time to do it, since we're about to
2015 * output the vertex_count'th vertex, so it's guaranteed that the
2016 * control data bits associated with the (vertex_count - 1)th vertex are
2017 * correct.
2018 */
2019 if (gs_compile->control_data_header_size_bits > 32) {
2020 const fs_builder abld =
2021 bld.annotate("emit vertex: emit control data bits");
2022
2023 /* Only emit control data bits if we've finished accumulating a batch
2024 * of 32 bits. This is the case when:
2025 *
2026 * (vertex_count * bits_per_vertex) % 32 == 0
2027 *
2028 * (in other words, when the last 5 bits of vertex_count *
2029 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2030 * integer n (which is always the case, since bits_per_vertex is
2031 * always 1 or 2), this is equivalent to requiring that the last 5-n
2032 * bits of vertex_count are 0:
2033 *
2034 * vertex_count & (2^(5-n) - 1) == 0
2035 *
2036 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2037 * equivalent to:
2038 *
2039 * vertex_count & (32 / bits_per_vertex - 1) == 0
2040 *
2041 * TODO: If vertex_count is an immediate, we could do some of this math
2042 * at compile time...
2043 */
2044 fs_inst *inst =
2045 abld.AND(bld.null_reg_d(), vertex_count,
2046 brw_imm_ud(32u / gs_compile->control_data_bits_per_vertex - 1u));
2047 inst->conditional_mod = BRW_CONDITIONAL_Z;
2048
2049 abld.IF(BRW_PREDICATE_NORMAL);
2050 /* If vertex_count is 0, then no control data bits have been
2051 * accumulated yet, so we can skip emitting them.
2052 */
2053 abld.CMP(bld.null_reg_d(), vertex_count, brw_imm_ud(0u),
2054 BRW_CONDITIONAL_NEQ);
2055 abld.IF(BRW_PREDICATE_NORMAL);
2056 emit_gs_control_data_bits(vertex_count);
2057 abld.emit(BRW_OPCODE_ENDIF);
2058
2059 /* Reset control_data_bits to 0 so we can start accumulating a new
2060 * batch.
2061 *
2062 * Note: in the case where vertex_count == 0, this neutralizes the
2063 * effect of any call to EndPrimitive() that the shader may have
2064 * made before outputting its first vertex.
2065 */
2066 inst = abld.MOV(this->control_data_bits, brw_imm_ud(0u));
2067 inst->force_writemask_all = true;
2068 abld.emit(BRW_OPCODE_ENDIF);
2069 }
2070
2071 emit_urb_writes(vertex_count);
2072
2073 /* In stream mode we have to set control data bits for all vertices
2074 * unless we have disabled control data bits completely (which we do
2075 * do for GL_POINTS outputs that don't use streams).
2076 */
2077 if (gs_compile->control_data_header_size_bits > 0 &&
2078 gs_prog_data->control_data_format ==
2079 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) {
2080 set_gs_stream_control_data_bits(vertex_count, stream_id);
2081 }
2082 }
2083
2084 void
emit_gs_input_load(const fs_reg & dst,const nir_src & vertex_src,unsigned base_offset,const nir_src & offset_src,unsigned num_components,unsigned first_component)2085 fs_visitor::emit_gs_input_load(const fs_reg &dst,
2086 const nir_src &vertex_src,
2087 unsigned base_offset,
2088 const nir_src &offset_src,
2089 unsigned num_components,
2090 unsigned first_component)
2091 {
2092 struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
2093
2094 nir_const_value *vertex_const = nir_src_as_const_value(vertex_src);
2095 nir_const_value *offset_const = nir_src_as_const_value(offset_src);
2096 const unsigned push_reg_count = gs_prog_data->base.urb_read_length * 8;
2097
2098 /* TODO: figure out push input layout for invocations == 1 */
2099 /* TODO: make this work with 64-bit inputs */
2100 if (gs_prog_data->invocations == 1 &&
2101 type_sz(dst.type) <= 4 &&
2102 offset_const != NULL && vertex_const != NULL &&
2103 4 * (base_offset + offset_const->u32[0]) < push_reg_count) {
2104 int imm_offset = (base_offset + offset_const->u32[0]) * 4 +
2105 vertex_const->u32[0] * push_reg_count;
2106 for (unsigned i = 0; i < num_components; i++) {
2107 bld.MOV(offset(dst, bld, i),
2108 fs_reg(ATTR, imm_offset + i + first_component, dst.type));
2109 }
2110 return;
2111 }
2112
2113 /* Resort to the pull model. Ensure the VUE handles are provided. */
2114 assert(gs_prog_data->base.include_vue_handles);
2115
2116 unsigned first_icp_handle = gs_prog_data->include_primitive_id ? 3 : 2;
2117 fs_reg icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2118
2119 if (gs_prog_data->invocations == 1) {
2120 if (vertex_const) {
2121 /* The vertex index is constant; just select the proper URB handle. */
2122 icp_handle =
2123 retype(brw_vec8_grf(first_icp_handle + vertex_const->i32[0], 0),
2124 BRW_REGISTER_TYPE_UD);
2125 } else {
2126 /* The vertex index is non-constant. We need to use indirect
2127 * addressing to fetch the proper URB handle.
2128 *
2129 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2130 * indicating that channel <n> should read the handle from
2131 * DWord <n>. We convert that to bytes by multiplying by 4.
2132 *
2133 * Next, we convert the vertex index to bytes by multiplying
2134 * by 32 (shifting by 5), and add the two together. This is
2135 * the final indirect byte offset.
2136 */
2137 fs_reg sequence = bld.vgrf(BRW_REGISTER_TYPE_UW, 1);
2138 fs_reg channel_offsets = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2139 fs_reg vertex_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2140 fs_reg icp_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2141
2142 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2143 bld.MOV(sequence, fs_reg(brw_imm_v(0x76543210)));
2144 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2145 bld.SHL(channel_offsets, sequence, brw_imm_ud(2u));
2146 /* Convert vertex_index to bytes (multiply by 32) */
2147 bld.SHL(vertex_offset_bytes,
2148 retype(get_nir_src(vertex_src), BRW_REGISTER_TYPE_UD),
2149 brw_imm_ud(5u));
2150 bld.ADD(icp_offset_bytes, vertex_offset_bytes, channel_offsets);
2151
2152 /* Use first_icp_handle as the base offset. There is one register
2153 * of URB handles per vertex, so inform the register allocator that
2154 * we might read up to nir->info.gs.vertices_in registers.
2155 */
2156 bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle,
2157 retype(brw_vec8_grf(first_icp_handle, 0), icp_handle.type),
2158 fs_reg(icp_offset_bytes),
2159 brw_imm_ud(nir->info.gs.vertices_in * REG_SIZE));
2160 }
2161 } else {
2162 assert(gs_prog_data->invocations > 1);
2163
2164 if (vertex_const) {
2165 assert(devinfo->gen >= 9 || vertex_const->i32[0] <= 5);
2166 bld.MOV(icp_handle,
2167 retype(brw_vec1_grf(first_icp_handle +
2168 vertex_const->i32[0] / 8,
2169 vertex_const->i32[0] % 8),
2170 BRW_REGISTER_TYPE_UD));
2171 } else {
2172 /* The vertex index is non-constant. We need to use indirect
2173 * addressing to fetch the proper URB handle.
2174 *
2175 */
2176 fs_reg icp_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2177
2178 /* Convert vertex_index to bytes (multiply by 4) */
2179 bld.SHL(icp_offset_bytes,
2180 retype(get_nir_src(vertex_src), BRW_REGISTER_TYPE_UD),
2181 brw_imm_ud(2u));
2182
2183 /* Use first_icp_handle as the base offset. There is one DWord
2184 * of URB handles per vertex, so inform the register allocator that
2185 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2186 */
2187 bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle,
2188 retype(brw_vec8_grf(first_icp_handle, 0), icp_handle.type),
2189 fs_reg(icp_offset_bytes),
2190 brw_imm_ud(DIV_ROUND_UP(nir->info.gs.vertices_in, 8) *
2191 REG_SIZE));
2192 }
2193 }
2194
2195 fs_inst *inst;
2196
2197 fs_reg tmp_dst = dst;
2198 fs_reg indirect_offset = get_nir_src(offset_src);
2199 unsigned num_iterations = 1;
2200 unsigned orig_num_components = num_components;
2201
2202 if (type_sz(dst.type) == 8) {
2203 if (num_components > 2) {
2204 num_iterations = 2;
2205 num_components = 2;
2206 }
2207 fs_reg tmp = fs_reg(VGRF, alloc.allocate(4), dst.type);
2208 tmp_dst = tmp;
2209 first_component = first_component / 2;
2210 }
2211
2212 for (unsigned iter = 0; iter < num_iterations; iter++) {
2213 if (offset_const) {
2214 /* Constant indexing - use global offset. */
2215 if (first_component != 0) {
2216 unsigned read_components = num_components + first_component;
2217 fs_reg tmp = bld.vgrf(dst.type, read_components);
2218 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp, icp_handle);
2219 inst->size_written = read_components *
2220 tmp.component_size(inst->exec_size);
2221 for (unsigned i = 0; i < num_components; i++) {
2222 bld.MOV(offset(tmp_dst, bld, i),
2223 offset(tmp, bld, i + first_component));
2224 }
2225 } else {
2226 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp_dst,
2227 icp_handle);
2228 inst->size_written = num_components *
2229 tmp_dst.component_size(inst->exec_size);
2230 }
2231 inst->offset = base_offset + offset_const->u32[0];
2232 inst->mlen = 1;
2233 } else {
2234 /* Indirect indexing - use per-slot offsets as well. */
2235 const fs_reg srcs[] = { icp_handle, indirect_offset };
2236 unsigned read_components = num_components + first_component;
2237 fs_reg tmp = bld.vgrf(dst.type, read_components);
2238 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
2239 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2240 if (first_component != 0) {
2241 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
2242 payload);
2243 inst->size_written = read_components *
2244 tmp.component_size(inst->exec_size);
2245 for (unsigned i = 0; i < num_components; i++) {
2246 bld.MOV(offset(tmp_dst, bld, i),
2247 offset(tmp, bld, i + first_component));
2248 }
2249 } else {
2250 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp_dst,
2251 payload);
2252 inst->size_written = num_components *
2253 tmp_dst.component_size(inst->exec_size);
2254 }
2255 inst->offset = base_offset;
2256 inst->mlen = 2;
2257 }
2258
2259 if (type_sz(dst.type) == 8) {
2260 shuffle_32bit_load_result_to_64bit_data(
2261 bld, tmp_dst, retype(tmp_dst, BRW_REGISTER_TYPE_F), num_components);
2262
2263 for (unsigned c = 0; c < num_components; c++)
2264 bld.MOV(offset(dst, bld, iter * 2 + c), offset(tmp_dst, bld, c));
2265 }
2266
2267 if (num_iterations > 1) {
2268 num_components = orig_num_components - 2;
2269 if(offset_const) {
2270 base_offset++;
2271 } else {
2272 fs_reg new_indirect = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2273 bld.ADD(new_indirect, indirect_offset, brw_imm_ud(1u));
2274 indirect_offset = new_indirect;
2275 }
2276 }
2277 }
2278 }
2279
2280 fs_reg
get_indirect_offset(nir_intrinsic_instr * instr)2281 fs_visitor::get_indirect_offset(nir_intrinsic_instr *instr)
2282 {
2283 nir_src *offset_src = nir_get_io_offset_src(instr);
2284 nir_const_value *const_value = nir_src_as_const_value(*offset_src);
2285
2286 if (const_value) {
2287 /* The only constant offset we should find is 0. brw_nir.c's
2288 * add_const_offset_to_base() will fold other constant offsets
2289 * into instr->const_index[0].
2290 */
2291 assert(const_value->u32[0] == 0);
2292 return fs_reg();
2293 }
2294
2295 return get_nir_src(*offset_src);
2296 }
2297
2298 static void
do_untyped_vector_read(const fs_builder & bld,const fs_reg dest,const fs_reg surf_index,const fs_reg offset_reg,unsigned num_components)2299 do_untyped_vector_read(const fs_builder &bld,
2300 const fs_reg dest,
2301 const fs_reg surf_index,
2302 const fs_reg offset_reg,
2303 unsigned num_components)
2304 {
2305 if (type_sz(dest.type) <= 2) {
2306 assert(dest.stride == 1);
2307
2308 if (num_components > 1) {
2309 /* Pairs of 16-bit components can be read with untyped read, for 16-bit
2310 * vec3 4th component is ignored.
2311 */
2312 fs_reg read_result =
2313 emit_untyped_read(bld, surf_index, offset_reg,
2314 1 /* dims */, DIV_ROUND_UP(num_components, 2),
2315 BRW_PREDICATE_NONE);
2316 shuffle_32bit_load_result_to_16bit_data(bld,
2317 retype(dest, BRW_REGISTER_TYPE_W),
2318 retype(read_result, BRW_REGISTER_TYPE_D),
2319 num_components);
2320 } else {
2321 assert(num_components == 1);
2322 /* scalar 16-bit are read using one byte_scattered_read message */
2323 fs_reg read_result =
2324 emit_byte_scattered_read(bld, surf_index, offset_reg,
2325 1 /* dims */, 1,
2326 type_sz(dest.type) * 8 /* bit_size */,
2327 BRW_PREDICATE_NONE);
2328 bld.MOV(dest, subscript(read_result, dest.type, 0));
2329 }
2330 } else if (type_sz(dest.type) == 4) {
2331 fs_reg read_result = emit_untyped_read(bld, surf_index, offset_reg,
2332 1 /* dims */,
2333 num_components,
2334 BRW_PREDICATE_NONE);
2335 read_result.type = dest.type;
2336 for (unsigned i = 0; i < num_components; i++)
2337 bld.MOV(offset(dest, bld, i), offset(read_result, bld, i));
2338 } else if (type_sz(dest.type) == 8) {
2339 /* Reading a dvec, so we need to:
2340 *
2341 * 1. Multiply num_components by 2, to account for the fact that we
2342 * need to read 64-bit components.
2343 * 2. Shuffle the result of the load to form valid 64-bit elements
2344 * 3. Emit a second load (for components z/w) if needed.
2345 */
2346 fs_reg read_offset = bld.vgrf(BRW_REGISTER_TYPE_UD);
2347 bld.MOV(read_offset, offset_reg);
2348
2349 int iters = num_components <= 2 ? 1 : 2;
2350
2351 /* Load the dvec, the first iteration loads components x/y, the second
2352 * iteration, if needed, loads components z/w
2353 */
2354 for (int it = 0; it < iters; it++) {
2355 /* Compute number of components to read in this iteration */
2356 int iter_components = MIN2(2, num_components);
2357 num_components -= iter_components;
2358
2359 /* Read. Since this message reads 32-bit components, we need to
2360 * read twice as many components.
2361 */
2362 fs_reg read_result = emit_untyped_read(bld, surf_index, read_offset,
2363 1 /* dims */,
2364 iter_components * 2,
2365 BRW_PREDICATE_NONE);
2366
2367 /* Shuffle the 32-bit load result into valid 64-bit data */
2368 const fs_reg packed_result = bld.vgrf(dest.type, iter_components);
2369 shuffle_32bit_load_result_to_64bit_data(
2370 bld, packed_result, read_result, iter_components);
2371
2372 /* Move each component to its destination */
2373 read_result = retype(read_result, BRW_REGISTER_TYPE_DF);
2374 for (int c = 0; c < iter_components; c++) {
2375 bld.MOV(offset(dest, bld, it * 2 + c),
2376 offset(packed_result, bld, c));
2377 }
2378
2379 bld.ADD(read_offset, read_offset, brw_imm_ud(16));
2380 }
2381 } else {
2382 unreachable("Unsupported type");
2383 }
2384 }
2385
2386 void
nir_emit_vs_intrinsic(const fs_builder & bld,nir_intrinsic_instr * instr)2387 fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld,
2388 nir_intrinsic_instr *instr)
2389 {
2390 assert(stage == MESA_SHADER_VERTEX);
2391
2392 fs_reg dest;
2393 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
2394 dest = get_nir_dest(instr->dest);
2395
2396 switch (instr->intrinsic) {
2397 case nir_intrinsic_load_vertex_id:
2398 unreachable("should be lowered by lower_vertex_id()");
2399
2400 case nir_intrinsic_load_vertex_id_zero_base:
2401 case nir_intrinsic_load_base_vertex:
2402 case nir_intrinsic_load_instance_id:
2403 case nir_intrinsic_load_base_instance:
2404 case nir_intrinsic_load_draw_id: {
2405 gl_system_value sv = nir_system_value_from_intrinsic(instr->intrinsic);
2406 fs_reg val = nir_system_values[sv];
2407 assert(val.file != BAD_FILE);
2408 dest.type = val.type;
2409 bld.MOV(dest, val);
2410 break;
2411 }
2412
2413 case nir_intrinsic_load_input: {
2414 fs_reg src = fs_reg(ATTR, nir_intrinsic_base(instr) * 4, dest.type);
2415 unsigned first_component = nir_intrinsic_component(instr);
2416 unsigned num_components = instr->num_components;
2417 enum brw_reg_type type = dest.type;
2418
2419 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
2420 assert(const_offset && "Indirect input loads not allowed");
2421 src = offset(src, bld, const_offset->u32[0]);
2422
2423 for (unsigned j = 0; j < num_components; j++) {
2424 bld.MOV(offset(dest, bld, j), offset(src, bld, j + first_component));
2425 }
2426
2427 if (type == BRW_REGISTER_TYPE_DF) {
2428 /* Once the double vector is read, set again its original register
2429 * type to continue with normal execution.
2430 */
2431 src = retype(src, type);
2432 dest = retype(dest, type);
2433 }
2434
2435 if (type_sz(src.type) == 8) {
2436 shuffle_32bit_load_result_to_64bit_data(bld,
2437 dest,
2438 retype(dest, BRW_REGISTER_TYPE_F),
2439 instr->num_components);
2440 }
2441 break;
2442 }
2443
2444 default:
2445 nir_emit_intrinsic(bld, instr);
2446 break;
2447 }
2448 }
2449
2450 void
nir_emit_tcs_intrinsic(const fs_builder & bld,nir_intrinsic_instr * instr)2451 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
2452 nir_intrinsic_instr *instr)
2453 {
2454 assert(stage == MESA_SHADER_TESS_CTRL);
2455 struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key;
2456 struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
2457
2458 fs_reg dst;
2459 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
2460 dst = get_nir_dest(instr->dest);
2461
2462 switch (instr->intrinsic) {
2463 case nir_intrinsic_load_primitive_id:
2464 bld.MOV(dst, fs_reg(brw_vec1_grf(0, 1)));
2465 break;
2466 case nir_intrinsic_load_invocation_id:
2467 bld.MOV(retype(dst, invocation_id.type), invocation_id);
2468 break;
2469 case nir_intrinsic_load_patch_vertices_in:
2470 bld.MOV(retype(dst, BRW_REGISTER_TYPE_D),
2471 brw_imm_d(tcs_key->input_vertices));
2472 break;
2473
2474 case nir_intrinsic_barrier: {
2475 if (tcs_prog_data->instances == 1)
2476 break;
2477
2478 fs_reg m0 = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2479 fs_reg m0_2 = component(m0, 2);
2480
2481 const fs_builder chanbld = bld.exec_all().group(1, 0);
2482
2483 /* Zero the message header */
2484 bld.exec_all().MOV(m0, brw_imm_ud(0u));
2485
2486 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2487 chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
2488 brw_imm_ud(INTEL_MASK(16, 13)));
2489
2490 /* Shift it up to bits 27:24. */
2491 chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
2492
2493 /* Set the Barrier Count and the enable bit */
2494 chanbld.OR(m0_2, m0_2,
2495 brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
2496
2497 bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0);
2498 break;
2499 }
2500
2501 case nir_intrinsic_load_input:
2502 unreachable("nir_lower_io should never give us these.");
2503 break;
2504
2505 case nir_intrinsic_load_per_vertex_input: {
2506 fs_reg indirect_offset = get_indirect_offset(instr);
2507 unsigned imm_offset = instr->const_index[0];
2508
2509 const nir_src &vertex_src = instr->src[0];
2510 nir_const_value *vertex_const = nir_src_as_const_value(vertex_src);
2511
2512 fs_inst *inst;
2513
2514 fs_reg icp_handle;
2515
2516 if (vertex_const) {
2517 /* Emit a MOV to resolve <0,1,0> regioning. */
2518 icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2519 bld.MOV(icp_handle,
2520 retype(brw_vec1_grf(1 + (vertex_const->i32[0] >> 3),
2521 vertex_const->i32[0] & 7),
2522 BRW_REGISTER_TYPE_UD));
2523 } else if (tcs_prog_data->instances == 1 &&
2524 vertex_src.is_ssa &&
2525 vertex_src.ssa->parent_instr->type == nir_instr_type_intrinsic &&
2526 nir_instr_as_intrinsic(vertex_src.ssa->parent_instr)->intrinsic == nir_intrinsic_load_invocation_id) {
2527 /* For the common case of only 1 instance, an array index of
2528 * gl_InvocationID means reading g1. Skip all the indirect work.
2529 */
2530 icp_handle = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
2531 } else {
2532 /* The vertex index is non-constant. We need to use indirect
2533 * addressing to fetch the proper URB handle.
2534 */
2535 icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2536
2537 /* Each ICP handle is a single DWord (4 bytes) */
2538 fs_reg vertex_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2539 bld.SHL(vertex_offset_bytes,
2540 retype(get_nir_src(vertex_src), BRW_REGISTER_TYPE_UD),
2541 brw_imm_ud(2u));
2542
2543 /* Start at g1. We might read up to 4 registers. */
2544 bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle,
2545 retype(brw_vec8_grf(1, 0), icp_handle.type), vertex_offset_bytes,
2546 brw_imm_ud(4 * REG_SIZE));
2547 }
2548
2549 /* We can only read two double components with each URB read, so
2550 * we send two read messages in that case, each one loading up to
2551 * two double components.
2552 */
2553 unsigned num_iterations = 1;
2554 unsigned num_components = instr->num_components;
2555 unsigned first_component = nir_intrinsic_component(instr);
2556 fs_reg orig_dst = dst;
2557 if (type_sz(dst.type) == 8) {
2558 first_component = first_component / 2;
2559 if (instr->num_components > 2) {
2560 num_iterations = 2;
2561 num_components = 2;
2562 }
2563
2564 fs_reg tmp = fs_reg(VGRF, alloc.allocate(4), dst.type);
2565 dst = tmp;
2566 }
2567
2568 for (unsigned iter = 0; iter < num_iterations; iter++) {
2569 if (indirect_offset.file == BAD_FILE) {
2570 /* Constant indexing - use global offset. */
2571 if (first_component != 0) {
2572 unsigned read_components = num_components + first_component;
2573 fs_reg tmp = bld.vgrf(dst.type, read_components);
2574 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp, icp_handle);
2575 for (unsigned i = 0; i < num_components; i++) {
2576 bld.MOV(offset(dst, bld, i),
2577 offset(tmp, bld, i + first_component));
2578 }
2579 } else {
2580 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, icp_handle);
2581 }
2582 inst->offset = imm_offset;
2583 inst->mlen = 1;
2584 } else {
2585 /* Indirect indexing - use per-slot offsets as well. */
2586 const fs_reg srcs[] = { icp_handle, indirect_offset };
2587 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
2588 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2589 if (first_component != 0) {
2590 unsigned read_components = num_components + first_component;
2591 fs_reg tmp = bld.vgrf(dst.type, read_components);
2592 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
2593 payload);
2594 for (unsigned i = 0; i < num_components; i++) {
2595 bld.MOV(offset(dst, bld, i),
2596 offset(tmp, bld, i + first_component));
2597 }
2598 } else {
2599 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst,
2600 payload);
2601 }
2602 inst->offset = imm_offset;
2603 inst->mlen = 2;
2604 }
2605 inst->size_written = (num_components + first_component) *
2606 inst->dst.component_size(inst->exec_size);
2607
2608 /* If we are reading 64-bit data using 32-bit read messages we need
2609 * build proper 64-bit data elements by shuffling the low and high
2610 * 32-bit components around like we do for other things like UBOs
2611 * or SSBOs.
2612 */
2613 if (type_sz(dst.type) == 8) {
2614 shuffle_32bit_load_result_to_64bit_data(
2615 bld, dst, retype(dst, BRW_REGISTER_TYPE_F), num_components);
2616
2617 for (unsigned c = 0; c < num_components; c++) {
2618 bld.MOV(offset(orig_dst, bld, iter * 2 + c),
2619 offset(dst, bld, c));
2620 }
2621 }
2622
2623 /* Copy the temporary to the destination to deal with writemasking.
2624 *
2625 * Also attempt to deal with gl_PointSize being in the .w component.
2626 */
2627 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
2628 assert(type_sz(dst.type) < 8);
2629 inst->dst = bld.vgrf(dst.type, 4);
2630 inst->size_written = 4 * REG_SIZE;
2631 bld.MOV(dst, offset(inst->dst, bld, 3));
2632 }
2633
2634 /* If we are loading double data and we need a second read message
2635 * adjust the write offset
2636 */
2637 if (num_iterations > 1) {
2638 num_components = instr->num_components - 2;
2639 imm_offset++;
2640 }
2641 }
2642 break;
2643 }
2644
2645 case nir_intrinsic_load_output:
2646 case nir_intrinsic_load_per_vertex_output: {
2647 fs_reg indirect_offset = get_indirect_offset(instr);
2648 unsigned imm_offset = instr->const_index[0];
2649 unsigned first_component = nir_intrinsic_component(instr);
2650
2651 fs_inst *inst;
2652 if (indirect_offset.file == BAD_FILE) {
2653 /* Replicate the patch handle to all enabled channels */
2654 fs_reg patch_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2655 bld.MOV(patch_handle,
2656 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
2657
2658 {
2659 if (first_component != 0) {
2660 unsigned read_components =
2661 instr->num_components + first_component;
2662 fs_reg tmp = bld.vgrf(dst.type, read_components);
2663 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp,
2664 patch_handle);
2665 inst->size_written = read_components * REG_SIZE;
2666 for (unsigned i = 0; i < instr->num_components; i++) {
2667 bld.MOV(offset(dst, bld, i),
2668 offset(tmp, bld, i + first_component));
2669 }
2670 } else {
2671 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst,
2672 patch_handle);
2673 inst->size_written = instr->num_components * REG_SIZE;
2674 }
2675 inst->offset = imm_offset;
2676 inst->mlen = 1;
2677 }
2678 } else {
2679 /* Indirect indexing - use per-slot offsets as well. */
2680 const fs_reg srcs[] = {
2681 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD),
2682 indirect_offset
2683 };
2684 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
2685 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2686 if (first_component != 0) {
2687 unsigned read_components =
2688 instr->num_components + first_component;
2689 fs_reg tmp = bld.vgrf(dst.type, read_components);
2690 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
2691 payload);
2692 inst->size_written = read_components * REG_SIZE;
2693 for (unsigned i = 0; i < instr->num_components; i++) {
2694 bld.MOV(offset(dst, bld, i),
2695 offset(tmp, bld, i + first_component));
2696 }
2697 } else {
2698 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst,
2699 payload);
2700 inst->size_written = instr->num_components * REG_SIZE;
2701 }
2702 inst->offset = imm_offset;
2703 inst->mlen = 2;
2704 }
2705 break;
2706 }
2707
2708 case nir_intrinsic_store_output:
2709 case nir_intrinsic_store_per_vertex_output: {
2710 fs_reg value = get_nir_src(instr->src[0]);
2711 bool is_64bit = (instr->src[0].is_ssa ?
2712 instr->src[0].ssa->bit_size : instr->src[0].reg.reg->bit_size) == 64;
2713 fs_reg indirect_offset = get_indirect_offset(instr);
2714 unsigned imm_offset = instr->const_index[0];
2715 unsigned mask = instr->const_index[1];
2716 unsigned header_regs = 0;
2717 fs_reg srcs[7];
2718 srcs[header_regs++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD);
2719
2720 if (indirect_offset.file != BAD_FILE) {
2721 srcs[header_regs++] = indirect_offset;
2722 }
2723
2724 if (mask == 0)
2725 break;
2726
2727 unsigned num_components = util_last_bit(mask);
2728 enum opcode opcode;
2729
2730 /* We can only pack two 64-bit components in a single message, so send
2731 * 2 messages if we have more components
2732 */
2733 unsigned num_iterations = 1;
2734 unsigned iter_components = num_components;
2735 unsigned first_component = nir_intrinsic_component(instr);
2736 if (is_64bit) {
2737 first_component = first_component / 2;
2738 if (instr->num_components > 2) {
2739 num_iterations = 2;
2740 iter_components = 2;
2741 }
2742 }
2743
2744 mask = mask << first_component;
2745
2746 for (unsigned iter = 0; iter < num_iterations; iter++) {
2747 if (!is_64bit && mask != WRITEMASK_XYZW) {
2748 srcs[header_regs++] = brw_imm_ud(mask << 16);
2749 opcode = indirect_offset.file != BAD_FILE ?
2750 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT :
2751 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED;
2752 } else if (is_64bit && ((mask & WRITEMASK_XY) != WRITEMASK_XY)) {
2753 /* Expand the 64-bit mask to 32-bit channels. We only handle
2754 * two channels in each iteration, so we only care about X/Y.
2755 */
2756 unsigned mask32 = 0;
2757 if (mask & WRITEMASK_X)
2758 mask32 |= WRITEMASK_XY;
2759 if (mask & WRITEMASK_Y)
2760 mask32 |= WRITEMASK_ZW;
2761
2762 /* If the mask does not include any of the channels X or Y there
2763 * is nothing to do in this iteration. Move on to the next couple
2764 * of 64-bit channels.
2765 */
2766 if (!mask32) {
2767 mask >>= 2;
2768 imm_offset++;
2769 continue;
2770 }
2771
2772 srcs[header_regs++] = brw_imm_ud(mask32 << 16);
2773 opcode = indirect_offset.file != BAD_FILE ?
2774 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT :
2775 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED;
2776 } else {
2777 opcode = indirect_offset.file != BAD_FILE ?
2778 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT :
2779 SHADER_OPCODE_URB_WRITE_SIMD8;
2780 }
2781
2782 for (unsigned i = 0; i < iter_components; i++) {
2783 if (!(mask & (1 << (i + first_component))))
2784 continue;
2785
2786 if (!is_64bit) {
2787 srcs[header_regs + i + first_component] = offset(value, bld, i);
2788 } else {
2789 /* We need to shuffle the 64-bit data to match the layout
2790 * expected by our 32-bit URB write messages. We use a temporary
2791 * for that.
2792 */
2793 unsigned channel = iter * 2 + i;
2794 fs_reg dest = shuffle_64bit_data_for_32bit_write(bld,
2795 offset(value, bld, channel), 1);
2796
2797 srcs[header_regs + (i + first_component) * 2] = dest;
2798 srcs[header_regs + (i + first_component) * 2 + 1] =
2799 offset(dest, bld, 1);
2800 }
2801 }
2802
2803 unsigned mlen =
2804 header_regs + (is_64bit ? 2 * iter_components : iter_components) +
2805 (is_64bit ? 2 * first_component : first_component);
2806 fs_reg payload =
2807 bld.vgrf(BRW_REGISTER_TYPE_UD, mlen);
2808 bld.LOAD_PAYLOAD(payload, srcs, mlen, header_regs);
2809
2810 fs_inst *inst = bld.emit(opcode, bld.null_reg_ud(), payload);
2811 inst->offset = imm_offset;
2812 inst->mlen = mlen;
2813
2814 /* If this is a 64-bit attribute, select the next two 64-bit channels
2815 * to be handled in the next iteration.
2816 */
2817 if (is_64bit) {
2818 mask >>= 2;
2819 imm_offset++;
2820 }
2821 }
2822 break;
2823 }
2824
2825 default:
2826 nir_emit_intrinsic(bld, instr);
2827 break;
2828 }
2829 }
2830
2831 void
nir_emit_tes_intrinsic(const fs_builder & bld,nir_intrinsic_instr * instr)2832 fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld,
2833 nir_intrinsic_instr *instr)
2834 {
2835 assert(stage == MESA_SHADER_TESS_EVAL);
2836 struct brw_tes_prog_data *tes_prog_data = brw_tes_prog_data(prog_data);
2837
2838 fs_reg dest;
2839 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
2840 dest = get_nir_dest(instr->dest);
2841
2842 switch (instr->intrinsic) {
2843 case nir_intrinsic_load_primitive_id:
2844 bld.MOV(dest, fs_reg(brw_vec1_grf(0, 1)));
2845 break;
2846 case nir_intrinsic_load_tess_coord:
2847 /* gl_TessCoord is part of the payload in g1-3 */
2848 for (unsigned i = 0; i < 3; i++) {
2849 bld.MOV(offset(dest, bld, i), fs_reg(brw_vec8_grf(1 + i, 0)));
2850 }
2851 break;
2852
2853 case nir_intrinsic_load_input:
2854 case nir_intrinsic_load_per_vertex_input: {
2855 fs_reg indirect_offset = get_indirect_offset(instr);
2856 unsigned imm_offset = instr->const_index[0];
2857 unsigned first_component = nir_intrinsic_component(instr);
2858
2859 if (type_sz(dest.type) == 8) {
2860 first_component = first_component / 2;
2861 }
2862
2863 fs_inst *inst;
2864 if (indirect_offset.file == BAD_FILE) {
2865 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2866 * which is 16 registers (since each holds 2 vec4 slots).
2867 */
2868 unsigned slot_count = 1;
2869 if (type_sz(dest.type) == 8 && instr->num_components > 2)
2870 slot_count++;
2871
2872 const unsigned max_push_slots = 32;
2873 if (imm_offset + slot_count <= max_push_slots) {
2874 fs_reg src = fs_reg(ATTR, imm_offset / 2, dest.type);
2875 for (int i = 0; i < instr->num_components; i++) {
2876 unsigned comp = 16 / type_sz(dest.type) * (imm_offset % 2) +
2877 i + first_component;
2878 bld.MOV(offset(dest, bld, i), component(src, comp));
2879 }
2880
2881 tes_prog_data->base.urb_read_length =
2882 MAX2(tes_prog_data->base.urb_read_length,
2883 DIV_ROUND_UP(imm_offset + slot_count, 2));
2884 } else {
2885 /* Replicate the patch handle to all enabled channels */
2886 const fs_reg srcs[] = {
2887 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)
2888 };
2889 fs_reg patch_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2890 bld.LOAD_PAYLOAD(patch_handle, srcs, ARRAY_SIZE(srcs), 0);
2891
2892 if (first_component != 0) {
2893 unsigned read_components =
2894 instr->num_components + first_component;
2895 fs_reg tmp = bld.vgrf(dest.type, read_components);
2896 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp,
2897 patch_handle);
2898 inst->size_written = read_components * REG_SIZE;
2899 for (unsigned i = 0; i < instr->num_components; i++) {
2900 bld.MOV(offset(dest, bld, i),
2901 offset(tmp, bld, i + first_component));
2902 }
2903 } else {
2904 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dest,
2905 patch_handle);
2906 inst->size_written = instr->num_components * REG_SIZE;
2907 }
2908 inst->mlen = 1;
2909 inst->offset = imm_offset;
2910 }
2911 } else {
2912 /* Indirect indexing - use per-slot offsets as well. */
2913
2914 /* We can only read two double components with each URB read, so
2915 * we send two read messages in that case, each one loading up to
2916 * two double components.
2917 */
2918 unsigned num_iterations = 1;
2919 unsigned num_components = instr->num_components;
2920 fs_reg orig_dest = dest;
2921 if (type_sz(dest.type) == 8) {
2922 if (instr->num_components > 2) {
2923 num_iterations = 2;
2924 num_components = 2;
2925 }
2926 fs_reg tmp = fs_reg(VGRF, alloc.allocate(4), dest.type);
2927 dest = tmp;
2928 }
2929
2930 for (unsigned iter = 0; iter < num_iterations; iter++) {
2931 const fs_reg srcs[] = {
2932 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD),
2933 indirect_offset
2934 };
2935 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
2936 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2937
2938 if (first_component != 0) {
2939 unsigned read_components =
2940 num_components + first_component;
2941 fs_reg tmp = bld.vgrf(dest.type, read_components);
2942 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
2943 payload);
2944 for (unsigned i = 0; i < num_components; i++) {
2945 bld.MOV(offset(dest, bld, i),
2946 offset(tmp, bld, i + first_component));
2947 }
2948 } else {
2949 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dest,
2950 payload);
2951 }
2952 inst->mlen = 2;
2953 inst->offset = imm_offset;
2954 inst->size_written = (num_components + first_component) *
2955 inst->dst.component_size(inst->exec_size);
2956
2957 /* If we are reading 64-bit data using 32-bit read messages we need
2958 * build proper 64-bit data elements by shuffling the low and high
2959 * 32-bit components around like we do for other things like UBOs
2960 * or SSBOs.
2961 */
2962 if (type_sz(dest.type) == 8) {
2963 shuffle_32bit_load_result_to_64bit_data(
2964 bld, dest, retype(dest, BRW_REGISTER_TYPE_F), num_components);
2965
2966 for (unsigned c = 0; c < num_components; c++) {
2967 bld.MOV(offset(orig_dest, bld, iter * 2 + c),
2968 offset(dest, bld, c));
2969 }
2970 }
2971
2972 /* If we are loading double data and we need a second read message
2973 * adjust the offset
2974 */
2975 if (num_iterations > 1) {
2976 num_components = instr->num_components - 2;
2977 imm_offset++;
2978 }
2979 }
2980 }
2981 break;
2982 }
2983 default:
2984 nir_emit_intrinsic(bld, instr);
2985 break;
2986 }
2987 }
2988
2989 void
nir_emit_gs_intrinsic(const fs_builder & bld,nir_intrinsic_instr * instr)2990 fs_visitor::nir_emit_gs_intrinsic(const fs_builder &bld,
2991 nir_intrinsic_instr *instr)
2992 {
2993 assert(stage == MESA_SHADER_GEOMETRY);
2994 fs_reg indirect_offset;
2995
2996 fs_reg dest;
2997 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
2998 dest = get_nir_dest(instr->dest);
2999
3000 switch (instr->intrinsic) {
3001 case nir_intrinsic_load_primitive_id:
3002 assert(stage == MESA_SHADER_GEOMETRY);
3003 assert(brw_gs_prog_data(prog_data)->include_primitive_id);
3004 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD),
3005 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD));
3006 break;
3007
3008 case nir_intrinsic_load_input:
3009 unreachable("load_input intrinsics are invalid for the GS stage");
3010
3011 case nir_intrinsic_load_per_vertex_input:
3012 emit_gs_input_load(dest, instr->src[0], instr->const_index[0],
3013 instr->src[1], instr->num_components,
3014 nir_intrinsic_component(instr));
3015 break;
3016
3017 case nir_intrinsic_emit_vertex_with_counter:
3018 emit_gs_vertex(instr->src[0], instr->const_index[0]);
3019 break;
3020
3021 case nir_intrinsic_end_primitive_with_counter:
3022 emit_gs_end_primitive(instr->src[0]);
3023 break;
3024
3025 case nir_intrinsic_set_vertex_count:
3026 bld.MOV(this->final_gs_vertex_count, get_nir_src(instr->src[0]));
3027 break;
3028
3029 case nir_intrinsic_load_invocation_id: {
3030 fs_reg val = nir_system_values[SYSTEM_VALUE_INVOCATION_ID];
3031 assert(val.file != BAD_FILE);
3032 dest.type = val.type;
3033 bld.MOV(dest, val);
3034 break;
3035 }
3036
3037 default:
3038 nir_emit_intrinsic(bld, instr);
3039 break;
3040 }
3041 }
3042
3043 /**
3044 * Fetch the current render target layer index.
3045 */
3046 static fs_reg
fetch_render_target_array_index(const fs_builder & bld)3047 fetch_render_target_array_index(const fs_builder &bld)
3048 {
3049 if (bld.shader->devinfo->gen >= 6) {
3050 /* The render target array index is provided in the thread payload as
3051 * bits 26:16 of r0.0.
3052 */
3053 const fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_UD);
3054 bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 0, 1),
3055 brw_imm_uw(0x7ff));
3056 return idx;
3057 } else {
3058 /* Pre-SNB we only ever render into the first layer of the framebuffer
3059 * since layered rendering is not implemented.
3060 */
3061 return brw_imm_ud(0);
3062 }
3063 }
3064
3065 /**
3066 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3067 * framebuffer at the current fragment coordinates and sample index.
3068 */
3069 fs_inst *
emit_non_coherent_fb_read(const fs_builder & bld,const fs_reg & dst,unsigned target)3070 fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst,
3071 unsigned target)
3072 {
3073 const struct gen_device_info *devinfo = bld.shader->devinfo;
3074
3075 assert(bld.shader->stage == MESA_SHADER_FRAGMENT);
3076 const brw_wm_prog_key *wm_key =
3077 reinterpret_cast<const brw_wm_prog_key *>(key);
3078 assert(!wm_key->coherent_fb_fetch);
3079 const struct brw_wm_prog_data *wm_prog_data =
3080 brw_wm_prog_data(stage_prog_data);
3081
3082 /* Calculate the surface index relative to the start of the texture binding
3083 * table block, since that's what the texturing messages expect.
3084 */
3085 const unsigned surface = target +
3086 wm_prog_data->binding_table.render_target_read_start -
3087 wm_prog_data->base.binding_table.texture_start;
3088
3089 brw_mark_surface_used(
3090 bld.shader->stage_prog_data,
3091 wm_prog_data->binding_table.render_target_read_start + target);
3092
3093 /* Calculate the fragment coordinates. */
3094 const fs_reg coords = bld.vgrf(BRW_REGISTER_TYPE_UD, 3);
3095 bld.MOV(offset(coords, bld, 0), pixel_x);
3096 bld.MOV(offset(coords, bld, 1), pixel_y);
3097 bld.MOV(offset(coords, bld, 2), fetch_render_target_array_index(bld));
3098
3099 /* Calculate the sample index and MCS payload when multisampling. Luckily
3100 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3101 * shouldn't be necessary to recompile based on whether the framebuffer is
3102 * CMS or UMS.
3103 */
3104 if (wm_key->multisample_fbo &&
3105 nir_system_values[SYSTEM_VALUE_SAMPLE_ID].file == BAD_FILE)
3106 nir_system_values[SYSTEM_VALUE_SAMPLE_ID] = *emit_sampleid_setup();
3107
3108 const fs_reg sample = nir_system_values[SYSTEM_VALUE_SAMPLE_ID];
3109 const fs_reg mcs = wm_key->multisample_fbo ?
3110 emit_mcs_fetch(coords, 3, brw_imm_ud(surface)) : fs_reg();
3111
3112 /* Use either a normal or a CMS texel fetch message depending on whether
3113 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3114 * message just in case the framebuffer uses 16x multisampling, it should
3115 * be equivalent to the normal CMS fetch for lower multisampling modes.
3116 */
3117 const opcode op = !wm_key->multisample_fbo ? SHADER_OPCODE_TXF_LOGICAL :
3118 devinfo->gen >= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL :
3119 SHADER_OPCODE_TXF_CMS_LOGICAL;
3120
3121 /* Emit the instruction. */
3122 const fs_reg srcs[] = { coords, fs_reg(), brw_imm_ud(0), fs_reg(),
3123 sample, mcs,
3124 brw_imm_ud(surface), brw_imm_ud(0),
3125 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3126 STATIC_ASSERT(ARRAY_SIZE(srcs) == TEX_LOGICAL_NUM_SRCS);
3127
3128 fs_inst *inst = bld.emit(op, dst, srcs, ARRAY_SIZE(srcs));
3129 inst->size_written = 4 * inst->dst.component_size(inst->exec_size);
3130
3131 return inst;
3132 }
3133
3134 /**
3135 * Actual coherent framebuffer read implemented using the native render target
3136 * read message. Requires SKL+.
3137 */
3138 static fs_inst *
emit_coherent_fb_read(const fs_builder & bld,const fs_reg & dst,unsigned target)3139 emit_coherent_fb_read(const fs_builder &bld, const fs_reg &dst, unsigned target)
3140 {
3141 assert(bld.shader->devinfo->gen >= 9);
3142 fs_inst *inst = bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst);
3143 inst->target = target;
3144 inst->size_written = 4 * inst->dst.component_size(inst->exec_size);
3145
3146 return inst;
3147 }
3148
3149 static fs_reg
alloc_temporary(const fs_builder & bld,unsigned size,fs_reg * regs,unsigned n)3150 alloc_temporary(const fs_builder &bld, unsigned size, fs_reg *regs, unsigned n)
3151 {
3152 if (n && regs[0].file != BAD_FILE) {
3153 return regs[0];
3154
3155 } else {
3156 const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, size);
3157
3158 for (unsigned i = 0; i < n; i++)
3159 regs[i] = tmp;
3160
3161 return tmp;
3162 }
3163 }
3164
3165 static fs_reg
alloc_frag_output(fs_visitor * v,unsigned location)3166 alloc_frag_output(fs_visitor *v, unsigned location)
3167 {
3168 assert(v->stage == MESA_SHADER_FRAGMENT);
3169 const brw_wm_prog_key *const key =
3170 reinterpret_cast<const brw_wm_prog_key *>(v->key);
3171 const unsigned l = GET_FIELD(location, BRW_NIR_FRAG_OUTPUT_LOCATION);
3172 const unsigned i = GET_FIELD(location, BRW_NIR_FRAG_OUTPUT_INDEX);
3173
3174 if (i > 0 || (key->force_dual_color_blend && l == FRAG_RESULT_DATA1))
3175 return alloc_temporary(v->bld, 4, &v->dual_src_output, 1);
3176
3177 else if (l == FRAG_RESULT_COLOR)
3178 return alloc_temporary(v->bld, 4, v->outputs,
3179 MAX2(key->nr_color_regions, 1));
3180
3181 else if (l == FRAG_RESULT_DEPTH)
3182 return alloc_temporary(v->bld, 1, &v->frag_depth, 1);
3183
3184 else if (l == FRAG_RESULT_STENCIL)
3185 return alloc_temporary(v->bld, 1, &v->frag_stencil, 1);
3186
3187 else if (l == FRAG_RESULT_SAMPLE_MASK)
3188 return alloc_temporary(v->bld, 1, &v->sample_mask, 1);
3189
3190 else if (l >= FRAG_RESULT_DATA0 &&
3191 l < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS)
3192 return alloc_temporary(v->bld, 4,
3193 &v->outputs[l - FRAG_RESULT_DATA0], 1);
3194
3195 else
3196 unreachable("Invalid location");
3197 }
3198
3199 void
nir_emit_fs_intrinsic(const fs_builder & bld,nir_intrinsic_instr * instr)3200 fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
3201 nir_intrinsic_instr *instr)
3202 {
3203 assert(stage == MESA_SHADER_FRAGMENT);
3204
3205 fs_reg dest;
3206 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
3207 dest = get_nir_dest(instr->dest);
3208
3209 switch (instr->intrinsic) {
3210 case nir_intrinsic_load_front_face:
3211 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
3212 *emit_frontfacing_interpolation());
3213 break;
3214
3215 case nir_intrinsic_load_sample_pos: {
3216 fs_reg sample_pos = nir_system_values[SYSTEM_VALUE_SAMPLE_POS];
3217 assert(sample_pos.file != BAD_FILE);
3218 dest.type = sample_pos.type;
3219 bld.MOV(dest, sample_pos);
3220 bld.MOV(offset(dest, bld, 1), offset(sample_pos, bld, 1));
3221 break;
3222 }
3223
3224 case nir_intrinsic_load_layer_id:
3225 dest.type = BRW_REGISTER_TYPE_UD;
3226 bld.MOV(dest, fetch_render_target_array_index(bld));
3227 break;
3228
3229 case nir_intrinsic_load_helper_invocation:
3230 case nir_intrinsic_load_sample_mask_in:
3231 case nir_intrinsic_load_sample_id: {
3232 gl_system_value sv = nir_system_value_from_intrinsic(instr->intrinsic);
3233 fs_reg val = nir_system_values[sv];
3234 assert(val.file != BAD_FILE);
3235 dest.type = val.type;
3236 bld.MOV(dest, val);
3237 break;
3238 }
3239
3240 case nir_intrinsic_store_output: {
3241 const fs_reg src = get_nir_src(instr->src[0]);
3242 const nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
3243 assert(const_offset && "Indirect output stores not allowed");
3244 const unsigned location = nir_intrinsic_base(instr) +
3245 SET_FIELD(const_offset->u32[0], BRW_NIR_FRAG_OUTPUT_LOCATION);
3246 const fs_reg new_dest = retype(alloc_frag_output(this, location),
3247 src.type);
3248
3249 for (unsigned j = 0; j < instr->num_components; j++)
3250 bld.MOV(offset(new_dest, bld, nir_intrinsic_component(instr) + j),
3251 offset(src, bld, j));
3252
3253 break;
3254 }
3255
3256 case nir_intrinsic_load_output: {
3257 const unsigned l = GET_FIELD(nir_intrinsic_base(instr),
3258 BRW_NIR_FRAG_OUTPUT_LOCATION);
3259 assert(l >= FRAG_RESULT_DATA0);
3260 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
3261 assert(const_offset && "Indirect output loads not allowed");
3262 const unsigned target = l - FRAG_RESULT_DATA0 + const_offset->u32[0];
3263 const fs_reg tmp = bld.vgrf(dest.type, 4);
3264
3265 if (reinterpret_cast<const brw_wm_prog_key *>(key)->coherent_fb_fetch)
3266 emit_coherent_fb_read(bld, tmp, target);
3267 else
3268 emit_non_coherent_fb_read(bld, tmp, target);
3269
3270 for (unsigned j = 0; j < instr->num_components; j++) {
3271 bld.MOV(offset(dest, bld, j),
3272 offset(tmp, bld, nir_intrinsic_component(instr) + j));
3273 }
3274
3275 break;
3276 }
3277
3278 case nir_intrinsic_discard:
3279 case nir_intrinsic_discard_if: {
3280 /* We track our discarded pixels in f0.1. By predicating on it, we can
3281 * update just the flag bits that aren't yet discarded. If there's no
3282 * condition, we emit a CMP of g0 != g0, so all currently executing
3283 * channels will get turned off.
3284 */
3285 fs_inst *cmp;
3286 if (instr->intrinsic == nir_intrinsic_discard_if) {
3287 cmp = bld.CMP(bld.null_reg_f(), get_nir_src(instr->src[0]),
3288 brw_imm_d(0), BRW_CONDITIONAL_Z);
3289 } else {
3290 fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
3291 BRW_REGISTER_TYPE_UW));
3292 cmp = bld.CMP(bld.null_reg_f(), some_reg, some_reg, BRW_CONDITIONAL_NZ);
3293 }
3294 cmp->predicate = BRW_PREDICATE_NORMAL;
3295 cmp->flag_subreg = 1;
3296
3297 if (devinfo->gen >= 6) {
3298 emit_discard_jump();
3299 }
3300 break;
3301 }
3302
3303 case nir_intrinsic_load_input: {
3304 /* load_input is only used for flat inputs */
3305 unsigned base = nir_intrinsic_base(instr);
3306 unsigned component = nir_intrinsic_component(instr);
3307 unsigned num_components = instr->num_components;
3308 enum brw_reg_type type = dest.type;
3309
3310 /* Special case fields in the VUE header */
3311 if (base == VARYING_SLOT_LAYER)
3312 component = 1;
3313 else if (base == VARYING_SLOT_VIEWPORT)
3314 component = 2;
3315
3316 if (nir_dest_bit_size(instr->dest) == 64) {
3317 /* const_index is in 32-bit type size units that could not be aligned
3318 * with DF. We need to read the double vector as if it was a float
3319 * vector of twice the number of components to fetch the right data.
3320 */
3321 type = BRW_REGISTER_TYPE_F;
3322 num_components *= 2;
3323 }
3324
3325 for (unsigned int i = 0; i < num_components; i++) {
3326 struct brw_reg interp = interp_reg(base, component + i);
3327 interp = suboffset(interp, 3);
3328 bld.emit(FS_OPCODE_CINTERP, offset(retype(dest, type), bld, i),
3329 retype(fs_reg(interp), type));
3330 }
3331
3332 if (nir_dest_bit_size(instr->dest) == 64) {
3333 shuffle_32bit_load_result_to_64bit_data(bld,
3334 dest,
3335 retype(dest, type),
3336 instr->num_components);
3337 }
3338 break;
3339 }
3340
3341 case nir_intrinsic_load_barycentric_pixel:
3342 case nir_intrinsic_load_barycentric_centroid:
3343 case nir_intrinsic_load_barycentric_sample:
3344 /* Do nothing - load_interpolated_input handling will handle it later. */
3345 break;
3346
3347 case nir_intrinsic_load_barycentric_at_sample: {
3348 const glsl_interp_mode interpolation =
3349 (enum glsl_interp_mode) nir_intrinsic_interp_mode(instr);
3350
3351 nir_const_value *const_sample = nir_src_as_const_value(instr->src[0]);
3352
3353 if (const_sample) {
3354 unsigned msg_data = const_sample->i32[0] << 4;
3355
3356 emit_pixel_interpolater_send(bld,
3357 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
3358 dest,
3359 fs_reg(), /* src */
3360 brw_imm_ud(msg_data),
3361 interpolation);
3362 } else {
3363 const fs_reg sample_src = retype(get_nir_src(instr->src[0]),
3364 BRW_REGISTER_TYPE_UD);
3365
3366 if (nir_src_is_dynamically_uniform(instr->src[0])) {
3367 const fs_reg sample_id = bld.emit_uniformize(sample_src);
3368 const fs_reg msg_data = vgrf(glsl_type::uint_type);
3369 bld.exec_all().group(1, 0)
3370 .SHL(msg_data, sample_id, brw_imm_ud(4u));
3371 emit_pixel_interpolater_send(bld,
3372 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
3373 dest,
3374 fs_reg(), /* src */
3375 msg_data,
3376 interpolation);
3377 } else {
3378 /* Make a loop that sends a message to the pixel interpolater
3379 * for the sample number in each live channel. If there are
3380 * multiple channels with the same sample number then these
3381 * will be handled simultaneously with a single interation of
3382 * the loop.
3383 */
3384 bld.emit(BRW_OPCODE_DO);
3385
3386 /* Get the next live sample number into sample_id_reg */
3387 const fs_reg sample_id = bld.emit_uniformize(sample_src);
3388
3389 /* Set the flag register so that we can perform the send
3390 * message on all channels that have the same sample number
3391 */
3392 bld.CMP(bld.null_reg_ud(),
3393 sample_src, sample_id,
3394 BRW_CONDITIONAL_EQ);
3395 const fs_reg msg_data = vgrf(glsl_type::uint_type);
3396 bld.exec_all().group(1, 0)
3397 .SHL(msg_data, sample_id, brw_imm_ud(4u));
3398 fs_inst *inst =
3399 emit_pixel_interpolater_send(bld,
3400 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
3401 dest,
3402 fs_reg(), /* src */
3403 msg_data,
3404 interpolation);
3405 set_predicate(BRW_PREDICATE_NORMAL, inst);
3406
3407 /* Continue the loop if there are any live channels left */
3408 set_predicate_inv(BRW_PREDICATE_NORMAL,
3409 true, /* inverse */
3410 bld.emit(BRW_OPCODE_WHILE));
3411 }
3412 }
3413 break;
3414 }
3415
3416 case nir_intrinsic_load_barycentric_at_offset: {
3417 const glsl_interp_mode interpolation =
3418 (enum glsl_interp_mode) nir_intrinsic_interp_mode(instr);
3419
3420 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
3421
3422 if (const_offset) {
3423 unsigned off_x = MIN2((int)(const_offset->f32[0] * 16), 7) & 0xf;
3424 unsigned off_y = MIN2((int)(const_offset->f32[1] * 16), 7) & 0xf;
3425
3426 emit_pixel_interpolater_send(bld,
3427 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
3428 dest,
3429 fs_reg(), /* src */
3430 brw_imm_ud(off_x | (off_y << 4)),
3431 interpolation);
3432 } else {
3433 fs_reg src = vgrf(glsl_type::ivec2_type);
3434 fs_reg offset_src = retype(get_nir_src(instr->src[0]),
3435 BRW_REGISTER_TYPE_F);
3436 for (int i = 0; i < 2; i++) {
3437 fs_reg temp = vgrf(glsl_type::float_type);
3438 bld.MUL(temp, offset(offset_src, bld, i), brw_imm_f(16.0f));
3439 fs_reg itemp = vgrf(glsl_type::int_type);
3440 /* float to int */
3441 bld.MOV(itemp, temp);
3442
3443 /* Clamp the upper end of the range to +7/16.
3444 * ARB_gpu_shader5 requires that we support a maximum offset
3445 * of +0.5, which isn't representable in a S0.4 value -- if
3446 * we didn't clamp it, we'd end up with -8/16, which is the
3447 * opposite of what the shader author wanted.
3448 *
3449 * This is legal due to ARB_gpu_shader5's quantization
3450 * rules:
3451 *
3452 * "Not all values of <offset> may be supported; x and y
3453 * offsets may be rounded to fixed-point values with the
3454 * number of fraction bits given by the
3455 * implementation-dependent constant
3456 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3457 */
3458 set_condmod(BRW_CONDITIONAL_L,
3459 bld.SEL(offset(src, bld, i), itemp, brw_imm_d(7)));
3460 }
3461
3462 const enum opcode opcode = FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET;
3463 emit_pixel_interpolater_send(bld,
3464 opcode,
3465 dest,
3466 src,
3467 brw_imm_ud(0u),
3468 interpolation);
3469 }
3470 break;
3471 }
3472
3473 case nir_intrinsic_load_interpolated_input: {
3474 if (nir_intrinsic_base(instr) == VARYING_SLOT_POS) {
3475 emit_fragcoord_interpolation(dest);
3476 break;
3477 }
3478
3479 assert(instr->src[0].ssa &&
3480 instr->src[0].ssa->parent_instr->type == nir_instr_type_intrinsic);
3481 nir_intrinsic_instr *bary_intrinsic =
3482 nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
3483 nir_intrinsic_op bary_intrin = bary_intrinsic->intrinsic;
3484 enum glsl_interp_mode interp_mode =
3485 (enum glsl_interp_mode) nir_intrinsic_interp_mode(bary_intrinsic);
3486 fs_reg dst_xy;
3487
3488 if (bary_intrin == nir_intrinsic_load_barycentric_at_offset ||
3489 bary_intrin == nir_intrinsic_load_barycentric_at_sample) {
3490 /* Use the result of the PI message */
3491 dst_xy = retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_F);
3492 } else {
3493 /* Use the delta_xy values computed from the payload */
3494 enum brw_barycentric_mode bary =
3495 brw_barycentric_mode(interp_mode, bary_intrin);
3496
3497 dst_xy = this->delta_xy[bary];
3498 }
3499
3500 for (unsigned int i = 0; i < instr->num_components; i++) {
3501 fs_reg interp =
3502 fs_reg(interp_reg(nir_intrinsic_base(instr),
3503 nir_intrinsic_component(instr) + i));
3504 interp.type = BRW_REGISTER_TYPE_F;
3505 dest.type = BRW_REGISTER_TYPE_F;
3506
3507 if (devinfo->gen < 6 && interp_mode == INTERP_MODE_SMOOTH) {
3508 fs_reg tmp = vgrf(glsl_type::float_type);
3509 bld.emit(FS_OPCODE_LINTERP, tmp, dst_xy, interp);
3510 bld.MUL(offset(dest, bld, i), tmp, this->pixel_w);
3511 } else {
3512 bld.emit(FS_OPCODE_LINTERP, offset(dest, bld, i), dst_xy, interp);
3513 }
3514 }
3515 break;
3516 }
3517
3518 default:
3519 nir_emit_intrinsic(bld, instr);
3520 break;
3521 }
3522 }
3523
3524 void
nir_emit_cs_intrinsic(const fs_builder & bld,nir_intrinsic_instr * instr)3525 fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
3526 nir_intrinsic_instr *instr)
3527 {
3528 assert(stage == MESA_SHADER_COMPUTE);
3529 struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data);
3530
3531 fs_reg dest;
3532 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
3533 dest = get_nir_dest(instr->dest);
3534
3535 switch (instr->intrinsic) {
3536 case nir_intrinsic_barrier:
3537 emit_barrier();
3538 cs_prog_data->uses_barrier = true;
3539 break;
3540
3541 case nir_intrinsic_load_subgroup_id:
3542 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), subgroup_id);
3543 break;
3544
3545 case nir_intrinsic_load_local_invocation_id:
3546 case nir_intrinsic_load_work_group_id: {
3547 gl_system_value sv = nir_system_value_from_intrinsic(instr->intrinsic);
3548 fs_reg val = nir_system_values[sv];
3549 assert(val.file != BAD_FILE);
3550 dest.type = val.type;
3551 for (unsigned i = 0; i < 3; i++)
3552 bld.MOV(offset(dest, bld, i), offset(val, bld, i));
3553 break;
3554 }
3555
3556 case nir_intrinsic_load_num_work_groups: {
3557 const unsigned surface =
3558 cs_prog_data->binding_table.work_groups_start;
3559
3560 cs_prog_data->uses_num_work_groups = true;
3561
3562 fs_reg surf_index = brw_imm_ud(surface);
3563 brw_mark_surface_used(prog_data, surface);
3564
3565 /* Read the 3 GLuint components of gl_NumWorkGroups */
3566 for (unsigned i = 0; i < 3; i++) {
3567 fs_reg read_result =
3568 emit_untyped_read(bld, surf_index,
3569 brw_imm_ud(i << 2),
3570 1 /* dims */, 1 /* size */,
3571 BRW_PREDICATE_NONE);
3572 read_result.type = dest.type;
3573 bld.MOV(dest, read_result);
3574 dest = offset(dest, bld, 1);
3575 }
3576 break;
3577 }
3578
3579 case nir_intrinsic_shared_atomic_add:
3580 nir_emit_shared_atomic(bld, BRW_AOP_ADD, instr);
3581 break;
3582 case nir_intrinsic_shared_atomic_imin:
3583 nir_emit_shared_atomic(bld, BRW_AOP_IMIN, instr);
3584 break;
3585 case nir_intrinsic_shared_atomic_umin:
3586 nir_emit_shared_atomic(bld, BRW_AOP_UMIN, instr);
3587 break;
3588 case nir_intrinsic_shared_atomic_imax:
3589 nir_emit_shared_atomic(bld, BRW_AOP_IMAX, instr);
3590 break;
3591 case nir_intrinsic_shared_atomic_umax:
3592 nir_emit_shared_atomic(bld, BRW_AOP_UMAX, instr);
3593 break;
3594 case nir_intrinsic_shared_atomic_and:
3595 nir_emit_shared_atomic(bld, BRW_AOP_AND, instr);
3596 break;
3597 case nir_intrinsic_shared_atomic_or:
3598 nir_emit_shared_atomic(bld, BRW_AOP_OR, instr);
3599 break;
3600 case nir_intrinsic_shared_atomic_xor:
3601 nir_emit_shared_atomic(bld, BRW_AOP_XOR, instr);
3602 break;
3603 case nir_intrinsic_shared_atomic_exchange:
3604 nir_emit_shared_atomic(bld, BRW_AOP_MOV, instr);
3605 break;
3606 case nir_intrinsic_shared_atomic_comp_swap:
3607 nir_emit_shared_atomic(bld, BRW_AOP_CMPWR, instr);
3608 break;
3609
3610 case nir_intrinsic_load_shared: {
3611 assert(devinfo->gen >= 7);
3612
3613 fs_reg surf_index = brw_imm_ud(GEN7_BTI_SLM);
3614
3615 /* Get the offset to read from */
3616 fs_reg offset_reg;
3617 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
3618 if (const_offset) {
3619 offset_reg = brw_imm_ud(instr->const_index[0] + const_offset->u32[0]);
3620 } else {
3621 offset_reg = vgrf(glsl_type::uint_type);
3622 bld.ADD(offset_reg,
3623 retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
3624 brw_imm_ud(instr->const_index[0]));
3625 }
3626
3627 /* Read the vector */
3628 do_untyped_vector_read(bld, dest, surf_index, offset_reg,
3629 instr->num_components);
3630 break;
3631 }
3632
3633 case nir_intrinsic_store_shared: {
3634 assert(devinfo->gen >= 7);
3635
3636 /* Block index */
3637 fs_reg surf_index = brw_imm_ud(GEN7_BTI_SLM);
3638
3639 /* Value */
3640 fs_reg val_reg = get_nir_src(instr->src[0]);
3641
3642 /* Writemask */
3643 unsigned writemask = instr->const_index[1];
3644
3645 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3646 * since the untyped writes below operate in units of 32-bits, which
3647 * means that we need to write twice as many components each time.
3648 * Also, we have to suffle 64-bit data to be in the appropriate layout
3649 * expected by our 32-bit write messages.
3650 */
3651 unsigned type_size = 4;
3652 if (nir_src_bit_size(instr->src[0]) == 64) {
3653 type_size = 8;
3654 val_reg = shuffle_64bit_data_for_32bit_write(bld,
3655 val_reg, instr->num_components);
3656 }
3657
3658 unsigned type_slots = type_size / 4;
3659
3660 /* Combine groups of consecutive enabled channels in one write
3661 * message. We use ffs to find the first enabled channel and then ffs on
3662 * the bit-inverse, down-shifted writemask to determine the length of
3663 * the block of enabled bits.
3664 */
3665 while (writemask) {
3666 unsigned first_component = ffs(writemask) - 1;
3667 unsigned length = ffs(~(writemask >> first_component)) - 1;
3668
3669 /* We can't write more than 2 64-bit components at once. Limit the
3670 * length of the write to what we can do and let the next iteration
3671 * handle the rest
3672 */
3673 if (type_size > 4)
3674 length = MIN2(2, length);
3675
3676 fs_reg offset_reg;
3677 nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
3678 if (const_offset) {
3679 offset_reg = brw_imm_ud(instr->const_index[0] + const_offset->u32[0] +
3680 type_size * first_component);
3681 } else {
3682 offset_reg = vgrf(glsl_type::uint_type);
3683 bld.ADD(offset_reg,
3684 retype(get_nir_src(instr->src[1]), BRW_REGISTER_TYPE_UD),
3685 brw_imm_ud(instr->const_index[0] + type_size * first_component));
3686 }
3687
3688 emit_untyped_write(bld, surf_index, offset_reg,
3689 offset(val_reg, bld, first_component * type_slots),
3690 1 /* dims */, length * type_slots,
3691 BRW_PREDICATE_NONE);
3692
3693 /* Clear the bits in the writemask that we just wrote, then try
3694 * again to see if more channels are left.
3695 */
3696 writemask &= (15 << (first_component + length));
3697 }
3698
3699 break;
3700 }
3701
3702 default:
3703 nir_emit_intrinsic(bld, instr);
3704 break;
3705 }
3706 }
3707
3708 void
nir_emit_intrinsic(const fs_builder & bld,nir_intrinsic_instr * instr)3709 fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr)
3710 {
3711 fs_reg dest;
3712 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
3713 dest = get_nir_dest(instr->dest);
3714
3715 switch (instr->intrinsic) {
3716 case nir_intrinsic_image_load:
3717 case nir_intrinsic_image_store:
3718 case nir_intrinsic_image_atomic_add:
3719 case nir_intrinsic_image_atomic_min:
3720 case nir_intrinsic_image_atomic_max:
3721 case nir_intrinsic_image_atomic_and:
3722 case nir_intrinsic_image_atomic_or:
3723 case nir_intrinsic_image_atomic_xor:
3724 case nir_intrinsic_image_atomic_exchange:
3725 case nir_intrinsic_image_atomic_comp_swap: {
3726 using namespace image_access;
3727
3728 if (stage == MESA_SHADER_FRAGMENT &&
3729 instr->intrinsic != nir_intrinsic_image_load)
3730 brw_wm_prog_data(prog_data)->has_side_effects = true;
3731
3732 /* Get the referenced image variable and type. */
3733 const nir_variable *var = instr->variables[0]->var;
3734 const glsl_type *type = var->type->without_array();
3735 const brw_reg_type base_type = get_image_base_type(type);
3736
3737 /* Get some metadata from the image intrinsic. */
3738 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
3739 const unsigned arr_dims = type->sampler_array ? 1 : 0;
3740 const unsigned surf_dims = type->coordinate_components() - arr_dims;
3741 const unsigned format = var->data.image.format;
3742
3743 /* Get the arguments of the image intrinsic. */
3744 const fs_reg image = get_nir_image_deref(instr->variables[0]);
3745 const fs_reg addr = retype(get_nir_src(instr->src[0]),
3746 BRW_REGISTER_TYPE_UD);
3747 const fs_reg src0 = (info->num_srcs >= 3 ?
3748 retype(get_nir_src(instr->src[2]), base_type) :
3749 fs_reg());
3750 const fs_reg src1 = (info->num_srcs >= 4 ?
3751 retype(get_nir_src(instr->src[3]), base_type) :
3752 fs_reg());
3753 fs_reg tmp;
3754
3755 /* Emit an image load, store or atomic op. */
3756 if (instr->intrinsic == nir_intrinsic_image_load)
3757 tmp = emit_image_load(bld, image, addr, surf_dims, arr_dims, format);
3758
3759 else if (instr->intrinsic == nir_intrinsic_image_store)
3760 emit_image_store(bld, image, addr, src0, surf_dims, arr_dims,
3761 var->data.image.write_only ? GL_NONE : format);
3762
3763 else
3764 tmp = emit_image_atomic(bld, image, addr, src0, src1,
3765 surf_dims, arr_dims, info->dest_components,
3766 get_image_atomic_op(instr->intrinsic, type));
3767
3768 /* Assign the result. */
3769 for (unsigned c = 0; c < info->dest_components; ++c)
3770 bld.MOV(offset(retype(dest, base_type), bld, c),
3771 offset(tmp, bld, c));
3772 break;
3773 }
3774
3775 case nir_intrinsic_memory_barrier_atomic_counter:
3776 case nir_intrinsic_memory_barrier_buffer:
3777 case nir_intrinsic_memory_barrier_image:
3778 case nir_intrinsic_memory_barrier: {
3779 const fs_builder ubld = bld.group(8, 0);
3780 const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);
3781 ubld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp)
3782 ->size_written = 2 * REG_SIZE;
3783 break;
3784 }
3785
3786 case nir_intrinsic_group_memory_barrier:
3787 case nir_intrinsic_memory_barrier_shared:
3788 /* We treat these workgroup-level barriers as no-ops. This should be
3789 * safe at present and as long as:
3790 *
3791 * - Memory access instructions are not subsequently reordered by the
3792 * compiler back-end.
3793 *
3794 * - All threads from a given compute shader workgroup fit within a
3795 * single subslice and therefore talk to the same HDC shared unit
3796 * what supposedly guarantees ordering and coherency between threads
3797 * from the same workgroup. This may change in the future when we
3798 * start splitting workgroups across multiple subslices.
3799 *
3800 * - The context is not in fault-and-stream mode, which could cause
3801 * memory transactions (including to SLM) prior to the barrier to be
3802 * replayed after the barrier if a pagefault occurs. This shouldn't
3803 * be a problem up to and including SKL because fault-and-stream is
3804 * not usable due to hardware issues, but that's likely to change in
3805 * the future.
3806 */
3807 break;
3808
3809 case nir_intrinsic_shader_clock: {
3810 /* We cannot do anything if there is an event, so ignore it for now */
3811 const fs_reg shader_clock = get_timestamp(bld);
3812 const fs_reg srcs[] = { component(shader_clock, 0),
3813 component(shader_clock, 1) };
3814 bld.LOAD_PAYLOAD(dest, srcs, ARRAY_SIZE(srcs), 0);
3815 break;
3816 }
3817
3818 case nir_intrinsic_image_size: {
3819 /* Get the referenced image variable and type. */
3820 const nir_variable *var = instr->variables[0]->var;
3821 const glsl_type *type = var->type->without_array();
3822
3823 /* Get the size of the image. */
3824 const fs_reg image = get_nir_image_deref(instr->variables[0]);
3825 const fs_reg size = offset(image, bld, BRW_IMAGE_PARAM_SIZE_OFFSET);
3826
3827 /* For 1DArray image types, the array index is stored in the Z component.
3828 * Fix this by swizzling the Z component to the Y component.
3829 */
3830 const bool is_1d_array_image =
3831 type->sampler_dimensionality == GLSL_SAMPLER_DIM_1D &&
3832 type->sampler_array;
3833
3834 /* For CubeArray images, we should count the number of cubes instead
3835 * of the number of faces. Fix it by dividing the (Z component) by 6.
3836 */
3837 const bool is_cube_array_image =
3838 type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
3839 type->sampler_array;
3840
3841 /* Copy all the components. */
3842 for (unsigned c = 0; c < instr->dest.ssa.num_components; ++c) {
3843 if ((int)c >= type->coordinate_components()) {
3844 bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
3845 brw_imm_d(1));
3846 } else if (c == 1 && is_1d_array_image) {
3847 bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
3848 offset(size, bld, 2));
3849 } else if (c == 2 && is_cube_array_image) {
3850 bld.emit(SHADER_OPCODE_INT_QUOTIENT,
3851 offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
3852 offset(size, bld, c), brw_imm_d(6));
3853 } else {
3854 bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
3855 offset(size, bld, c));
3856 }
3857 }
3858
3859 break;
3860 }
3861
3862 case nir_intrinsic_image_samples:
3863 /* The driver does not support multi-sampled images. */
3864 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), brw_imm_d(1));
3865 break;
3866
3867 case nir_intrinsic_load_uniform: {
3868 /* Offsets are in bytes but they should always be multiples of 4 */
3869 assert(instr->const_index[0] % 4 == 0);
3870
3871 fs_reg src(UNIFORM, instr->const_index[0] / 4, dest.type);
3872
3873 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
3874 if (const_offset) {
3875 /* Offsets are in bytes but they should always be multiples of 4 */
3876 assert(const_offset->u32[0] % 4 == 0);
3877 src.offset = const_offset->u32[0];
3878
3879 for (unsigned j = 0; j < instr->num_components; j++) {
3880 bld.MOV(offset(dest, bld, j), offset(src, bld, j));
3881 }
3882 } else {
3883 fs_reg indirect = retype(get_nir_src(instr->src[0]),
3884 BRW_REGISTER_TYPE_UD);
3885
3886 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3887 * go past the end of the uniform. In order to keep the n'th
3888 * component from running past, we subtract off the size of all but
3889 * one component of the vector.
3890 */
3891 assert(instr->const_index[1] >=
3892 instr->num_components * (int) type_sz(dest.type));
3893 unsigned read_size = instr->const_index[1] -
3894 (instr->num_components - 1) * type_sz(dest.type);
3895
3896 bool supports_64bit_indirects =
3897 !devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo);
3898
3899 if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
3900 for (unsigned j = 0; j < instr->num_components; j++) {
3901 bld.emit(SHADER_OPCODE_MOV_INDIRECT,
3902 offset(dest, bld, j), offset(src, bld, j),
3903 indirect, brw_imm_ud(read_size));
3904 }
3905 } else {
3906 const unsigned num_mov_indirects =
3907 type_sz(dest.type) / type_sz(BRW_REGISTER_TYPE_UD);
3908 /* We read a little bit less per MOV INDIRECT, as they are now
3909 * 32-bits ones instead of 64-bit. Fix read_size then.
3910 */
3911 const unsigned read_size_32bit = read_size -
3912 (num_mov_indirects - 1) * type_sz(BRW_REGISTER_TYPE_UD);
3913 for (unsigned j = 0; j < instr->num_components; j++) {
3914 for (unsigned i = 0; i < num_mov_indirects; i++) {
3915 bld.emit(SHADER_OPCODE_MOV_INDIRECT,
3916 subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, i),
3917 subscript(offset(src, bld, j), BRW_REGISTER_TYPE_UD, i),
3918 indirect, brw_imm_ud(read_size_32bit));
3919 }
3920 }
3921 }
3922 }
3923 break;
3924 }
3925
3926 case nir_intrinsic_load_ubo: {
3927 nir_const_value *const_index = nir_src_as_const_value(instr->src[0]);
3928 fs_reg surf_index;
3929
3930 if (const_index) {
3931 const unsigned index = stage_prog_data->binding_table.ubo_start +
3932 const_index->u32[0];
3933 surf_index = brw_imm_ud(index);
3934 brw_mark_surface_used(prog_data, index);
3935 } else {
3936 /* The block index is not a constant. Evaluate the index expression
3937 * per-channel and add the base UBO index; we have to select a value
3938 * from any live channel.
3939 */
3940 surf_index = vgrf(glsl_type::uint_type);
3941 bld.ADD(surf_index, get_nir_src(instr->src[0]),
3942 brw_imm_ud(stage_prog_data->binding_table.ubo_start));
3943 surf_index = bld.emit_uniformize(surf_index);
3944
3945 /* Assume this may touch any UBO. It would be nice to provide
3946 * a tighter bound, but the array information is already lowered away.
3947 */
3948 brw_mark_surface_used(prog_data,
3949 stage_prog_data->binding_table.ubo_start +
3950 nir->info.num_ubos - 1);
3951 }
3952
3953 nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
3954 if (const_offset == NULL) {
3955 fs_reg base_offset = retype(get_nir_src(instr->src[1]),
3956 BRW_REGISTER_TYPE_UD);
3957
3958 for (int i = 0; i < instr->num_components; i++)
3959 VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
3960 base_offset, i * type_sz(dest.type));
3961 } else {
3962 /* Even if we are loading doubles, a pull constant load will load
3963 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3964 * need to load a full dvec4 we will have to emit 2 loads. This is
3965 * similar to demote_pull_constants(), except that in that case we
3966 * see individual accesses to each component of the vector and then
3967 * we let CSE deal with duplicate loads. Here we see a vector access
3968 * and we have to split it if necessary.
3969 */
3970 const unsigned type_size = type_sz(dest.type);
3971
3972 /* See if we've selected this as a push constant candidate */
3973 if (const_index) {
3974 const unsigned ubo_block = const_index->u32[0];
3975 const unsigned offset_256b = const_offset->u32[0] / 32;
3976
3977 fs_reg push_reg;
3978 for (int i = 0; i < 4; i++) {
3979 const struct brw_ubo_range *range = &prog_data->ubo_ranges[i];
3980 if (range->block == ubo_block &&
3981 offset_256b >= range->start &&
3982 offset_256b < range->start + range->length) {
3983
3984 push_reg = fs_reg(UNIFORM, UBO_START + i, dest.type);
3985 push_reg.offset = const_offset->u32[0] - 32 * range->start;
3986 break;
3987 }
3988 }
3989
3990 if (push_reg.file != BAD_FILE) {
3991 for (unsigned i = 0; i < instr->num_components; i++) {
3992 bld.MOV(offset(dest, bld, i),
3993 byte_offset(push_reg, i * type_size));
3994 }
3995 break;
3996 }
3997 }
3998
3999 const unsigned block_sz = 64; /* Fetch one cacheline at a time. */
4000 const fs_builder ubld = bld.exec_all().group(block_sz / 4, 0);
4001 const fs_reg packed_consts = ubld.vgrf(BRW_REGISTER_TYPE_UD);
4002
4003 for (unsigned c = 0; c < instr->num_components;) {
4004 const unsigned base = const_offset->u32[0] + c * type_size;
4005 /* Number of usable components in the next block-aligned load. */
4006 const unsigned count = MIN2(instr->num_components - c,
4007 (block_sz - base % block_sz) / type_size);
4008
4009 ubld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
4010 packed_consts, surf_index,
4011 brw_imm_ud(base & ~(block_sz - 1)));
4012
4013 const fs_reg consts =
4014 retype(byte_offset(packed_consts, base & (block_sz - 1)),
4015 dest.type);
4016
4017 for (unsigned d = 0; d < count; d++)
4018 bld.MOV(offset(dest, bld, c + d), component(consts, d));
4019
4020 c += count;
4021 }
4022 }
4023 break;
4024 }
4025
4026 case nir_intrinsic_load_ssbo: {
4027 assert(devinfo->gen >= 7);
4028
4029 nir_const_value *const_uniform_block =
4030 nir_src_as_const_value(instr->src[0]);
4031
4032 fs_reg surf_index;
4033 if (const_uniform_block) {
4034 unsigned index = stage_prog_data->binding_table.ssbo_start +
4035 const_uniform_block->u32[0];
4036 surf_index = brw_imm_ud(index);
4037 brw_mark_surface_used(prog_data, index);
4038 } else {
4039 surf_index = vgrf(glsl_type::uint_type);
4040 bld.ADD(surf_index, get_nir_src(instr->src[0]),
4041 brw_imm_ud(stage_prog_data->binding_table.ssbo_start));
4042
4043 /* Assume this may touch any UBO. It would be nice to provide
4044 * a tighter bound, but the array information is already lowered away.
4045 */
4046 brw_mark_surface_used(prog_data,
4047 stage_prog_data->binding_table.ssbo_start +
4048 nir->info.num_ssbos - 1);
4049 }
4050
4051 fs_reg offset_reg;
4052 nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
4053 if (const_offset) {
4054 offset_reg = brw_imm_ud(const_offset->u32[0]);
4055 } else {
4056 offset_reg = get_nir_src(instr->src[1]);
4057 }
4058
4059 /* Read the vector */
4060 do_untyped_vector_read(bld, dest, surf_index, offset_reg,
4061 instr->num_components);
4062
4063 break;
4064 }
4065
4066 case nir_intrinsic_store_ssbo: {
4067 assert(devinfo->gen >= 7);
4068
4069 if (stage == MESA_SHADER_FRAGMENT)
4070 brw_wm_prog_data(prog_data)->has_side_effects = true;
4071
4072 /* Block index */
4073 fs_reg surf_index;
4074 nir_const_value *const_uniform_block =
4075 nir_src_as_const_value(instr->src[1]);
4076 if (const_uniform_block) {
4077 unsigned index = stage_prog_data->binding_table.ssbo_start +
4078 const_uniform_block->u32[0];
4079 surf_index = brw_imm_ud(index);
4080 brw_mark_surface_used(prog_data, index);
4081 } else {
4082 surf_index = vgrf(glsl_type::uint_type);
4083 bld.ADD(surf_index, get_nir_src(instr->src[1]),
4084 brw_imm_ud(stage_prog_data->binding_table.ssbo_start));
4085
4086 brw_mark_surface_used(prog_data,
4087 stage_prog_data->binding_table.ssbo_start +
4088 nir->info.num_ssbos - 1);
4089 }
4090
4091 /* Value */
4092 fs_reg val_reg = get_nir_src(instr->src[0]);
4093
4094 /* Writemask */
4095 unsigned writemask = instr->const_index[0];
4096
4097 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4098 * since the untyped writes below operate in units of 32-bits, which
4099 * means that we need to write twice as many components each time.
4100 * Also, we have to suffle 64-bit data to be in the appropriate layout
4101 * expected by our 32-bit write messages.
4102 */
4103 unsigned bit_size = nir_src_bit_size(instr->src[0]);
4104 unsigned type_size = bit_size / 8;
4105
4106 /* Combine groups of consecutive enabled channels in one write
4107 * message. We use ffs to find the first enabled channel and then ffs on
4108 * the bit-inverse, down-shifted writemask to determine the num_components
4109 * of the block of enabled bits.
4110 */
4111 while (writemask) {
4112 unsigned first_component = ffs(writemask) - 1;
4113 unsigned num_components = ffs(~(writemask >> first_component)) - 1;
4114 fs_reg write_src = offset(val_reg, bld, first_component);
4115
4116 if (type_size > 4) {
4117 /* We can't write more than 2 64-bit components at once. Limit
4118 * the num_components of the write to what we can do and let the next
4119 * iteration handle the rest.
4120 */
4121 num_components = MIN2(2, num_components);
4122 write_src = shuffle_64bit_data_for_32bit_write(bld, write_src,
4123 num_components);
4124 } else if (type_size < 4) {
4125 assert(type_size == 2);
4126 /* For 16-bit types we pack two consecutive values into a 32-bit
4127 * word and use an untyped write message. For single values or not
4128 * 32-bit-aligned we need to use byte-scattered writes because
4129 * untyped writes works with 32-bit components with 32-bit
4130 * alignment. byte_scattered_write messages only support one
4131 * 16-bit component at a time.
4132 *
4133 * For example, if there is a 3-components vector we submit one
4134 * untyped-write message of 32-bit (first two components), and one
4135 * byte-scattered write message (the last component).
4136 */
4137
4138 if (first_component % 2) {
4139 /* If we use a .yz writemask we also need to emit 2
4140 * byte-scattered write messages because of y-component not
4141 * being aligned to 32-bit.
4142 */
4143 num_components = 1;
4144 } else if (num_components > 2 && (num_components % 2)) {
4145 /* If there is an odd number of consecutive components we left
4146 * the not paired component for a following emit of length == 1
4147 * with byte_scattered_write.
4148 */
4149 num_components --;
4150 }
4151 /* For num_components == 1 we are also shuffling the component
4152 * because byte scattered writes of 16-bit need values to be dword
4153 * aligned. Shuffling only one component would be the same as
4154 * striding it.
4155 */
4156 fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D,
4157 DIV_ROUND_UP(num_components, 2));
4158 shuffle_16bit_data_for_32bit_write(bld, tmp, write_src,
4159 num_components);
4160 write_src = tmp;
4161 }
4162
4163 fs_reg offset_reg;
4164 nir_const_value *const_offset = nir_src_as_const_value(instr->src[2]);
4165 if (const_offset) {
4166 offset_reg = brw_imm_ud(const_offset->u32[0] +
4167 type_size * first_component);
4168 } else {
4169 offset_reg = vgrf(glsl_type::uint_type);
4170 bld.ADD(offset_reg,
4171 retype(get_nir_src(instr->src[2]), BRW_REGISTER_TYPE_UD),
4172 brw_imm_ud(type_size * first_component));
4173 }
4174
4175 if (type_size < 4 && num_components == 1) {
4176 assert(type_size == 2);
4177 /* Untyped Surface messages have a fixed 32-bit size, so we need
4178 * to rely on byte scattered in order to write 16-bit elements.
4179 * The byte_scattered_write message needs that every written 16-bit
4180 * type to be aligned 32-bits (stride=2).
4181 * Additionally, while on Untyped Surface messages the
4182 * bits of the execution mask are ANDed with the corresponding
4183 * bits of the Pixel/Sample Mask, that is not the case for byte
4184 * scattered writes. That is needed to avoid ssbo stores writing
4185 * on helper invocations. So when that can affect, we load the
4186 * sample mask, and predicate the send message.
4187 */
4188 brw_predicate pred = BRW_PREDICATE_NONE;
4189
4190 if (stage == MESA_SHADER_FRAGMENT) {
4191 bld.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
4192 pred = BRW_PREDICATE_NORMAL;
4193 }
4194
4195 emit_byte_scattered_write(bld, surf_index, offset_reg,
4196 write_src,
4197 1 /* dims */, 1,
4198 bit_size,
4199 pred);
4200 } else {
4201 assert(num_components * type_size <= 16);
4202 assert((num_components * type_size) % 4 == 0);
4203 assert((first_component * type_size) % 4 == 0);
4204 unsigned num_slots = (num_components * type_size) / 4;
4205
4206 emit_untyped_write(bld, surf_index, offset_reg,
4207 write_src,
4208 1 /* dims */, num_slots,
4209 BRW_PREDICATE_NONE);
4210 }
4211
4212 /* Clear the bits in the writemask that we just wrote, then try
4213 * again to see if more channels are left.
4214 */
4215 writemask &= (15 << (first_component + num_components));
4216 }
4217 break;
4218 }
4219
4220 case nir_intrinsic_store_output: {
4221 fs_reg src = get_nir_src(instr->src[0]);
4222
4223 nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
4224 assert(const_offset && "Indirect output stores not allowed");
4225
4226 unsigned num_components = instr->num_components;
4227 unsigned first_component = nir_intrinsic_component(instr);
4228 if (nir_src_bit_size(instr->src[0]) == 64) {
4229 src = shuffle_64bit_data_for_32bit_write(bld, src, num_components);
4230 num_components *= 2;
4231 }
4232
4233 fs_reg new_dest = retype(offset(outputs[instr->const_index[0]], bld,
4234 4 * const_offset->u32[0]), src.type);
4235 for (unsigned j = 0; j < num_components; j++) {
4236 bld.MOV(offset(new_dest, bld, j + first_component),
4237 offset(src, bld, j));
4238 }
4239 break;
4240 }
4241
4242 case nir_intrinsic_ssbo_atomic_add:
4243 nir_emit_ssbo_atomic(bld, BRW_AOP_ADD, instr);
4244 break;
4245 case nir_intrinsic_ssbo_atomic_imin:
4246 nir_emit_ssbo_atomic(bld, BRW_AOP_IMIN, instr);
4247 break;
4248 case nir_intrinsic_ssbo_atomic_umin:
4249 nir_emit_ssbo_atomic(bld, BRW_AOP_UMIN, instr);
4250 break;
4251 case nir_intrinsic_ssbo_atomic_imax:
4252 nir_emit_ssbo_atomic(bld, BRW_AOP_IMAX, instr);
4253 break;
4254 case nir_intrinsic_ssbo_atomic_umax:
4255 nir_emit_ssbo_atomic(bld, BRW_AOP_UMAX, instr);
4256 break;
4257 case nir_intrinsic_ssbo_atomic_and:
4258 nir_emit_ssbo_atomic(bld, BRW_AOP_AND, instr);
4259 break;
4260 case nir_intrinsic_ssbo_atomic_or:
4261 nir_emit_ssbo_atomic(bld, BRW_AOP_OR, instr);
4262 break;
4263 case nir_intrinsic_ssbo_atomic_xor:
4264 nir_emit_ssbo_atomic(bld, BRW_AOP_XOR, instr);
4265 break;
4266 case nir_intrinsic_ssbo_atomic_exchange:
4267 nir_emit_ssbo_atomic(bld, BRW_AOP_MOV, instr);
4268 break;
4269 case nir_intrinsic_ssbo_atomic_comp_swap:
4270 nir_emit_ssbo_atomic(bld, BRW_AOP_CMPWR, instr);
4271 break;
4272
4273 case nir_intrinsic_get_buffer_size: {
4274 nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]);
4275 unsigned ssbo_index = const_uniform_block ? const_uniform_block->u32[0] : 0;
4276
4277 /* A resinfo's sampler message is used to get the buffer size. The
4278 * SIMD8's writeback message consists of four registers and SIMD16's
4279 * writeback message consists of 8 destination registers (two per each
4280 * component). Because we are only interested on the first channel of
4281 * the first returned component, where resinfo returns the buffer size
4282 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4283 * the dispatch width.
4284 */
4285 const fs_builder ubld = bld.exec_all().group(8, 0);
4286 fs_reg src_payload = ubld.vgrf(BRW_REGISTER_TYPE_UD);
4287 fs_reg ret_payload = ubld.vgrf(BRW_REGISTER_TYPE_UD, 4);
4288
4289 /* Set LOD = 0 */
4290 ubld.MOV(src_payload, brw_imm_d(0));
4291
4292 const unsigned index = prog_data->binding_table.ssbo_start + ssbo_index;
4293 fs_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload,
4294 src_payload, brw_imm_ud(index));
4295 inst->header_size = 0;
4296 inst->mlen = 1;
4297 inst->size_written = 4 * REG_SIZE;
4298
4299 bld.MOV(retype(dest, ret_payload.type), component(ret_payload, 0));
4300 brw_mark_surface_used(prog_data, index);
4301 break;
4302 }
4303
4304 case nir_intrinsic_load_subgroup_invocation:
4305 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
4306 nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]);
4307 break;
4308
4309 case nir_intrinsic_load_subgroup_eq_mask:
4310 case nir_intrinsic_load_subgroup_ge_mask:
4311 case nir_intrinsic_load_subgroup_gt_mask:
4312 case nir_intrinsic_load_subgroup_le_mask:
4313 case nir_intrinsic_load_subgroup_lt_mask:
4314 unreachable("not reached");
4315
4316 case nir_intrinsic_vote_any: {
4317 const fs_builder ubld = bld.exec_all().group(1, 0);
4318
4319 /* The any/all predicates do not consider channel enables. To prevent
4320 * dead channels from affecting the result, we initialize the flag with
4321 * with the identity value for the logical operation.
4322 */
4323 if (dispatch_width == 32) {
4324 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4325 ubld.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD),
4326 brw_imm_ud(0));
4327 } else {
4328 ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4329 }
4330 bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ);
4331
4332 /* For some reason, the any/all predicates don't work properly with
4333 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4334 * doesn't read the correct subset of the flag register and you end up
4335 * getting garbage in the second half. Work around this by using a pair
4336 * of 1-wide MOVs and scattering the result.
4337 */
4338 fs_reg res1 = ubld.vgrf(BRW_REGISTER_TYPE_D);
4339 ubld.MOV(res1, brw_imm_d(0));
4340 set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ANY8H :
4341 dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ANY16H :
4342 BRW_PREDICATE_ALIGN1_ANY32H,
4343 ubld.MOV(res1, brw_imm_d(-1)));
4344
4345 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0));
4346 break;
4347 }
4348 case nir_intrinsic_vote_all: {
4349 const fs_builder ubld = bld.exec_all().group(1, 0);
4350
4351 /* The any/all predicates do not consider channel enables. To prevent
4352 * dead channels from affecting the result, we initialize the flag with
4353 * with the identity value for the logical operation.
4354 */
4355 if (dispatch_width == 32) {
4356 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4357 ubld.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD),
4358 brw_imm_ud(0xffffffff));
4359 } else {
4360 ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4361 }
4362 bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ);
4363
4364 /* For some reason, the any/all predicates don't work properly with
4365 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4366 * doesn't read the correct subset of the flag register and you end up
4367 * getting garbage in the second half. Work around this by using a pair
4368 * of 1-wide MOVs and scattering the result.
4369 */
4370 fs_reg res1 = ubld.vgrf(BRW_REGISTER_TYPE_D);
4371 ubld.MOV(res1, brw_imm_d(0));
4372 set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H :
4373 dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H :
4374 BRW_PREDICATE_ALIGN1_ALL32H,
4375 ubld.MOV(res1, brw_imm_d(-1)));
4376
4377 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0));
4378 break;
4379 }
4380 case nir_intrinsic_vote_eq: {
4381 fs_reg value = get_nir_src(instr->src[0]);
4382 fs_reg uniformized = bld.emit_uniformize(value);
4383 const fs_builder ubld = bld.exec_all().group(1, 0);
4384
4385 /* The any/all predicates do not consider channel enables. To prevent
4386 * dead channels from affecting the result, we initialize the flag with
4387 * with the identity value for the logical operation.
4388 */
4389 if (dispatch_width == 32) {
4390 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4391 ubld.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD),
4392 brw_imm_ud(0xffffffff));
4393 } else {
4394 ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4395 }
4396 bld.CMP(bld.null_reg_d(), value, uniformized, BRW_CONDITIONAL_Z);
4397
4398 /* For some reason, the any/all predicates don't work properly with
4399 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4400 * doesn't read the correct subset of the flag register and you end up
4401 * getting garbage in the second half. Work around this by using a pair
4402 * of 1-wide MOVs and scattering the result.
4403 */
4404 fs_reg res1 = ubld.vgrf(BRW_REGISTER_TYPE_D);
4405 ubld.MOV(res1, brw_imm_d(0));
4406 set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H :
4407 dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H :
4408 BRW_PREDICATE_ALIGN1_ALL32H,
4409 ubld.MOV(res1, brw_imm_d(-1)));
4410
4411 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0));
4412 break;
4413 }
4414
4415 case nir_intrinsic_ballot: {
4416 const fs_reg value = retype(get_nir_src(instr->src[0]),
4417 BRW_REGISTER_TYPE_UD);
4418 struct brw_reg flag = brw_flag_reg(0, 0);
4419 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4420 * as f0.0. This is a problem for fragment programs as we currently use
4421 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4422 * programs yet so this isn't a problem. When we do, something will
4423 * have to change.
4424 */
4425 if (dispatch_width == 32)
4426 flag.type = BRW_REGISTER_TYPE_UD;
4427
4428 bld.exec_all().group(1, 0).MOV(flag, brw_imm_ud(0u));
4429 bld.CMP(bld.null_reg_ud(), value, brw_imm_ud(0u), BRW_CONDITIONAL_NZ);
4430
4431 if (instr->dest.ssa.bit_size > 32) {
4432 dest.type = BRW_REGISTER_TYPE_UQ;
4433 } else {
4434 dest.type = BRW_REGISTER_TYPE_UD;
4435 }
4436 bld.MOV(dest, flag);
4437 break;
4438 }
4439
4440 case nir_intrinsic_read_invocation: {
4441 const fs_reg value = get_nir_src(instr->src[0]);
4442 const fs_reg invocation = get_nir_src(instr->src[1]);
4443 fs_reg tmp = bld.vgrf(value.type);
4444
4445 bld.exec_all().emit(SHADER_OPCODE_BROADCAST, tmp, value,
4446 bld.emit_uniformize(invocation));
4447
4448 bld.MOV(retype(dest, value.type), fs_reg(component(tmp, 0)));
4449 break;
4450 }
4451
4452 case nir_intrinsic_read_first_invocation: {
4453 const fs_reg value = get_nir_src(instr->src[0]);
4454 bld.MOV(retype(dest, value.type), bld.emit_uniformize(value));
4455 break;
4456 }
4457
4458 default:
4459 unreachable("unknown intrinsic");
4460 }
4461 }
4462
4463 void
nir_emit_ssbo_atomic(const fs_builder & bld,int op,nir_intrinsic_instr * instr)4464 fs_visitor::nir_emit_ssbo_atomic(const fs_builder &bld,
4465 int op, nir_intrinsic_instr *instr)
4466 {
4467 if (stage == MESA_SHADER_FRAGMENT)
4468 brw_wm_prog_data(prog_data)->has_side_effects = true;
4469
4470 fs_reg dest;
4471 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
4472 dest = get_nir_dest(instr->dest);
4473
4474 fs_reg surface;
4475 nir_const_value *const_surface = nir_src_as_const_value(instr->src[0]);
4476 if (const_surface) {
4477 unsigned surf_index = stage_prog_data->binding_table.ssbo_start +
4478 const_surface->u32[0];
4479 surface = brw_imm_ud(surf_index);
4480 brw_mark_surface_used(prog_data, surf_index);
4481 } else {
4482 surface = vgrf(glsl_type::uint_type);
4483 bld.ADD(surface, get_nir_src(instr->src[0]),
4484 brw_imm_ud(stage_prog_data->binding_table.ssbo_start));
4485
4486 /* Assume this may touch any SSBO. This is the same we do for other
4487 * UBO/SSBO accesses with non-constant surface.
4488 */
4489 brw_mark_surface_used(prog_data,
4490 stage_prog_data->binding_table.ssbo_start +
4491 nir->info.num_ssbos - 1);
4492 }
4493
4494 fs_reg offset = get_nir_src(instr->src[1]);
4495 fs_reg data1 = get_nir_src(instr->src[2]);
4496 fs_reg data2;
4497 if (op == BRW_AOP_CMPWR)
4498 data2 = get_nir_src(instr->src[3]);
4499
4500 /* Emit the actual atomic operation */
4501
4502 fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
4503 data1, data2,
4504 1 /* dims */, 1 /* rsize */,
4505 op,
4506 BRW_PREDICATE_NONE);
4507 dest.type = atomic_result.type;
4508 bld.MOV(dest, atomic_result);
4509 }
4510
4511 void
nir_emit_shared_atomic(const fs_builder & bld,int op,nir_intrinsic_instr * instr)4512 fs_visitor::nir_emit_shared_atomic(const fs_builder &bld,
4513 int op, nir_intrinsic_instr *instr)
4514 {
4515 fs_reg dest;
4516 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
4517 dest = get_nir_dest(instr->dest);
4518
4519 fs_reg surface = brw_imm_ud(GEN7_BTI_SLM);
4520 fs_reg offset;
4521 fs_reg data1 = get_nir_src(instr->src[1]);
4522 fs_reg data2;
4523 if (op == BRW_AOP_CMPWR)
4524 data2 = get_nir_src(instr->src[2]);
4525
4526 /* Get the offset */
4527 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
4528 if (const_offset) {
4529 offset = brw_imm_ud(instr->const_index[0] + const_offset->u32[0]);
4530 } else {
4531 offset = vgrf(glsl_type::uint_type);
4532 bld.ADD(offset,
4533 retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
4534 brw_imm_ud(instr->const_index[0]));
4535 }
4536
4537 /* Emit the actual atomic operation operation */
4538
4539 fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
4540 data1, data2,
4541 1 /* dims */, 1 /* rsize */,
4542 op,
4543 BRW_PREDICATE_NONE);
4544 dest.type = atomic_result.type;
4545 bld.MOV(dest, atomic_result);
4546 }
4547
4548 void
nir_emit_texture(const fs_builder & bld,nir_tex_instr * instr)4549 fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
4550 {
4551 unsigned texture = instr->texture_index;
4552 unsigned sampler = instr->sampler_index;
4553
4554 fs_reg srcs[TEX_LOGICAL_NUM_SRCS];
4555
4556 srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(texture);
4557 srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(sampler);
4558
4559 int lod_components = 0;
4560
4561 /* The hardware requires a LOD for buffer textures */
4562 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4563 srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_d(0);
4564
4565 uint32_t header_bits = 0;
4566 for (unsigned i = 0; i < instr->num_srcs; i++) {
4567 fs_reg src = get_nir_src(instr->src[i].src);
4568 switch (instr->src[i].src_type) {
4569 case nir_tex_src_bias:
4570 srcs[TEX_LOGICAL_SRC_LOD] =
4571 retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_F);
4572 break;
4573 case nir_tex_src_comparator:
4574 srcs[TEX_LOGICAL_SRC_SHADOW_C] = retype(src, BRW_REGISTER_TYPE_F);
4575 break;
4576 case nir_tex_src_coord:
4577 switch (instr->op) {
4578 case nir_texop_txf:
4579 case nir_texop_txf_ms:
4580 case nir_texop_txf_ms_mcs:
4581 case nir_texop_samples_identical:
4582 srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, BRW_REGISTER_TYPE_D);
4583 break;
4584 default:
4585 srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, BRW_REGISTER_TYPE_F);
4586 break;
4587 }
4588 break;
4589 case nir_tex_src_ddx:
4590 srcs[TEX_LOGICAL_SRC_LOD] = retype(src, BRW_REGISTER_TYPE_F);
4591 lod_components = nir_tex_instr_src_size(instr, i);
4592 break;
4593 case nir_tex_src_ddy:
4594 srcs[TEX_LOGICAL_SRC_LOD2] = retype(src, BRW_REGISTER_TYPE_F);
4595 break;
4596 case nir_tex_src_lod:
4597 switch (instr->op) {
4598 case nir_texop_txs:
4599 srcs[TEX_LOGICAL_SRC_LOD] =
4600 retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_UD);
4601 break;
4602 case nir_texop_txf:
4603 srcs[TEX_LOGICAL_SRC_LOD] =
4604 retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_D);
4605 break;
4606 default:
4607 srcs[TEX_LOGICAL_SRC_LOD] =
4608 retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_F);
4609 break;
4610 }
4611 break;
4612 case nir_tex_src_ms_index:
4613 srcs[TEX_LOGICAL_SRC_SAMPLE_INDEX] = retype(src, BRW_REGISTER_TYPE_UD);
4614 break;
4615
4616 case nir_tex_src_offset: {
4617 nir_const_value *const_offset =
4618 nir_src_as_const_value(instr->src[i].src);
4619 unsigned offset_bits = 0;
4620 if (const_offset &&
4621 brw_texture_offset(const_offset->i32,
4622 nir_tex_instr_src_size(instr, i),
4623 &offset_bits)) {
4624 header_bits |= offset_bits;
4625 } else {
4626 srcs[TEX_LOGICAL_SRC_TG4_OFFSET] =
4627 retype(src, BRW_REGISTER_TYPE_D);
4628 }
4629 break;
4630 }
4631
4632 case nir_tex_src_projector:
4633 unreachable("should be lowered");
4634
4635 case nir_tex_src_texture_offset: {
4636 /* Figure out the highest possible texture index and mark it as used */
4637 uint32_t max_used = texture + instr->texture_array_size - 1;
4638 if (instr->op == nir_texop_tg4 && devinfo->gen < 8) {
4639 max_used += stage_prog_data->binding_table.gather_texture_start;
4640 } else {
4641 max_used += stage_prog_data->binding_table.texture_start;
4642 }
4643 brw_mark_surface_used(prog_data, max_used);
4644
4645 /* Emit code to evaluate the actual indexing expression */
4646 fs_reg tmp = vgrf(glsl_type::uint_type);
4647 bld.ADD(tmp, src, brw_imm_ud(texture));
4648 srcs[TEX_LOGICAL_SRC_SURFACE] = bld.emit_uniformize(tmp);
4649 break;
4650 }
4651
4652 case nir_tex_src_sampler_offset: {
4653 /* Emit code to evaluate the actual indexing expression */
4654 fs_reg tmp = vgrf(glsl_type::uint_type);
4655 bld.ADD(tmp, src, brw_imm_ud(sampler));
4656 srcs[TEX_LOGICAL_SRC_SAMPLER] = bld.emit_uniformize(tmp);
4657 break;
4658 }
4659
4660 case nir_tex_src_ms_mcs:
4661 assert(instr->op == nir_texop_txf_ms);
4662 srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D);
4663 break;
4664
4665 case nir_tex_src_plane: {
4666 nir_const_value *const_plane =
4667 nir_src_as_const_value(instr->src[i].src);
4668 const uint32_t plane = const_plane->u32[0];
4669 const uint32_t texture_index =
4670 instr->texture_index +
4671 stage_prog_data->binding_table.plane_start[plane] -
4672 stage_prog_data->binding_table.texture_start;
4673
4674 srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(texture_index);
4675 break;
4676 }
4677
4678 default:
4679 unreachable("unknown texture source");
4680 }
4681 }
4682
4683 if (srcs[TEX_LOGICAL_SRC_MCS].file == BAD_FILE &&
4684 (instr->op == nir_texop_txf_ms ||
4685 instr->op == nir_texop_samples_identical)) {
4686 if (devinfo->gen >= 7 &&
4687 key_tex->compressed_multisample_layout_mask & (1 << texture)) {
4688 srcs[TEX_LOGICAL_SRC_MCS] =
4689 emit_mcs_fetch(srcs[TEX_LOGICAL_SRC_COORDINATE],
4690 instr->coord_components,
4691 srcs[TEX_LOGICAL_SRC_SURFACE]);
4692 } else {
4693 srcs[TEX_LOGICAL_SRC_MCS] = brw_imm_ud(0u);
4694 }
4695 }
4696
4697 srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(instr->coord_components);
4698 srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(lod_components);
4699
4700 enum opcode opcode;
4701 switch (instr->op) {
4702 case nir_texop_tex:
4703 opcode = (stage == MESA_SHADER_FRAGMENT ? SHADER_OPCODE_TEX_LOGICAL :
4704 SHADER_OPCODE_TXL_LOGICAL);
4705 break;
4706 case nir_texop_txb:
4707 opcode = FS_OPCODE_TXB_LOGICAL;
4708 break;
4709 case nir_texop_txl:
4710 opcode = SHADER_OPCODE_TXL_LOGICAL;
4711 break;
4712 case nir_texop_txd:
4713 opcode = SHADER_OPCODE_TXD_LOGICAL;
4714 break;
4715 case nir_texop_txf:
4716 opcode = SHADER_OPCODE_TXF_LOGICAL;
4717 break;
4718 case nir_texop_txf_ms:
4719 if ((key_tex->msaa_16 & (1 << sampler)))
4720 opcode = SHADER_OPCODE_TXF_CMS_W_LOGICAL;
4721 else
4722 opcode = SHADER_OPCODE_TXF_CMS_LOGICAL;
4723 break;
4724 case nir_texop_txf_ms_mcs:
4725 opcode = SHADER_OPCODE_TXF_MCS_LOGICAL;
4726 break;
4727 case nir_texop_query_levels:
4728 case nir_texop_txs:
4729 opcode = SHADER_OPCODE_TXS_LOGICAL;
4730 break;
4731 case nir_texop_lod:
4732 opcode = SHADER_OPCODE_LOD_LOGICAL;
4733 break;
4734 case nir_texop_tg4:
4735 if (srcs[TEX_LOGICAL_SRC_TG4_OFFSET].file != BAD_FILE)
4736 opcode = SHADER_OPCODE_TG4_OFFSET_LOGICAL;
4737 else
4738 opcode = SHADER_OPCODE_TG4_LOGICAL;
4739 break;
4740 case nir_texop_texture_samples:
4741 opcode = SHADER_OPCODE_SAMPLEINFO_LOGICAL;
4742 break;
4743 case nir_texop_samples_identical: {
4744 fs_reg dst = retype(get_nir_dest(instr->dest), BRW_REGISTER_TYPE_D);
4745
4746 /* If mcs is an immediate value, it means there is no MCS. In that case
4747 * just return false.
4748 */
4749 if (srcs[TEX_LOGICAL_SRC_MCS].file == BRW_IMMEDIATE_VALUE) {
4750 bld.MOV(dst, brw_imm_ud(0u));
4751 } else if ((key_tex->msaa_16 & (1 << sampler))) {
4752 fs_reg tmp = vgrf(glsl_type::uint_type);
4753 bld.OR(tmp, srcs[TEX_LOGICAL_SRC_MCS],
4754 offset(srcs[TEX_LOGICAL_SRC_MCS], bld, 1));
4755 bld.CMP(dst, tmp, brw_imm_ud(0u), BRW_CONDITIONAL_EQ);
4756 } else {
4757 bld.CMP(dst, srcs[TEX_LOGICAL_SRC_MCS], brw_imm_ud(0u),
4758 BRW_CONDITIONAL_EQ);
4759 }
4760 return;
4761 }
4762 default:
4763 unreachable("unknown texture opcode");
4764 }
4765
4766 if (instr->op == nir_texop_tg4) {
4767 if (instr->component == 1 &&
4768 key_tex->gather_channel_quirk_mask & (1 << texture)) {
4769 /* gather4 sampler is broken for green channel on RG32F --
4770 * we must ask for blue instead.
4771 */
4772 header_bits |= 2 << 16;
4773 } else {
4774 header_bits |= instr->component << 16;
4775 }
4776 }
4777
4778 fs_reg dst = bld.vgrf(brw_type_for_nir_type(devinfo, instr->dest_type), 4);
4779 fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs));
4780 inst->offset = header_bits;
4781
4782 const unsigned dest_size = nir_tex_instr_dest_size(instr);
4783 if (devinfo->gen >= 9 &&
4784 instr->op != nir_texop_tg4 && instr->op != nir_texop_query_levels) {
4785 unsigned write_mask = instr->dest.is_ssa ?
4786 nir_ssa_def_components_read(&instr->dest.ssa):
4787 (1 << dest_size) - 1;
4788 assert(write_mask != 0); /* dead code should have been eliminated */
4789 inst->size_written = util_last_bit(write_mask) *
4790 inst->dst.component_size(inst->exec_size);
4791 } else {
4792 inst->size_written = 4 * inst->dst.component_size(inst->exec_size);
4793 }
4794
4795 if (srcs[TEX_LOGICAL_SRC_SHADOW_C].file != BAD_FILE)
4796 inst->shadow_compare = true;
4797
4798 if (instr->op == nir_texop_tg4 && devinfo->gen == 6)
4799 emit_gen6_gather_wa(key_tex->gen6_gather_wa[texture], dst);
4800
4801 fs_reg nir_dest[4];
4802 for (unsigned i = 0; i < dest_size; i++)
4803 nir_dest[i] = offset(dst, bld, i);
4804
4805 if (instr->op == nir_texop_query_levels) {
4806 /* # levels is in .w */
4807 nir_dest[0] = offset(dst, bld, 3);
4808 } else if (instr->op == nir_texop_txs &&
4809 dest_size >= 3 && devinfo->gen < 7) {
4810 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4811 fs_reg depth = offset(dst, bld, 2);
4812 nir_dest[2] = vgrf(glsl_type::int_type);
4813 bld.emit_minmax(nir_dest[2], depth, brw_imm_d(1), BRW_CONDITIONAL_GE);
4814 }
4815
4816 bld.LOAD_PAYLOAD(get_nir_dest(instr->dest), nir_dest, dest_size, 0);
4817 }
4818
4819 void
nir_emit_jump(const fs_builder & bld,nir_jump_instr * instr)4820 fs_visitor::nir_emit_jump(const fs_builder &bld, nir_jump_instr *instr)
4821 {
4822 switch (instr->type) {
4823 case nir_jump_break:
4824 bld.emit(BRW_OPCODE_BREAK);
4825 break;
4826 case nir_jump_continue:
4827 bld.emit(BRW_OPCODE_CONTINUE);
4828 break;
4829 case nir_jump_return:
4830 default:
4831 unreachable("unknown jump");
4832 }
4833 }
4834
4835 /**
4836 * This helper takes the result of a load operation that reads 32-bit elements
4837 * in this format:
4838 *
4839 * x x x x x x x x
4840 * y y y y y y y y
4841 * z z z z z z z z
4842 * w w w w w w w w
4843 *
4844 * and shuffles the data to get this:
4845 *
4846 * x y x y x y x y
4847 * x y x y x y x y
4848 * z w z w z w z w
4849 * z w z w z w z w
4850 *
4851 * Which is exactly what we want if the load is reading 64-bit components
4852 * like doubles, where x represents the low 32-bit of the x double component
4853 * and y represents the high 32-bit of the x double component (likewise with
4854 * z and w for double component y). The parameter @components represents
4855 * the number of 64-bit components present in @src. This would typically be
4856 * 2 at most, since we can only fit 2 double elements in the result of a
4857 * vec4 load.
4858 *
4859 * Notice that @dst and @src can be the same register.
4860 */
4861 void
shuffle_32bit_load_result_to_64bit_data(const fs_builder & bld,const fs_reg & dst,const fs_reg & src,uint32_t components)4862 shuffle_32bit_load_result_to_64bit_data(const fs_builder &bld,
4863 const fs_reg &dst,
4864 const fs_reg &src,
4865 uint32_t components)
4866 {
4867 assert(type_sz(src.type) == 4);
4868 assert(type_sz(dst.type) == 8);
4869
4870 /* A temporary that we will use to shuffle the 32-bit data of each
4871 * component in the vector into valid 64-bit data. We can't write directly
4872 * to dst because dst can be (and would usually be) the same as src
4873 * and in that case the first MOV in the loop below would overwrite the
4874 * data read in the second MOV.
4875 */
4876 fs_reg tmp = bld.vgrf(dst.type);
4877
4878 for (unsigned i = 0; i < components; i++) {
4879 const fs_reg component_i = offset(src, bld, 2 * i);
4880
4881 bld.MOV(subscript(tmp, src.type, 0), component_i);
4882 bld.MOV(subscript(tmp, src.type, 1), offset(component_i, bld, 1));
4883
4884 bld.MOV(offset(dst, bld, i), tmp);
4885 }
4886 }
4887
4888 void
shuffle_32bit_load_result_to_16bit_data(const fs_builder & bld,const fs_reg & dst,const fs_reg & src,uint32_t components)4889 shuffle_32bit_load_result_to_16bit_data(const fs_builder &bld,
4890 const fs_reg &dst,
4891 const fs_reg &src,
4892 uint32_t components)
4893 {
4894 assert(type_sz(src.type) == 4);
4895 assert(type_sz(dst.type) == 2);
4896
4897 /* A temporary is used to un-shuffle the 32-bit data of each component in
4898 * into a valid 16-bit vector. We can't write directly to dst because it
4899 * can be the same register as src and in that case the first MOV in the
4900 * loop below would overwrite the data read in the second MOV.
4901 */
4902 fs_reg tmp = retype(bld.vgrf(src.type), dst.type);
4903
4904 for (unsigned i = 0; i < components; i++) {
4905 const fs_reg component_i =
4906 subscript(offset(src, bld, i / 2), dst.type, i % 2);
4907
4908 bld.MOV(offset(tmp, bld, i % 2), component_i);
4909
4910 if (i % 2) {
4911 bld.MOV(offset(dst, bld, i -1), offset(tmp, bld, 0));
4912 bld.MOV(offset(dst, bld, i), offset(tmp, bld, 1));
4913 }
4914 }
4915 if (components % 2) {
4916 bld.MOV(offset(dst, bld, components - 1), tmp);
4917 }
4918 }
4919
4920 /**
4921 * This helper does the inverse operation of
4922 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4923 *
4924 * We need to do this when we are going to use untyped write messsages that
4925 * operate with 32-bit components in order to arrange our 64-bit data to be
4926 * in the expected layout.
4927 *
4928 * Notice that callers of this function, unlike in the case of the inverse
4929 * operation, would typically need to call this with dst and src being
4930 * different registers, since they would otherwise corrupt the original
4931 * 64-bit data they are about to write. Because of this the function checks
4932 * that the src and dst regions involved in the operation do not overlap.
4933 */
4934 fs_reg
shuffle_64bit_data_for_32bit_write(const fs_builder & bld,const fs_reg & src,uint32_t components)4935 shuffle_64bit_data_for_32bit_write(const fs_builder &bld,
4936 const fs_reg &src,
4937 uint32_t components)
4938 {
4939 assert(type_sz(src.type) == 8);
4940
4941 fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_D, 2 * components);
4942
4943 for (unsigned i = 0; i < components; i++) {
4944 const fs_reg component_i = offset(src, bld, i);
4945 bld.MOV(offset(dst, bld, 2 * i), subscript(component_i, dst.type, 0));
4946 bld.MOV(offset(dst, bld, 2 * i + 1), subscript(component_i, dst.type, 1));
4947 }
4948
4949 return dst;
4950 }
4951
4952 void
shuffle_16bit_data_for_32bit_write(const fs_builder & bld,const fs_reg & dst,const fs_reg & src,uint32_t components)4953 shuffle_16bit_data_for_32bit_write(const fs_builder &bld,
4954 const fs_reg &dst,
4955 const fs_reg &src,
4956 uint32_t components)
4957 {
4958 assert(type_sz(src.type) == 2);
4959 assert(type_sz(dst.type) == 4);
4960
4961 /* A temporary is used to shuffle the 16-bit data of each component in the
4962 * 32-bit data vector. We can't write directly to dst because it can be the
4963 * same register as src and in that case the first MOV in the loop below
4964 * would overwrite the data read in the second MOV.
4965 */
4966 fs_reg tmp = bld.vgrf(dst.type);
4967
4968 for (unsigned i = 0; i < components; i++) {
4969 const fs_reg component_i = offset(src, bld, i);
4970 bld.MOV(subscript(tmp, src.type, i % 2), component_i);
4971 if (i % 2) {
4972 bld.MOV(offset(dst, bld, i / 2), tmp);
4973 }
4974 }
4975 if (components % 2) {
4976 bld.MOV(offset(dst, bld, components / 2), tmp);
4977 }
4978 }
4979
4980 fs_reg
setup_imm_df(const fs_builder & bld,double v)4981 setup_imm_df(const fs_builder &bld, double v)
4982 {
4983 const struct gen_device_info *devinfo = bld.shader->devinfo;
4984 assert(devinfo->gen >= 7);
4985
4986 if (devinfo->gen >= 8)
4987 return brw_imm_df(v);
4988
4989 /* gen7.5 does not support DF immediates straighforward but the DIM
4990 * instruction allows to set the 64-bit immediate value.
4991 */
4992 if (devinfo->is_haswell) {
4993 const fs_builder ubld = bld.exec_all().group(1, 0);
4994 fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_DF, 1);
4995 ubld.DIM(dst, brw_imm_df(v));
4996 return component(dst, 0);
4997 }
4998
4999 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5000 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5001 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5002 *
5003 * Alternatively, we could also produce a normal VGRF (without stride 0)
5004 * by writing to all the channels in the VGRF, however, that would hit the
5005 * gen7 bug where we have to split writes that span more than 1 register
5006 * into instructions with a width of 4 (otherwise the write to the second
5007 * register written runs into an execmask hardware bug) which isn't very
5008 * nice.
5009 */
5010 union {
5011 double d;
5012 struct {
5013 uint32_t i1;
5014 uint32_t i2;
5015 };
5016 } di;
5017
5018 di.d = v;
5019
5020 const fs_builder ubld = bld.exec_all().group(1, 0);
5021 const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);
5022 ubld.MOV(tmp, brw_imm_ud(di.i1));
5023 ubld.MOV(horiz_offset(tmp, 1), brw_imm_ud(di.i2));
5024
5025 return component(retype(tmp, BRW_REGISTER_TYPE_DF), 0);
5026 }
5027