1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <fdt_support.h>
9 #include <asm/io.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #ifdef CONFIG_FSL_LS_PPA
13 #include <asm/arch/ppa.h>
14 #endif
15 #include <asm/arch/fdt.h>
16 #include <asm/arch/mmu.h>
17 #include <asm/arch/soc.h>
18 #include <ahci.h>
19 #include <hwconfig.h>
20 #include <mmc.h>
21 #include <scsi.h>
22 #include <fm_eth.h>
23 #include <fsl_esdhc.h>
24 #include <fsl_mmdc.h>
25 #include <spl.h>
26 #include <netdev.h>
27 #include "../common/qixis.h"
28 #include "ls1012aqds_qixis.h"
29 #include "ls1012aqds_pfe.h"
30
31 DECLARE_GLOBAL_DATA_PTR;
32
checkboard(void)33 int checkboard(void)
34 {
35 char buf[64];
36 u8 sw;
37
38 sw = QIXIS_READ(arch);
39 printf("Board Arch: V%d, ", sw >> 4);
40 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
41
42 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
43
44 if (sw & QIXIS_LBMAP_ALTBANK)
45 printf("flash: 2\n");
46 else
47 printf("flash: 1\n");
48
49 printf("FPGA: v%d (%s), build %d",
50 (int)QIXIS_READ(scver), qixis_read_tag(buf),
51 (int)qixis_read_minor());
52
53 /* the timestamp string contains "\n" at the end */
54 printf(" on %s", qixis_read_time(buf));
55 return 0;
56 }
57
dram_init(void)58 int dram_init(void)
59 {
60 static const struct fsl_mmdc_info mparam = {
61 0x05180000, /* mdctl */
62 0x00030035, /* mdpdc */
63 0x12554000, /* mdotc */
64 0xbabf7954, /* mdcfg0 */
65 0xdb328f64, /* mdcfg1 */
66 0x01ff00db, /* mdcfg2 */
67 0x00001680, /* mdmisc */
68 0x0f3c8000, /* mdref */
69 0x00002000, /* mdrwd */
70 0x00bf1023, /* mdor */
71 0x0000003f, /* mdasp */
72 0x0000022a, /* mpodtctrl */
73 0xa1390003, /* mpzqhwctrl */
74 };
75
76 mmdc_init(&mparam);
77
78 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
79 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
80 /* This will break-before-make MMU for DDR */
81 update_early_mmu_table();
82 #endif
83
84 return 0;
85 }
86
board_early_init_f(void)87 int board_early_init_f(void)
88 {
89 fsl_lsch2_early_init_f();
90
91 return 0;
92 }
93
94 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)95 int misc_init_r(void)
96 {
97 u8 mux_sdhc_cd = 0x80;
98
99 i2c_set_bus_num(0);
100
101 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
102 return 0;
103 }
104 #endif
105
board_init(void)106 int board_init(void)
107 {
108 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
109 CONFIG_SYS_CCI400_OFFSET);
110
111 /* Set CCI-400 control override register to enable barrier
112 * transaction */
113 out_le32(&cci->ctrl_ord,
114 CCI400_CTRLORD_EN_BARRIER);
115
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
117 erratum_a010315();
118 #endif
119
120 #ifdef CONFIG_ENV_IS_NOWHERE
121 gd->env_addr = (ulong)&default_environment[0];
122 #endif
123
124 #ifdef CONFIG_FSL_LS_PPA
125 ppa_init();
126 #endif
127 return 0;
128 }
129
esdhc_status_fixup(void * blob,const char * compat)130 int esdhc_status_fixup(void *blob, const char *compat)
131 {
132 char esdhc0_path[] = "/soc/esdhc@1560000";
133 char esdhc1_path[] = "/soc/esdhc@1580000";
134 u8 card_id;
135
136 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
137 sizeof("okay"), 1);
138
139 /*
140 * The Presence Detect 2 register detects the installation
141 * of cards in various PCI Express or SGMII slots.
142 *
143 * STAT_PRS2[7:5]: Specifies the type of card installed in the
144 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
145 */
146 card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
147
148 /* If no adapter is installed in SDHC2, disable SDHC2 */
149 if (card_id == 0x7)
150 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
151 sizeof("disabled"), 1);
152 else
153 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
154 sizeof("okay"), 1);
155 return 0;
156 }
157
pfe_set_properties(void * set_blob,struct pfe_prop_val prop_val,char * enet_path,char * mdio_path)158 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
159 char *enet_path, char *mdio_path)
160 {
161 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
162 &prop_val.busid, PFE_PROP_LEN, 1);
163 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
164 &prop_val.phyid, PFE_PROP_LEN, 1);
165 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
166 &prop_val.mux_val, PFE_PROP_LEN, 1);
167 do_fixup_by_path(set_blob, enet_path, "phy-mode",
168 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
169 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
170 &prop_val.phy_mask, PFE_PROP_LEN, 1);
171 return 0;
172 }
173
fdt_fsl_fixup_of_pfe(void * blob)174 static void fdt_fsl_fixup_of_pfe(void *blob)
175 {
176 int i = 0;
177 struct pfe_prop_val prop_val;
178 void *l_blob = blob;
179
180 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
181 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
182 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
183 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
184
185 for (i = 0; i < NUM_ETH_NODE; i++) {
186 switch (srds_s1) {
187 case SERDES_1_G_PROTOCOL:
188 if (i == 0) {
189 prop_val.busid = cpu_to_fdt32(
190 ETH_1_1G_BUS_ID);
191 prop_val.phyid = cpu_to_fdt32(
192 ETH_1_1G_PHY_ID);
193 prop_val.mux_val = cpu_to_fdt32(
194 ETH_1_1G_MDIO_MUX);
195 prop_val.phy_mask = cpu_to_fdt32(
196 ETH_1G_MDIO_PHY_MASK);
197 prop_val.phy_mode = "sgmii";
198 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
199 ETH_1_MDIO);
200 } else {
201 prop_val.busid = cpu_to_fdt32(
202 ETH_2_1G_BUS_ID);
203 prop_val.phyid = cpu_to_fdt32(
204 ETH_2_1G_PHY_ID);
205 prop_val.mux_val = cpu_to_fdt32(
206 ETH_2_1G_MDIO_MUX);
207 prop_val.phy_mask = cpu_to_fdt32(
208 ETH_1G_MDIO_PHY_MASK);
209 prop_val.phy_mode = "rgmii";
210 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
211 ETH_2_MDIO);
212 }
213 break;
214 case SERDES_2_5_G_PROTOCOL:
215 if (i == 0) {
216 prop_val.busid = cpu_to_fdt32(
217 ETH_1_2_5G_BUS_ID);
218 prop_val.phyid = cpu_to_fdt32(
219 ETH_1_2_5G_PHY_ID);
220 prop_val.mux_val = cpu_to_fdt32(
221 ETH_1_2_5G_MDIO_MUX);
222 prop_val.phy_mask = cpu_to_fdt32(
223 ETH_2_5G_MDIO_PHY_MASK);
224 prop_val.phy_mode = "sgmii-2500";
225 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
226 ETH_1_MDIO);
227 } else {
228 prop_val.busid = cpu_to_fdt32(
229 ETH_2_2_5G_BUS_ID);
230 prop_val.phyid = cpu_to_fdt32(
231 ETH_2_2_5G_PHY_ID);
232 prop_val.mux_val = cpu_to_fdt32(
233 ETH_2_2_5G_MDIO_MUX);
234 prop_val.phy_mask = cpu_to_fdt32(
235 ETH_2_5G_MDIO_PHY_MASK);
236 prop_val.phy_mode = "sgmii-2500";
237 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
238 ETH_2_MDIO);
239 }
240 break;
241 default:
242 printf("serdes:[%d]\n", srds_s1);
243 }
244 }
245 }
246
247 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)248 int ft_board_setup(void *blob, bd_t *bd)
249 {
250 arch_fixup_fdt(blob);
251
252 ft_cpu_setup(blob, bd);
253 fdt_fsl_fixup_of_pfe(blob);
254
255 return 0;
256 }
257 #endif
258