1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <bootm.h>
10 #include <common.h>
11 #include <netdev.h>
12 #include <linux/errno.h>
13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h>
21 #include <thermal.h>
22 #include <sata.h>
23
24 #ifdef CONFIG_FSL_ESDHC
25 #include <fsl_esdhc.h>
26 #endif
27
28 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
29 static u32 reset_cause = -1;
30
get_reset_cause(void)31 static char *get_reset_cause(void)
32 {
33 u32 cause;
34 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
35
36 cause = readl(&src_regs->srsr);
37 writel(cause, &src_regs->srsr);
38 reset_cause = cause;
39
40 switch (cause) {
41 case 0x00001:
42 case 0x00011:
43 return "POR";
44 case 0x00004:
45 return "CSU";
46 case 0x00008:
47 return "IPP USER";
48 case 0x00010:
49 #ifdef CONFIG_MX7
50 return "WDOG1";
51 #else
52 return "WDOG";
53 #endif
54 case 0x00020:
55 return "JTAG HIGH-Z";
56 case 0x00040:
57 return "JTAG SW";
58 case 0x00080:
59 return "WDOG3";
60 #ifdef CONFIG_MX7
61 case 0x00100:
62 return "WDOG4";
63 case 0x00200:
64 return "TEMPSENSE";
65 #elif defined(CONFIG_MX8M)
66 case 0x00100:
67 return "WDOG2";
68 case 0x00200:
69 return "TEMPSENSE";
70 #else
71 case 0x00100:
72 return "TEMPSENSE";
73 case 0x10000:
74 return "WARM BOOT";
75 #endif
76 default:
77 return "unknown reset";
78 }
79 }
80
get_imx_reset_cause(void)81 u32 get_imx_reset_cause(void)
82 {
83 return reset_cause;
84 }
85 #endif
86
87 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
88 #if defined(CONFIG_MX53)
89 #define MEMCTL_BASE ESDCTL_BASE_ADDR
90 #else
91 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
92 #endif
93 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
94 static const unsigned char bank_lookup[] = {3, 2};
95
96 /* these MMDC registers are common to the IMX53 and IMX6 */
97 struct esd_mmdc_regs {
98 uint32_t ctl;
99 uint32_t pdc;
100 uint32_t otc;
101 uint32_t cfg0;
102 uint32_t cfg1;
103 uint32_t cfg2;
104 uint32_t misc;
105 };
106
107 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
108 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
109 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
110 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
111 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
112
113 /*
114 * imx_ddr_size - return size in bytes of DRAM according MMDC config
115 * The MMDC MDCTL register holds the number of bits for row, col, and data
116 * width and the MMDC MDMISC register holds the number of banks. Combine
117 * all these bits to determine the meme size the MMDC has been configured for
118 */
imx_ddr_size(void)119 unsigned imx_ddr_size(void)
120 {
121 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
122 unsigned ctl = readl(&mem->ctl);
123 unsigned misc = readl(&mem->misc);
124 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
125
126 bits += ESD_MMDC_CTL_GET_ROW(ctl);
127 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
128 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
129 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
130 bits += ESD_MMDC_CTL_GET_CS1(ctl);
131
132 /* The MX6 can do only 3840 MiB of DRAM */
133 if (bits == 32)
134 return 0xf0000000;
135
136 return 1 << bits;
137 }
138 #endif
139
140 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
141
get_imx_type(u32 imxtype)142 const char *get_imx_type(u32 imxtype)
143 {
144 switch (imxtype) {
145 case MXC_CPU_MX8MQ:
146 return "8MQ"; /* Quad-core version of the mx8m */
147 case MXC_CPU_MX7S:
148 return "7S"; /* Single-core version of the mx7 */
149 case MXC_CPU_MX7D:
150 return "7D"; /* Dual-core version of the mx7 */
151 case MXC_CPU_MX6QP:
152 return "6QP"; /* Quad-Plus version of the mx6 */
153 case MXC_CPU_MX6DP:
154 return "6DP"; /* Dual-Plus version of the mx6 */
155 case MXC_CPU_MX6Q:
156 return "6Q"; /* Quad-core version of the mx6 */
157 case MXC_CPU_MX6D:
158 return "6D"; /* Dual-core version of the mx6 */
159 case MXC_CPU_MX6DL:
160 return "6DL"; /* Dual Lite version of the mx6 */
161 case MXC_CPU_MX6SOLO:
162 return "6SOLO"; /* Solo version of the mx6 */
163 case MXC_CPU_MX6SL:
164 return "6SL"; /* Solo-Lite version of the mx6 */
165 case MXC_CPU_MX6SLL:
166 return "6SLL"; /* SLL version of the mx6 */
167 case MXC_CPU_MX6SX:
168 return "6SX"; /* SoloX version of the mx6 */
169 case MXC_CPU_MX6UL:
170 return "6UL"; /* Ultra-Lite version of the mx6 */
171 case MXC_CPU_MX6ULL:
172 return "6ULL"; /* ULL version of the mx6 */
173 case MXC_CPU_MX51:
174 return "51";
175 case MXC_CPU_MX53:
176 return "53";
177 default:
178 return "??";
179 }
180 }
181
print_cpuinfo(void)182 int print_cpuinfo(void)
183 {
184 u32 cpurev;
185 __maybe_unused u32 max_freq;
186
187 cpurev = get_cpu_rev();
188
189 #if defined(CONFIG_IMX_THERMAL)
190 struct udevice *thermal_dev;
191 int cpu_tmp, minc, maxc, ret;
192
193 printf("CPU: Freescale i.MX%s rev%d.%d",
194 get_imx_type((cpurev & 0xFF000) >> 12),
195 (cpurev & 0x000F0) >> 4,
196 (cpurev & 0x0000F) >> 0);
197 max_freq = get_cpu_speed_grade_hz();
198 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
199 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
200 } else {
201 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
202 mxc_get_clock(MXC_ARM_CLK) / 1000000);
203 }
204 #else
205 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
206 get_imx_type((cpurev & 0xFF000) >> 12),
207 (cpurev & 0x000F0) >> 4,
208 (cpurev & 0x0000F) >> 0,
209 mxc_get_clock(MXC_ARM_CLK) / 1000000);
210 #endif
211
212 #if defined(CONFIG_IMX_THERMAL)
213 puts("CPU: ");
214 switch (get_cpu_temp_grade(&minc, &maxc)) {
215 case TEMP_AUTOMOTIVE:
216 puts("Automotive temperature grade ");
217 break;
218 case TEMP_INDUSTRIAL:
219 puts("Industrial temperature grade ");
220 break;
221 case TEMP_EXTCOMMERCIAL:
222 puts("Extended Commercial temperature grade ");
223 break;
224 default:
225 puts("Commercial temperature grade ");
226 break;
227 }
228 printf("(%dC to %dC)", minc, maxc);
229 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
230 if (!ret) {
231 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
232
233 if (!ret)
234 printf(" at %dC\n", cpu_tmp);
235 else
236 debug(" - invalid sensor data\n");
237 } else {
238 debug(" - invalid sensor device\n");
239 }
240 #endif
241
242 printf("Reset cause: %s\n", get_reset_cause());
243 return 0;
244 }
245 #endif
246
cpu_eth_init(bd_t * bis)247 int cpu_eth_init(bd_t *bis)
248 {
249 int rc = -ENODEV;
250
251 #if defined(CONFIG_FEC_MXC)
252 rc = fecmxc_initialize(bis);
253 #endif
254
255 return rc;
256 }
257
258 #ifdef CONFIG_FSL_ESDHC
259 /*
260 * Initializes on-chip MMC controllers.
261 * to override, implement board_mmc_init()
262 */
cpu_mmc_init(bd_t * bis)263 int cpu_mmc_init(bd_t *bis)
264 {
265 return fsl_esdhc_mmc_init(bis);
266 }
267 #endif
268
269 #if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
get_ahb_clk(void)270 u32 get_ahb_clk(void)
271 {
272 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
273 u32 reg, ahb_podf;
274
275 reg = __raw_readl(&imx_ccm->cbcdr);
276 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
277 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
278
279 return get_periph_clk() / (ahb_podf + 1);
280 }
281 #endif
282
arch_preboot_os(void)283 void arch_preboot_os(void)
284 {
285 #if defined(CONFIG_PCIE_IMX)
286 imx_pcie_remove();
287 #endif
288 #if defined(CONFIG_SATA)
289 sata_remove(0);
290 #if defined(CONFIG_MX6)
291 disable_sata_clock();
292 #endif
293 #endif
294 #if defined(CONFIG_VIDEO_IPUV3)
295 /* disable video before launching O/S */
296 ipuv3_fb_shutdown();
297 #endif
298 #if defined(CONFIG_VIDEO_MXS)
299 lcdif_power_down();
300 #endif
301 }
302
303 #ifndef CONFIG_MX8M
set_chipselect_size(int const cs_size)304 void set_chipselect_size(int const cs_size)
305 {
306 unsigned int reg;
307 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
308 reg = readl(&iomuxc_regs->gpr[1]);
309
310 switch (cs_size) {
311 case CS0_128:
312 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
313 reg |= 0x5;
314 break;
315 case CS0_64M_CS1_64M:
316 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
317 reg |= 0x1B;
318 break;
319 case CS0_64M_CS1_32M_CS2_32M:
320 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
321 reg |= 0x4B;
322 break;
323 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
324 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
325 reg |= 0x249;
326 break;
327 default:
328 printf("Unknown chip select size: %d\n", cs_size);
329 break;
330 }
331
332 writel(reg, &iomuxc_regs->gpr[1]);
333 }
334 #endif
335
336 #if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
337 /*
338 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
339 * defines a 2-bit SPEED_GRADING
340 */
341 #define OCOTP_TESTER3_SPEED_SHIFT 8
342 enum cpu_speed {
343 OCOTP_TESTER3_SPEED_GRADE0,
344 OCOTP_TESTER3_SPEED_GRADE1,
345 OCOTP_TESTER3_SPEED_GRADE2,
346 OCOTP_TESTER3_SPEED_GRADE3,
347 };
348
get_cpu_speed_grade_hz(void)349 u32 get_cpu_speed_grade_hz(void)
350 {
351 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
352 struct fuse_bank *bank = &ocotp->bank[1];
353 struct fuse_bank1_regs *fuse =
354 (struct fuse_bank1_regs *)bank->fuse_regs;
355 uint32_t val;
356
357 val = readl(&fuse->tester3);
358 val >>= OCOTP_TESTER3_SPEED_SHIFT;
359 val &= 0x3;
360
361 switch(val) {
362 case OCOTP_TESTER3_SPEED_GRADE0:
363 return 800000000;
364 case OCOTP_TESTER3_SPEED_GRADE1:
365 return is_mx7() ? 500000000 : 1000000000;
366 case OCOTP_TESTER3_SPEED_GRADE2:
367 return is_mx7() ? 1000000000 : 1300000000;
368 case OCOTP_TESTER3_SPEED_GRADE3:
369 return is_mx7() ? 1200000000 : 1500000000;
370 }
371
372 return 0;
373 }
374
375 /*
376 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
377 * defines a 2-bit SPEED_GRADING
378 */
379 #define OCOTP_TESTER3_TEMP_SHIFT 6
380
get_cpu_temp_grade(int * minc,int * maxc)381 u32 get_cpu_temp_grade(int *minc, int *maxc)
382 {
383 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
384 struct fuse_bank *bank = &ocotp->bank[1];
385 struct fuse_bank1_regs *fuse =
386 (struct fuse_bank1_regs *)bank->fuse_regs;
387 uint32_t val;
388
389 val = readl(&fuse->tester3);
390 val >>= OCOTP_TESTER3_TEMP_SHIFT;
391 val &= 0x3;
392
393 if (minc && maxc) {
394 if (val == TEMP_AUTOMOTIVE) {
395 *minc = -40;
396 *maxc = 125;
397 } else if (val == TEMP_INDUSTRIAL) {
398 *minc = -40;
399 *maxc = 105;
400 } else if (val == TEMP_EXTCOMMERCIAL) {
401 *minc = -20;
402 *maxc = 105;
403 } else {
404 *minc = 0;
405 *maxc = 95;
406 }
407 }
408 return val;
409 }
410 #endif
411
412 #if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
get_boot_device(void)413 enum boot_device get_boot_device(void)
414 {
415 struct bootrom_sw_info **p =
416 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
417
418 enum boot_device boot_dev = SD1_BOOT;
419 u8 boot_type = (*p)->boot_dev_type;
420 u8 boot_instance = (*p)->boot_dev_instance;
421
422 switch (boot_type) {
423 case BOOT_TYPE_SD:
424 boot_dev = boot_instance + SD1_BOOT;
425 break;
426 case BOOT_TYPE_MMC:
427 boot_dev = boot_instance + MMC1_BOOT;
428 break;
429 case BOOT_TYPE_NAND:
430 boot_dev = NAND_BOOT;
431 break;
432 case BOOT_TYPE_QSPI:
433 boot_dev = QSPI_BOOT;
434 break;
435 case BOOT_TYPE_WEIM:
436 boot_dev = WEIM_NOR_BOOT;
437 break;
438 case BOOT_TYPE_SPINOR:
439 boot_dev = SPI_NOR_BOOT;
440 break;
441 #ifdef CONFIG_MX8M
442 case BOOT_TYPE_USB:
443 boot_dev = USB_BOOT;
444 break;
445 #endif
446 default:
447 break;
448 }
449
450 return boot_dev;
451 }
452 #endif
453
454 #ifdef CONFIG_NXP_BOARD_REVISION
nxp_board_rev(void)455 int nxp_board_rev(void)
456 {
457 /*
458 * Get Board ID information from OCOTP_GP1[15:8]
459 * RevA: 0x1
460 * RevB: 0x2
461 * RevC: 0x3
462 */
463 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
464 struct fuse_bank *bank = &ocotp->bank[4];
465 struct fuse_bank4_regs *fuse =
466 (struct fuse_bank4_regs *)bank->fuse_regs;
467
468 return (readl(&fuse->gp1) >> 8 & 0x0F);
469 }
470
nxp_board_rev_string(void)471 char nxp_board_rev_string(void)
472 {
473 const char *rev = "A";
474
475 return (*rev + nxp_board_rev() - 1);
476 }
477 #endif
478