1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "radeon/r600_cs.h"
26
27 #include "util/os_time.h"
28
si_destroy_saved_cs(struct si_saved_cs * scs)29 void si_destroy_saved_cs(struct si_saved_cs *scs)
30 {
31 si_clear_saved_cs(&scs->gfx);
32 r600_resource_reference(&scs->trace_buf, NULL);
33 free(scs);
34 }
35
36 /* initialize */
si_need_cs_space(struct si_context * ctx)37 void si_need_cs_space(struct si_context *ctx)
38 {
39 struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
40
41 /* There is no need to flush the DMA IB here, because
42 * r600_need_dma_space always flushes the GFX IB if there is
43 * a conflict, which means any unflushed DMA commands automatically
44 * precede the GFX IB (= they had no dependency on the GFX IB when
45 * they were submitted).
46 */
47
48 /* There are two memory usage counters in the winsys for all buffers
49 * that have been added (cs_add_buffer) and two counters in the pipe
50 * driver for those that haven't been added yet.
51 */
52 if (unlikely(!radeon_cs_memory_below_limit(ctx->b.screen, ctx->b.gfx.cs,
53 ctx->b.vram, ctx->b.gtt))) {
54 ctx->b.gtt = 0;
55 ctx->b.vram = 0;
56 ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
57 return;
58 }
59 ctx->b.gtt = 0;
60 ctx->b.vram = 0;
61
62 /* If the CS is sufficiently large, don't count the space needed
63 * and just flush if there is not enough space left.
64 */
65 if (!ctx->b.ws->cs_check_space(cs, 2048))
66 ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
67 }
68
si_context_gfx_flush(void * context,unsigned flags,struct pipe_fence_handle ** fence)69 void si_context_gfx_flush(void *context, unsigned flags,
70 struct pipe_fence_handle **fence)
71 {
72 struct si_context *ctx = context;
73 struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
74 struct radeon_winsys *ws = ctx->b.ws;
75
76 if (ctx->gfx_flush_in_progress)
77 return;
78
79 if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
80 return;
81
82 if (si_check_device_reset(&ctx->b))
83 return;
84
85 if (ctx->screen->debug_flags & DBG(CHECK_VM))
86 flags &= ~PIPE_FLUSH_ASYNC;
87
88 /* If the state tracker is flushing the GFX IB, r600_flush_from_st is
89 * responsible for flushing the DMA IB and merging the fences from both.
90 * This code is only needed when the driver flushes the GFX IB
91 * internally, and it never asks for a fence handle.
92 */
93 if (radeon_emitted(ctx->b.dma.cs, 0)) {
94 assert(fence == NULL); /* internal flushes only */
95 ctx->b.dma.flush(ctx, flags, NULL);
96 }
97
98 ctx->gfx_flush_in_progress = true;
99
100 if (!LIST_IS_EMPTY(&ctx->b.active_queries))
101 si_suspend_queries(&ctx->b);
102
103 ctx->streamout.suspended = false;
104 if (ctx->streamout.begin_emitted) {
105 si_emit_streamout_end(ctx);
106 ctx->streamout.suspended = true;
107 }
108
109 ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
110 SI_CONTEXT_PS_PARTIAL_FLUSH;
111
112 /* DRM 3.1.0 doesn't flush TC for VI correctly. */
113 if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
114 ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
115 SI_CONTEXT_INV_VMEM_L1;
116
117 si_emit_cache_flush(ctx);
118
119 if (ctx->current_saved_cs) {
120 si_trace_emit(ctx);
121 si_log_hw_flush(ctx);
122
123 /* Save the IB for debug contexts. */
124 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
125 ctx->current_saved_cs->flushed = true;
126 ctx->current_saved_cs->time_flush = os_time_get_nano();
127 }
128
129 /* Flush the CS. */
130 ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
131 if (fence)
132 ws->fence_reference(fence, ctx->b.last_gfx_fence);
133
134 /* This must be after cs_flush returns, since the context's API
135 * thread can concurrently read this value in si_fence_finish. */
136 ctx->b.num_gfx_cs_flushes++;
137
138 /* Check VM faults if needed. */
139 if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
140 /* Use conservative timeout 800ms, after which we won't wait any
141 * longer and assume the GPU is hung.
142 */
143 ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_gfx_fence, 800*1000*1000);
144
145 si_check_vm_faults(&ctx->b, &ctx->current_saved_cs->gfx, RING_GFX);
146 }
147
148 if (ctx->current_saved_cs)
149 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
150
151 si_begin_new_cs(ctx);
152 ctx->gfx_flush_in_progress = false;
153 }
154
si_begin_cs_debug(struct si_context * ctx)155 static void si_begin_cs_debug(struct si_context *ctx)
156 {
157 static const uint32_t zeros[1];
158 assert(!ctx->current_saved_cs);
159
160 ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
161 if (!ctx->current_saved_cs)
162 return;
163
164 pipe_reference_init(&ctx->current_saved_cs->reference, 1);
165
166 ctx->current_saved_cs->trace_buf = (struct r600_resource*)
167 pipe_buffer_create(ctx->b.b.screen, 0,
168 PIPE_USAGE_STAGING, 8);
169 if (!ctx->current_saved_cs->trace_buf) {
170 free(ctx->current_saved_cs);
171 ctx->current_saved_cs = NULL;
172 return;
173 }
174
175 pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->current_saved_cs->trace_buf->b.b,
176 0, sizeof(zeros), zeros);
177 ctx->current_saved_cs->trace_id = 0;
178
179 si_trace_emit(ctx);
180
181 radeon_add_to_buffer_list(&ctx->b, &ctx->b.gfx, ctx->current_saved_cs->trace_buf,
182 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
183 }
184
si_begin_new_cs(struct si_context * ctx)185 void si_begin_new_cs(struct si_context *ctx)
186 {
187 if (ctx->is_debug)
188 si_begin_cs_debug(ctx);
189
190 /* Flush read caches at the beginning of CS not flushed by the kernel. */
191 if (ctx->b.chip_class >= CIK)
192 ctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
193 SI_CONTEXT_INV_ICACHE;
194
195 ctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS;
196
197 /* set all valid group as dirty so they get reemited on
198 * next draw command
199 */
200 si_pm4_reset_emitted(ctx);
201
202 /* The CS initialization should be emitted before everything else. */
203 si_pm4_emit(ctx, ctx->init_config);
204 if (ctx->init_config_gs_rings)
205 si_pm4_emit(ctx, ctx->init_config_gs_rings);
206
207 if (ctx->queued.named.ls)
208 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
209 if (ctx->queued.named.hs)
210 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
211 if (ctx->queued.named.es)
212 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
213 if (ctx->queued.named.gs)
214 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
215 if (ctx->queued.named.vs)
216 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
217 if (ctx->queued.named.ps)
218 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
219 if (ctx->vertex_buffers.buffer && ctx->vertex_elements)
220 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
221
222 /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
223 bool has_clear_state = ctx->screen->has_clear_state;
224 if (has_clear_state) {
225 ctx->framebuffer.dirty_cbufs =
226 u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
227 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
228 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
229 } else {
230 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
231 ctx->framebuffer.dirty_zsbuf = true;
232 }
233 /* This should always be marked as dirty to set the framebuffer scissor
234 * at least. */
235 si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
236
237 si_mark_atom_dirty(ctx, &ctx->clip_regs);
238 /* CLEAR_STATE sets zeros. */
239 if (!has_clear_state || ctx->clip_state.any_nonzeros)
240 si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
241 ctx->msaa_sample_locs.nr_samples = 0;
242 si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
243 si_mark_atom_dirty(ctx, &ctx->msaa_config);
244 /* CLEAR_STATE sets 0xffff. */
245 if (!has_clear_state || ctx->sample_mask.sample_mask != 0xffff)
246 si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
247 si_mark_atom_dirty(ctx, &ctx->cb_render_state);
248 /* CLEAR_STATE sets zeros. */
249 if (!has_clear_state || ctx->blend_color.any_nonzeros)
250 si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
251 si_mark_atom_dirty(ctx, &ctx->db_render_state);
252 if (ctx->b.chip_class >= GFX9)
253 si_mark_atom_dirty(ctx, &ctx->dpbb_state);
254 si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
255 si_mark_atom_dirty(ctx, &ctx->spi_map);
256 si_mark_atom_dirty(ctx, &ctx->streamout.enable_atom);
257 si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
258 si_all_descriptors_begin_new_cs(ctx);
259 si_all_resident_buffers_begin_new_cs(ctx);
260
261 ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
262 ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
263 ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
264 si_mark_atom_dirty(ctx, &ctx->scissors.atom);
265 si_mark_atom_dirty(ctx, &ctx->viewports.atom);
266
267 si_mark_atom_dirty(ctx, &ctx->scratch_state);
268 if (ctx->scratch_buffer) {
269 si_context_add_resource_size(&ctx->b.b,
270 &ctx->scratch_buffer->b.b);
271 }
272
273 if (ctx->streamout.suspended) {
274 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
275 si_streamout_buffers_dirty(ctx);
276 }
277
278 if (!LIST_IS_EMPTY(&ctx->b.active_queries))
279 si_resume_queries(&ctx->b);
280
281 assert(!ctx->b.gfx.cs->prev_dw);
282 ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
283
284 /* Invalidate various draw states so that they are emitted before
285 * the first draw call. */
286 si_invalidate_draw_sh_constants(ctx);
287 ctx->last_index_size = -1;
288 ctx->last_primitive_restart_en = -1;
289 ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
290 ctx->last_gs_out_prim = -1;
291 ctx->last_prim = -1;
292 ctx->last_multi_vgt_param = -1;
293 ctx->last_rast_prim = -1;
294 ctx->last_sc_line_stipple = ~0;
295 ctx->last_vs_state = ~0;
296 ctx->last_ls = NULL;
297 ctx->last_tcs = NULL;
298 ctx->last_tes_sh_base = -1;
299 ctx->last_num_tcs_input_cp = -1;
300
301 ctx->cs_shader_state.initialized = false;
302 }
303