1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "radeon/radeon_video.h"
26 #include "radeon/radeon_vce.h"
27 #include "ac_llvm_util.h"
28 #include "vl/vl_decoder.h"
29 #include "vl/vl_video_buffer.h"
30 #include "util/u_video.h"
31 #include "compiler/nir/nir.h"
32
33 #include <sys/utsname.h>
34
si_get_vendor(struct pipe_screen * pscreen)35 static const char *si_get_vendor(struct pipe_screen *pscreen)
36 {
37 /* Don't change this. Games such as Alien Isolation are broken if this
38 * returns "Advanced Micro Devices, Inc."
39 */
40 return "X.Org";
41 }
42
si_get_device_vendor(struct pipe_screen * pscreen)43 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
44 {
45 return "AMD";
46 }
47
si_get_marketing_name(struct radeon_winsys * ws)48 static const char *si_get_marketing_name(struct radeon_winsys *ws)
49 {
50 if (!ws->get_chip_name)
51 return NULL;
52 return ws->get_chip_name(ws);
53 }
54
si_get_family_name(const struct si_screen * sscreen)55 const char *si_get_family_name(const struct si_screen *sscreen)
56 {
57 switch (sscreen->info.family) {
58 case CHIP_TAHITI: return "AMD TAHITI";
59 case CHIP_PITCAIRN: return "AMD PITCAIRN";
60 case CHIP_VERDE: return "AMD CAPE VERDE";
61 case CHIP_OLAND: return "AMD OLAND";
62 case CHIP_HAINAN: return "AMD HAINAN";
63 case CHIP_BONAIRE: return "AMD BONAIRE";
64 case CHIP_KAVERI: return "AMD KAVERI";
65 case CHIP_KABINI: return "AMD KABINI";
66 case CHIP_HAWAII: return "AMD HAWAII";
67 case CHIP_MULLINS: return "AMD MULLINS";
68 case CHIP_TONGA: return "AMD TONGA";
69 case CHIP_ICELAND: return "AMD ICELAND";
70 case CHIP_CARRIZO: return "AMD CARRIZO";
71 case CHIP_FIJI: return "AMD FIJI";
72 case CHIP_POLARIS10: return "AMD POLARIS10";
73 case CHIP_POLARIS11: return "AMD POLARIS11";
74 case CHIP_POLARIS12: return "AMD POLARIS12";
75 case CHIP_STONEY: return "AMD STONEY";
76 case CHIP_VEGA10: return "AMD VEGA10";
77 case CHIP_RAVEN: return "AMD RAVEN";
78 default: return "AMD unknown";
79 }
80 }
81
si_have_tgsi_compute(struct si_screen * sscreen)82 static bool si_have_tgsi_compute(struct si_screen *sscreen)
83 {
84 /* Old kernels disallowed some register writes for SI
85 * that are used for indirect dispatches. */
86 return (sscreen->info.chip_class >= CIK ||
87 sscreen->info.drm_major == 3 ||
88 (sscreen->info.drm_major == 2 &&
89 sscreen->info.drm_minor >= 45));
90 }
91
si_get_param(struct pipe_screen * pscreen,enum pipe_cap param)92 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
93 {
94 struct si_screen *sscreen = (struct si_screen *)pscreen;
95
96 switch (param) {
97 /* Supported features (boolean caps). */
98 case PIPE_CAP_ACCELERATED:
99 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
100 case PIPE_CAP_ANISOTROPIC_FILTER:
101 case PIPE_CAP_POINT_SPRITE:
102 case PIPE_CAP_OCCLUSION_QUERY:
103 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
104 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
105 case PIPE_CAP_TEXTURE_SWIZZLE:
106 case PIPE_CAP_DEPTH_CLIP_DISABLE:
107 case PIPE_CAP_SHADER_STENCIL_EXPORT:
108 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
109 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
110 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
111 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
112 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
113 case PIPE_CAP_SM3:
114 case PIPE_CAP_SEAMLESS_CUBE_MAP:
115 case PIPE_CAP_PRIMITIVE_RESTART:
116 case PIPE_CAP_CONDITIONAL_RENDER:
117 case PIPE_CAP_TEXTURE_BARRIER:
118 case PIPE_CAP_INDEP_BLEND_ENABLE:
119 case PIPE_CAP_INDEP_BLEND_FUNC:
120 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
121 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
122 case PIPE_CAP_START_INSTANCE:
123 case PIPE_CAP_NPOT_TEXTURES:
124 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
125 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
126 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
127 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
128 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
129 case PIPE_CAP_TGSI_INSTANCEID:
130 case PIPE_CAP_COMPUTE:
131 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
132 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
133 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
134 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
135 case PIPE_CAP_CUBE_MAP_ARRAY:
136 case PIPE_CAP_SAMPLE_SHADING:
137 case PIPE_CAP_DRAW_INDIRECT:
138 case PIPE_CAP_CLIP_HALFZ:
139 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
140 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
141 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
142 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
143 case PIPE_CAP_TGSI_TEXCOORD:
144 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
145 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
146 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
147 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
148 case PIPE_CAP_SHAREABLE_SHADERS:
149 case PIPE_CAP_DEPTH_BOUNDS_TEST:
150 case PIPE_CAP_SAMPLER_VIEW_TARGET:
151 case PIPE_CAP_TEXTURE_QUERY_LOD:
152 case PIPE_CAP_TEXTURE_GATHER_SM5:
153 case PIPE_CAP_TGSI_TXQS:
154 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
155 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
156 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
157 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
158 case PIPE_CAP_INVALIDATE_BUFFER:
159 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
160 case PIPE_CAP_QUERY_MEMORY_INFO:
161 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
162 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
163 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
164 case PIPE_CAP_GENERATE_MIPMAP:
165 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
166 case PIPE_CAP_STRING_MARKER:
167 case PIPE_CAP_CLEAR_TEXTURE:
168 case PIPE_CAP_CULL_DISTANCE:
169 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
170 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
171 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
172 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
173 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
174 case PIPE_CAP_DOUBLES:
175 case PIPE_CAP_TGSI_TEX_TXF_LZ:
176 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
177 case PIPE_CAP_BINDLESS_TEXTURE:
178 case PIPE_CAP_QUERY_TIMESTAMP:
179 case PIPE_CAP_QUERY_TIME_ELAPSED:
180 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
181 case PIPE_CAP_QUERY_SO_OVERFLOW:
182 case PIPE_CAP_MEMOBJ:
183 case PIPE_CAP_LOAD_CONSTBUF:
184 case PIPE_CAP_INT64:
185 case PIPE_CAP_INT64_DIVMOD:
186 case PIPE_CAP_TGSI_CLOCK:
187 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
188 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
189 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
190 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
191 return 1;
192
193 case PIPE_CAP_TGSI_VOTE:
194 return HAVE_LLVM >= 0x0400;
195
196 case PIPE_CAP_TGSI_BALLOT:
197 return HAVE_LLVM >= 0x0500;
198
199 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
200 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
201
202 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
203 return (sscreen->info.drm_major == 2 &&
204 sscreen->info.drm_minor >= 43) ||
205 sscreen->info.drm_major == 3;
206
207 case PIPE_CAP_TEXTURE_MULTISAMPLE:
208 /* 2D tiling on CIK is supported since DRM 2.35.0 */
209 return sscreen->info.chip_class < CIK ||
210 (sscreen->info.drm_major == 2 &&
211 sscreen->info.drm_minor >= 35) ||
212 sscreen->info.drm_major == 3;
213
214 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
215 return R600_MAP_BUFFER_ALIGNMENT;
216
217 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
218 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
219 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
220 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
221 case PIPE_CAP_MAX_VERTEX_STREAMS:
222 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
223 return 4;
224
225 case PIPE_CAP_GLSL_FEATURE_LEVEL:
226 if (si_have_tgsi_compute(sscreen))
227 return 450;
228 return 420;
229
230 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
231 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
232
233 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
234 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
235 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
236 /* SI doesn't support unaligned loads.
237 * CIK needs DRM 2.50.0 on radeon. */
238 return sscreen->info.chip_class == SI ||
239 (sscreen->info.drm_major == 2 &&
240 sscreen->info.drm_minor < 50);
241
242 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
243 /* TODO: GFX9 hangs. */
244 if (sscreen->info.chip_class >= GFX9)
245 return 0;
246 /* Disable on SI due to VM faults in CP DMA. Enable once these
247 * faults are mitigated in software.
248 */
249 if (sscreen->info.chip_class >= CIK &&
250 sscreen->info.drm_major == 3 &&
251 sscreen->info.drm_minor >= 13)
252 return RADEON_SPARSE_PAGE_SIZE;
253 return 0;
254
255 /* Unsupported features. */
256 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
257 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
258 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
259 case PIPE_CAP_USER_VERTEX_BUFFERS:
260 case PIPE_CAP_FAKE_SW_MSAA:
261 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
262 case PIPE_CAP_VERTEXID_NOBASE:
263 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
264 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
265 case PIPE_CAP_TGSI_FS_FBFETCH:
266 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
267 case PIPE_CAP_UMA:
268 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
269 case PIPE_CAP_POST_DEPTH_COVERAGE:
270 case PIPE_CAP_TILE_RASTER_ORDER:
271 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
272 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
273 return 0;
274
275 case PIPE_CAP_NATIVE_FENCE_FD:
276 return sscreen->info.has_fence_to_handle;
277
278 case PIPE_CAP_QUERY_BUFFER_OBJECT:
279 return si_have_tgsi_compute(sscreen);
280
281 case PIPE_CAP_DRAW_PARAMETERS:
282 case PIPE_CAP_MULTI_DRAW_INDIRECT:
283 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
284 return sscreen->has_draw_indirect_multi;
285
286 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
287 return 30;
288
289 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
290 return sscreen->info.chip_class <= VI ?
291 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
292
293 /* Stream output. */
294 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
295 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
296 return 32*4;
297
298 /* Geometry shader output. */
299 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
300 return 1024;
301 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
302 return 4095;
303
304 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
305 return 2048;
306
307 /* Texturing. */
308 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
309 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
310 return 15; /* 16384 */
311 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
312 /* textures support 8192, but layered rendering supports 2048 */
313 return 12;
314 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
315 /* textures support 8192, but layered rendering supports 2048 */
316 return 2048;
317
318 /* Viewports and render targets. */
319 case PIPE_CAP_MAX_VIEWPORTS:
320 return SI_MAX_VIEWPORTS;
321 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
322 case PIPE_CAP_MAX_RENDER_TARGETS:
323 return 8;
324
325 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
326 case PIPE_CAP_MIN_TEXEL_OFFSET:
327 return -32;
328
329 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
330 case PIPE_CAP_MAX_TEXEL_OFFSET:
331 return 31;
332
333 case PIPE_CAP_ENDIANNESS:
334 return PIPE_ENDIAN_LITTLE;
335
336 case PIPE_CAP_VENDOR_ID:
337 return ATI_VENDOR_ID;
338 case PIPE_CAP_DEVICE_ID:
339 return sscreen->info.pci_id;
340 case PIPE_CAP_VIDEO_MEMORY:
341 return sscreen->info.vram_size >> 20;
342 case PIPE_CAP_PCI_GROUP:
343 return sscreen->info.pci_domain;
344 case PIPE_CAP_PCI_BUS:
345 return sscreen->info.pci_bus;
346 case PIPE_CAP_PCI_DEVICE:
347 return sscreen->info.pci_dev;
348 case PIPE_CAP_PCI_FUNCTION:
349 return sscreen->info.pci_func;
350 }
351 return 0;
352 }
353
si_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)354 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
355 {
356 switch (param) {
357 case PIPE_CAPF_MAX_LINE_WIDTH:
358 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
359 case PIPE_CAPF_MAX_POINT_WIDTH:
360 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
361 return 8192.0f;
362 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
363 return 16.0f;
364 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
365 return 16.0f;
366 case PIPE_CAPF_GUARD_BAND_LEFT:
367 case PIPE_CAPF_GUARD_BAND_TOP:
368 case PIPE_CAPF_GUARD_BAND_RIGHT:
369 case PIPE_CAPF_GUARD_BAND_BOTTOM:
370 return 0.0f;
371 }
372 return 0.0f;
373 }
374
si_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)375 static int si_get_shader_param(struct pipe_screen* pscreen,
376 enum pipe_shader_type shader,
377 enum pipe_shader_cap param)
378 {
379 struct si_screen *sscreen = (struct si_screen *)pscreen;
380
381 switch(shader)
382 {
383 case PIPE_SHADER_FRAGMENT:
384 case PIPE_SHADER_VERTEX:
385 case PIPE_SHADER_GEOMETRY:
386 case PIPE_SHADER_TESS_CTRL:
387 case PIPE_SHADER_TESS_EVAL:
388 break;
389 case PIPE_SHADER_COMPUTE:
390 switch (param) {
391 case PIPE_SHADER_CAP_PREFERRED_IR:
392 return PIPE_SHADER_IR_NATIVE;
393
394 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
395 int ir = 1 << PIPE_SHADER_IR_NATIVE;
396
397 if (si_have_tgsi_compute(sscreen))
398 ir |= 1 << PIPE_SHADER_IR_TGSI;
399
400 return ir;
401 }
402
403 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
404 uint64_t max_const_buffer_size;
405 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
406 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
407 &max_const_buffer_size);
408 return MIN2(max_const_buffer_size, INT_MAX);
409 }
410 default:
411 /* If compute shaders don't require a special value
412 * for this cap, we can return the same value we
413 * do for other shader types. */
414 break;
415 }
416 break;
417 default:
418 return 0;
419 }
420
421 switch (param) {
422 /* Shader limits. */
423 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
424 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
425 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
426 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
427 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
428 return 16384;
429 case PIPE_SHADER_CAP_MAX_INPUTS:
430 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
431 case PIPE_SHADER_CAP_MAX_OUTPUTS:
432 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
433 case PIPE_SHADER_CAP_MAX_TEMPS:
434 return 256; /* Max native temporaries. */
435 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
436 return 4096 * sizeof(float[4]); /* actually only memory limits this */
437 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
438 return SI_NUM_CONST_BUFFERS;
439 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
440 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
441 return SI_NUM_SAMPLERS;
442 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
443 return SI_NUM_SHADER_BUFFERS;
444 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
445 return SI_NUM_IMAGES;
446 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
447 return 32;
448 case PIPE_SHADER_CAP_PREFERRED_IR:
449 if (sscreen->debug_flags & DBG(NIR))
450 return PIPE_SHADER_IR_NIR;
451 return PIPE_SHADER_IR_TGSI;
452 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
453 return 4;
454
455 /* Supported boolean features. */
456 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
457 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
458 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
459 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
460 case PIPE_SHADER_CAP_INTEGERS:
461 case PIPE_SHADER_CAP_INT64_ATOMICS:
462 case PIPE_SHADER_CAP_FP16:
463 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
464 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
465 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
466 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
467 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
468 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
469 return 1;
470
471 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
472 /* TODO: Indirect indexing of GS inputs is unimplemented. */
473 if (shader == PIPE_SHADER_GEOMETRY)
474 return 0;
475
476 if (shader == PIPE_SHADER_VERTEX &&
477 !sscreen->llvm_has_working_vgpr_indexing)
478 return 0;
479
480 /* TCS and TES load inputs directly from LDS or offchip
481 * memory, so indirect indexing is always supported.
482 * PS has to support indirect indexing, because we can't
483 * lower that to TEMPs for INTERP instructions.
484 */
485 return 1;
486
487 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
488 return sscreen->llvm_has_working_vgpr_indexing ||
489 /* TCS stores outputs directly to memory. */
490 shader == PIPE_SHADER_TESS_CTRL;
491
492 /* Unsupported boolean features. */
493 case PIPE_SHADER_CAP_SUBROUTINES:
494 case PIPE_SHADER_CAP_SUPPORTED_IRS:
495 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
496 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
497 return 0;
498 }
499 return 0;
500 }
501
502 static const struct nir_shader_compiler_options nir_options = {
503 .vertex_id_zero_based = true,
504 .lower_scmp = true,
505 .lower_flrp32 = true,
506 .lower_flrp64 = true,
507 .lower_fsat = true,
508 .lower_fdiv = true,
509 .lower_sub = true,
510 .lower_ffma = true,
511 .lower_pack_snorm_2x16 = true,
512 .lower_pack_snorm_4x8 = true,
513 .lower_pack_unorm_2x16 = true,
514 .lower_pack_unorm_4x8 = true,
515 .lower_unpack_snorm_2x16 = true,
516 .lower_unpack_snorm_4x8 = true,
517 .lower_unpack_unorm_2x16 = true,
518 .lower_unpack_unorm_4x8 = true,
519 .lower_extract_byte = true,
520 .lower_extract_word = true,
521 .max_unroll_iterations = 32,
522 .native_integers = true,
523 };
524
525 static const void *
si_get_compiler_options(struct pipe_screen * screen,enum pipe_shader_ir ir,enum pipe_shader_type shader)526 si_get_compiler_options(struct pipe_screen *screen,
527 enum pipe_shader_ir ir,
528 enum pipe_shader_type shader)
529 {
530 assert(ir == PIPE_SHADER_IR_NIR);
531 return &nir_options;
532 }
533
si_get_driver_uuid(struct pipe_screen * pscreen,char * uuid)534 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
535 {
536 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
537 }
538
si_get_device_uuid(struct pipe_screen * pscreen,char * uuid)539 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
540 {
541 struct si_screen *sscreen = (struct si_screen *)pscreen;
542
543 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
544 }
545
si_get_name(struct pipe_screen * pscreen)546 static const char* si_get_name(struct pipe_screen *pscreen)
547 {
548 struct si_screen *sscreen = (struct si_screen*)pscreen;
549
550 return sscreen->renderer_string;
551 }
552
si_get_video_param_no_decode(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)553 static int si_get_video_param_no_decode(struct pipe_screen *screen,
554 enum pipe_video_profile profile,
555 enum pipe_video_entrypoint entrypoint,
556 enum pipe_video_cap param)
557 {
558 switch (param) {
559 case PIPE_VIDEO_CAP_SUPPORTED:
560 return vl_profile_supported(screen, profile, entrypoint);
561 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
562 return 1;
563 case PIPE_VIDEO_CAP_MAX_WIDTH:
564 case PIPE_VIDEO_CAP_MAX_HEIGHT:
565 return vl_video_buffer_max_size(screen);
566 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
567 return PIPE_FORMAT_NV12;
568 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
569 return false;
570 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
571 return false;
572 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
573 return true;
574 case PIPE_VIDEO_CAP_MAX_LEVEL:
575 return vl_level_supported(screen, profile);
576 default:
577 return 0;
578 }
579 }
580
si_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)581 static int si_get_video_param(struct pipe_screen *screen,
582 enum pipe_video_profile profile,
583 enum pipe_video_entrypoint entrypoint,
584 enum pipe_video_cap param)
585 {
586 struct si_screen *sscreen = (struct si_screen *)screen;
587 enum pipe_video_format codec = u_reduce_video_profile(profile);
588
589 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
590 switch (param) {
591 case PIPE_VIDEO_CAP_SUPPORTED:
592 return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
593 (si_vce_is_fw_version_supported(sscreen) ||
594 sscreen->info.family == CHIP_RAVEN);
595 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
596 return 1;
597 case PIPE_VIDEO_CAP_MAX_WIDTH:
598 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
599 case PIPE_VIDEO_CAP_MAX_HEIGHT:
600 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
601 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
602 return PIPE_FORMAT_NV12;
603 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
604 return false;
605 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
606 return false;
607 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
608 return true;
609 case PIPE_VIDEO_CAP_STACKED_FRAMES:
610 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
611 default:
612 return 0;
613 }
614 }
615
616 switch (param) {
617 case PIPE_VIDEO_CAP_SUPPORTED:
618 switch (codec) {
619 case PIPE_VIDEO_FORMAT_MPEG12:
620 return profile != PIPE_VIDEO_PROFILE_MPEG1;
621 case PIPE_VIDEO_FORMAT_MPEG4:
622 return 1;
623 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
624 if ((sscreen->info.family == CHIP_POLARIS10 ||
625 sscreen->info.family == CHIP_POLARIS11) &&
626 sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
627 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
628 return false;
629 }
630 return true;
631 case PIPE_VIDEO_FORMAT_VC1:
632 return true;
633 case PIPE_VIDEO_FORMAT_HEVC:
634 /* Carrizo only supports HEVC Main */
635 if (sscreen->info.family >= CHIP_STONEY)
636 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
637 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
638 else if (sscreen->info.family >= CHIP_CARRIZO)
639 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
640 return false;
641 case PIPE_VIDEO_FORMAT_JPEG:
642 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
643 return false;
644 if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
645 RVID_ERR("No MJPEG support for the kernel version\n");
646 return false;
647 }
648 return true;
649 default:
650 return false;
651 }
652 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
653 return 1;
654 case PIPE_VIDEO_CAP_MAX_WIDTH:
655 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
656 case PIPE_VIDEO_CAP_MAX_HEIGHT:
657 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
658 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
659 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
660 return PIPE_FORMAT_P016;
661 else
662 return PIPE_FORMAT_NV12;
663
664 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
665 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
666 enum pipe_video_format format = u_reduce_video_profile(profile);
667
668 if (format == PIPE_VIDEO_FORMAT_HEVC)
669 return false; //The firmware doesn't support interlaced HEVC.
670 else if (format == PIPE_VIDEO_FORMAT_JPEG)
671 return false;
672 return true;
673 }
674 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
675 return true;
676 case PIPE_VIDEO_CAP_MAX_LEVEL:
677 switch (profile) {
678 case PIPE_VIDEO_PROFILE_MPEG1:
679 return 0;
680 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
681 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
682 return 3;
683 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
684 return 3;
685 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
686 return 5;
687 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
688 return 1;
689 case PIPE_VIDEO_PROFILE_VC1_MAIN:
690 return 2;
691 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
692 return 4;
693 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
694 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
695 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
696 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
697 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
698 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
699 return 186;
700 default:
701 return 0;
702 }
703 default:
704 return 0;
705 }
706 }
707
si_vid_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint)708 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
709 enum pipe_format format,
710 enum pipe_video_profile profile,
711 enum pipe_video_entrypoint entrypoint)
712 {
713 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
714 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
715 return (format == PIPE_FORMAT_NV12) ||
716 (format == PIPE_FORMAT_P016);
717
718 /* we can only handle this one with UVD */
719 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
720 return format == PIPE_FORMAT_NV12;
721
722 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
723 }
724
get_max_threads_per_block(struct si_screen * screen,enum pipe_shader_ir ir_type)725 static unsigned get_max_threads_per_block(struct si_screen *screen,
726 enum pipe_shader_ir ir_type)
727 {
728 if (ir_type != PIPE_SHADER_IR_TGSI)
729 return 256;
730
731 /* Only 16 waves per thread-group on gfx9. */
732 if (screen->info.chip_class >= GFX9)
733 return 1024;
734
735 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
736 * round number.
737 */
738 return 2048;
739 }
740
si_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)741 static int si_get_compute_param(struct pipe_screen *screen,
742 enum pipe_shader_ir ir_type,
743 enum pipe_compute_cap param,
744 void *ret)
745 {
746 struct si_screen *sscreen = (struct si_screen *)screen;
747
748 //TODO: select these params by asic
749 switch (param) {
750 case PIPE_COMPUTE_CAP_IR_TARGET: {
751 const char *gpu;
752 const char *triple;
753
754 if (HAVE_LLVM < 0x0400)
755 triple = "amdgcn--";
756 else
757 triple = "amdgcn-mesa-mesa3d";
758
759 gpu = ac_get_llvm_processor_name(sscreen->info.family);
760 if (ret) {
761 sprintf(ret, "%s-%s", gpu, triple);
762 }
763 /* +2 for dash and terminating NIL byte */
764 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
765 }
766 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
767 if (ret) {
768 uint64_t *grid_dimension = ret;
769 grid_dimension[0] = 3;
770 }
771 return 1 * sizeof(uint64_t);
772
773 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
774 if (ret) {
775 uint64_t *grid_size = ret;
776 grid_size[0] = 65535;
777 grid_size[1] = 65535;
778 grid_size[2] = 65535;
779 }
780 return 3 * sizeof(uint64_t) ;
781
782 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
783 if (ret) {
784 uint64_t *block_size = ret;
785 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
786 block_size[0] = threads_per_block;
787 block_size[1] = threads_per_block;
788 block_size[2] = threads_per_block;
789 }
790 return 3 * sizeof(uint64_t);
791
792 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
793 if (ret) {
794 uint64_t *max_threads_per_block = ret;
795 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
796 }
797 return sizeof(uint64_t);
798 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
799 if (ret) {
800 uint32_t *address_bits = ret;
801 address_bits[0] = 64;
802 }
803 return 1 * sizeof(uint32_t);
804
805 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
806 if (ret) {
807 uint64_t *max_global_size = ret;
808 uint64_t max_mem_alloc_size;
809
810 si_get_compute_param(screen, ir_type,
811 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
812 &max_mem_alloc_size);
813
814 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
815 * 1/4 of the MAX_GLOBAL_SIZE. Since the
816 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
817 * make sure we never report more than
818 * 4 * MAX_MEM_ALLOC_SIZE.
819 */
820 *max_global_size = MIN2(4 * max_mem_alloc_size,
821 MAX2(sscreen->info.gart_size,
822 sscreen->info.vram_size));
823 }
824 return sizeof(uint64_t);
825
826 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
827 if (ret) {
828 uint64_t *max_local_size = ret;
829 /* Value reported by the closed source driver. */
830 *max_local_size = 32768;
831 }
832 return sizeof(uint64_t);
833
834 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
835 if (ret) {
836 uint64_t *max_input_size = ret;
837 /* Value reported by the closed source driver. */
838 *max_input_size = 1024;
839 }
840 return sizeof(uint64_t);
841
842 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
843 if (ret) {
844 uint64_t *max_mem_alloc_size = ret;
845
846 *max_mem_alloc_size = sscreen->info.max_alloc_size;
847 }
848 return sizeof(uint64_t);
849
850 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
851 if (ret) {
852 uint32_t *max_clock_frequency = ret;
853 *max_clock_frequency = sscreen->info.max_shader_clock;
854 }
855 return sizeof(uint32_t);
856
857 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
858 if (ret) {
859 uint32_t *max_compute_units = ret;
860 *max_compute_units = sscreen->info.num_good_compute_units;
861 }
862 return sizeof(uint32_t);
863
864 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
865 if (ret) {
866 uint32_t *images_supported = ret;
867 *images_supported = 0;
868 }
869 return sizeof(uint32_t);
870 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
871 break; /* unused */
872 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
873 if (ret) {
874 uint32_t *subgroup_size = ret;
875 *subgroup_size = 64;
876 }
877 return sizeof(uint32_t);
878 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
879 if (ret) {
880 uint64_t *max_variable_threads_per_block = ret;
881 if (ir_type == PIPE_SHADER_IR_TGSI)
882 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
883 else
884 *max_variable_threads_per_block = 0;
885 }
886 return sizeof(uint64_t);
887 }
888
889 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
890 return 0;
891 }
892
si_get_timestamp(struct pipe_screen * screen)893 static uint64_t si_get_timestamp(struct pipe_screen *screen)
894 {
895 struct si_screen *sscreen = (struct si_screen*)screen;
896
897 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
898 sscreen->info.clock_crystal_freq;
899 }
900
si_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)901 static void si_query_memory_info(struct pipe_screen *screen,
902 struct pipe_memory_info *info)
903 {
904 struct si_screen *sscreen = (struct si_screen*)screen;
905 struct radeon_winsys *ws = sscreen->ws;
906 unsigned vram_usage, gtt_usage;
907
908 info->total_device_memory = sscreen->info.vram_size / 1024;
909 info->total_staging_memory = sscreen->info.gart_size / 1024;
910
911 /* The real TTM memory usage is somewhat random, because:
912 *
913 * 1) TTM delays freeing memory, because it can only free it after
914 * fences expire.
915 *
916 * 2) The memory usage can be really low if big VRAM evictions are
917 * taking place, but the real usage is well above the size of VRAM.
918 *
919 * Instead, return statistics of this process.
920 */
921 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
922 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
923
924 info->avail_device_memory =
925 vram_usage <= info->total_device_memory ?
926 info->total_device_memory - vram_usage : 0;
927 info->avail_staging_memory =
928 gtt_usage <= info->total_staging_memory ?
929 info->total_staging_memory - gtt_usage : 0;
930
931 info->device_memory_evicted =
932 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
933
934 if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
935 info->nr_device_memory_evictions =
936 ws->query_value(ws, RADEON_NUM_EVICTIONS);
937 else
938 /* Just return the number of evicted 64KB pages. */
939 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
940 }
941
si_get_disk_shader_cache(struct pipe_screen * pscreen)942 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
943 {
944 struct si_screen *sscreen = (struct si_screen*)pscreen;
945
946 return sscreen->disk_shader_cache;
947 }
948
si_init_renderer_string(struct si_screen * sscreen)949 static void si_init_renderer_string(struct si_screen *sscreen)
950 {
951 struct radeon_winsys *ws = sscreen->ws;
952 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
953 struct utsname uname_data;
954
955 const char *chip_name = si_get_marketing_name(ws);
956
957 if (chip_name)
958 snprintf(family_name, sizeof(family_name), "%s / ",
959 si_get_family_name(sscreen) + 4);
960 else
961 chip_name = si_get_family_name(sscreen);
962
963 if (uname(&uname_data) == 0)
964 snprintf(kernel_version, sizeof(kernel_version),
965 " / %s", uname_data.release);
966
967 if (HAVE_LLVM > 0) {
968 snprintf(llvm_string, sizeof(llvm_string),
969 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
970 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
971 }
972
973 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
974 "%s (%sDRM %i.%i.%i%s%s)",
975 chip_name, family_name, sscreen->info.drm_major,
976 sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
977 kernel_version, llvm_string);
978 }
979
si_init_screen_get_functions(struct si_screen * sscreen)980 void si_init_screen_get_functions(struct si_screen *sscreen)
981 {
982 sscreen->b.get_name = si_get_name;
983 sscreen->b.get_vendor = si_get_vendor;
984 sscreen->b.get_device_vendor = si_get_device_vendor;
985 sscreen->b.get_param = si_get_param;
986 sscreen->b.get_paramf = si_get_paramf;
987 sscreen->b.get_compute_param = si_get_compute_param;
988 sscreen->b.get_timestamp = si_get_timestamp;
989 sscreen->b.get_shader_param = si_get_shader_param;
990 sscreen->b.get_compiler_options = si_get_compiler_options;
991 sscreen->b.get_device_uuid = si_get_device_uuid;
992 sscreen->b.get_driver_uuid = si_get_driver_uuid;
993 sscreen->b.query_memory_info = si_query_memory_info;
994 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
995
996 if (sscreen->info.has_hw_decode) {
997 sscreen->b.get_video_param = si_get_video_param;
998 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
999 } else {
1000 sscreen->b.get_video_param = si_get_video_param_no_decode;
1001 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1002 }
1003
1004 si_init_renderer_string(sscreen);
1005 }
1006