1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "radeonsi/si_pipe.h"
25 #include "r600_cs.h"
26 #include "r600_query.h"
27 #include "util/u_format.h"
28 #include "util/u_log.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/u_resource.h"
32 #include "util/u_surface.h"
33 #include "util/os_time.h"
34 #include <errno.h>
35 #include <inttypes.h>
36 #include "state_tracker/drm_driver.h"
37 #include "amd/common/sid.h"
38
39 static void r600_texture_discard_cmask(struct si_screen *sscreen,
40 struct r600_texture *rtex);
41 static enum radeon_surf_mode
42 r600_choose_tiling(struct si_screen *sscreen,
43 const struct pipe_resource *templ);
44
45
si_prepare_for_dma_blit(struct r600_common_context * rctx,struct r600_texture * rdst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct r600_texture * rsrc,unsigned src_level,const struct pipe_box * src_box)46 bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
47 struct r600_texture *rdst,
48 unsigned dst_level, unsigned dstx,
49 unsigned dsty, unsigned dstz,
50 struct r600_texture *rsrc,
51 unsigned src_level,
52 const struct pipe_box *src_box)
53 {
54 if (!rctx->dma.cs)
55 return false;
56
57 if (rdst->surface.bpe != rsrc->surface.bpe)
58 return false;
59
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc->resource.b.b.nr_samples > 1 ||
62 rdst->resource.b.b.nr_samples > 1)
63 return false;
64
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
68 */
69 if (rsrc->is_depth || rdst->is_depth)
70 return false;
71
72 /* DCC as:
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
75 */
76 if (vi_dcc_enabled(rsrc, src_level) ||
77 vi_dcc_enabled(rdst, dst_level))
78 return false;
79
80 /* CMASK as:
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
84 */
85 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level == 0);
88 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
89 dstx, dsty, dstz, src_box->width,
90 src_box->height, src_box->depth))
91 return false;
92
93 r600_texture_discard_cmask(rctx->screen, rdst);
94 }
95
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
98 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
99
100 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
101 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
102
103 return true;
104 }
105
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
r600_copy_region_with_blit(struct pipe_context * pipe,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)107 static void r600_copy_region_with_blit(struct pipe_context *pipe,
108 struct pipe_resource *dst,
109 unsigned dst_level,
110 unsigned dstx, unsigned dsty, unsigned dstz,
111 struct pipe_resource *src,
112 unsigned src_level,
113 const struct pipe_box *src_box)
114 {
115 struct pipe_blit_info blit;
116
117 memset(&blit, 0, sizeof(blit));
118 blit.src.resource = src;
119 blit.src.format = src->format;
120 blit.src.level = src_level;
121 blit.src.box = *src_box;
122 blit.dst.resource = dst;
123 blit.dst.format = dst->format;
124 blit.dst.level = dst_level;
125 blit.dst.box.x = dstx;
126 blit.dst.box.y = dsty;
127 blit.dst.box.z = dstz;
128 blit.dst.box.width = src_box->width;
129 blit.dst.box.height = src_box->height;
130 blit.dst.box.depth = src_box->depth;
131 blit.mask = util_format_get_mask(src->format) &
132 util_format_get_mask(dst->format);
133 blit.filter = PIPE_TEX_FILTER_NEAREST;
134
135 if (blit.mask) {
136 pipe->blit(pipe, &blit);
137 }
138 }
139
140 /* Copy from a full GPU texture to a transfer's staging one. */
r600_copy_to_staging_texture(struct pipe_context * ctx,struct r600_transfer * rtransfer)141 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
142 {
143 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
144 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
145 struct pipe_resource *dst = &rtransfer->staging->b.b;
146 struct pipe_resource *src = transfer->resource;
147
148 if (src->nr_samples > 1) {
149 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
150 src, transfer->level, &transfer->box);
151 return;
152 }
153
154 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
155 &transfer->box);
156 }
157
158 /* Copy from a transfer's staging texture to a full GPU one. */
r600_copy_from_staging_texture(struct pipe_context * ctx,struct r600_transfer * rtransfer)159 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
160 {
161 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
162 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
163 struct pipe_resource *dst = transfer->resource;
164 struct pipe_resource *src = &rtransfer->staging->b.b;
165 struct pipe_box sbox;
166
167 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
168
169 if (dst->nr_samples > 1) {
170 r600_copy_region_with_blit(ctx, dst, transfer->level,
171 transfer->box.x, transfer->box.y, transfer->box.z,
172 src, 0, &sbox);
173 return;
174 }
175
176 rctx->dma_copy(ctx, dst, transfer->level,
177 transfer->box.x, transfer->box.y, transfer->box.z,
178 src, 0, &sbox);
179 }
180
r600_texture_get_offset(struct si_screen * sscreen,struct r600_texture * rtex,unsigned level,const struct pipe_box * box,unsigned * stride,unsigned * layer_stride)181 static unsigned r600_texture_get_offset(struct si_screen *sscreen,
182 struct r600_texture *rtex, unsigned level,
183 const struct pipe_box *box,
184 unsigned *stride,
185 unsigned *layer_stride)
186 {
187 if (sscreen->info.chip_class >= GFX9) {
188 *stride = rtex->surface.u.gfx9.surf_pitch * rtex->surface.bpe;
189 *layer_stride = rtex->surface.u.gfx9.surf_slice_size;
190
191 if (!box)
192 return 0;
193
194 /* Each texture is an array of slices. Each slice is an array
195 * of mipmap levels. */
196 return box->z * rtex->surface.u.gfx9.surf_slice_size +
197 rtex->surface.u.gfx9.offset[level] +
198 (box->y / rtex->surface.blk_h *
199 rtex->surface.u.gfx9.surf_pitch +
200 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
201 } else {
202 *stride = rtex->surface.u.legacy.level[level].nblk_x *
203 rtex->surface.bpe;
204 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
205 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
206
207 if (!box)
208 return rtex->surface.u.legacy.level[level].offset;
209
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return rtex->surface.u.legacy.level[level].offset +
213 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
214 (box->y / rtex->surface.blk_h *
215 rtex->surface.u.legacy.level[level].nblk_x +
216 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
217 }
218 }
219
r600_init_surface(struct si_screen * sscreen,struct radeon_surf * surface,const struct pipe_resource * ptex,enum radeon_surf_mode array_mode,unsigned pitch_in_bytes_override,unsigned offset,bool is_imported,bool is_scanout,bool is_flushed_depth,bool tc_compatible_htile)220 static int r600_init_surface(struct si_screen *sscreen,
221 struct radeon_surf *surface,
222 const struct pipe_resource *ptex,
223 enum radeon_surf_mode array_mode,
224 unsigned pitch_in_bytes_override,
225 unsigned offset,
226 bool is_imported,
227 bool is_scanout,
228 bool is_flushed_depth,
229 bool tc_compatible_htile)
230 {
231 const struct util_format_description *desc =
232 util_format_description(ptex->format);
233 bool is_depth, is_stencil;
234 int r;
235 unsigned i, bpe, flags = 0;
236
237 is_depth = util_format_has_depth(desc);
238 is_stencil = util_format_has_stencil(desc);
239
240 if (!is_flushed_depth &&
241 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
242 bpe = 4; /* stencil is allocated separately on evergreen */
243 } else {
244 bpe = util_format_get_blocksize(ptex->format);
245 assert(util_is_power_of_two(bpe));
246 }
247
248 if (!is_flushed_depth && is_depth) {
249 flags |= RADEON_SURF_ZBUFFER;
250
251 if (tc_compatible_htile &&
252 (sscreen->info.chip_class >= GFX9 ||
253 array_mode == RADEON_SURF_MODE_2D)) {
254 /* TC-compatible HTILE only supports Z32_FLOAT.
255 * GFX9 also supports Z16_UNORM.
256 * On VI, promote Z16 to Z32. DB->CB copies will convert
257 * the format for transfers.
258 */
259 if (sscreen->info.chip_class == VI)
260 bpe = 4;
261
262 flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
263 }
264
265 if (is_stencil)
266 flags |= RADEON_SURF_SBUFFER;
267 }
268
269 if (sscreen->info.chip_class >= VI &&
270 (ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
271 ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
272 /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
273 (ptex->nr_samples >= 2 &&
274 (!sscreen->dcc_msaa_allowed || ptex->array_size > 1))))
275 flags |= RADEON_SURF_DISABLE_DCC;
276
277 if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
278 /* This should catch bugs in gallium users setting incorrect flags. */
279 assert(ptex->nr_samples <= 1 &&
280 ptex->array_size == 1 &&
281 ptex->depth0 == 1 &&
282 ptex->last_level == 0 &&
283 !(flags & RADEON_SURF_Z_OR_SBUFFER));
284
285 flags |= RADEON_SURF_SCANOUT;
286 }
287
288 if (ptex->bind & PIPE_BIND_SHARED)
289 flags |= RADEON_SURF_SHAREABLE;
290 if (is_imported)
291 flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
292 if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
293 flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
294
295 r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
296 array_mode, surface);
297 if (r) {
298 return r;
299 }
300
301 unsigned pitch = pitch_in_bytes_override / bpe;
302
303 if (sscreen->info.chip_class >= GFX9) {
304 if (pitch) {
305 surface->u.gfx9.surf_pitch = pitch;
306 surface->u.gfx9.surf_slice_size =
307 (uint64_t)pitch * surface->u.gfx9.surf_height * bpe;
308 }
309 surface->u.gfx9.surf_offset = offset;
310 } else {
311 if (pitch) {
312 surface->u.legacy.level[0].nblk_x = pitch;
313 surface->u.legacy.level[0].slice_size_dw =
314 ((uint64_t)pitch * surface->u.legacy.level[0].nblk_y * bpe) / 4;
315 }
316 if (offset) {
317 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
318 surface->u.legacy.level[i].offset += offset;
319 }
320 }
321 return 0;
322 }
323
r600_texture_init_metadata(struct si_screen * sscreen,struct r600_texture * rtex,struct radeon_bo_metadata * metadata)324 static void r600_texture_init_metadata(struct si_screen *sscreen,
325 struct r600_texture *rtex,
326 struct radeon_bo_metadata *metadata)
327 {
328 struct radeon_surf *surface = &rtex->surface;
329
330 memset(metadata, 0, sizeof(*metadata));
331
332 if (sscreen->info.chip_class >= GFX9) {
333 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
334 } else {
335 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
336 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
337 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
338 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
339 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
340 metadata->u.legacy.bankw = surface->u.legacy.bankw;
341 metadata->u.legacy.bankh = surface->u.legacy.bankh;
342 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
343 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
344 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
345 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
346 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
347 }
348 }
349
r600_surface_import_metadata(struct si_screen * sscreen,struct radeon_surf * surf,struct radeon_bo_metadata * metadata,enum radeon_surf_mode * array_mode,bool * is_scanout)350 static void r600_surface_import_metadata(struct si_screen *sscreen,
351 struct radeon_surf *surf,
352 struct radeon_bo_metadata *metadata,
353 enum radeon_surf_mode *array_mode,
354 bool *is_scanout)
355 {
356 if (sscreen->info.chip_class >= GFX9) {
357 if (metadata->u.gfx9.swizzle_mode > 0)
358 *array_mode = RADEON_SURF_MODE_2D;
359 else
360 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
361
362 *is_scanout = metadata->u.gfx9.swizzle_mode == 0 ||
363 metadata->u.gfx9.swizzle_mode % 4 == 2;
364
365 surf->u.gfx9.surf.swizzle_mode = metadata->u.gfx9.swizzle_mode;
366 } else {
367 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
368 surf->u.legacy.bankw = metadata->u.legacy.bankw;
369 surf->u.legacy.bankh = metadata->u.legacy.bankh;
370 surf->u.legacy.tile_split = metadata->u.legacy.tile_split;
371 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
372 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
373
374 if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED)
375 *array_mode = RADEON_SURF_MODE_2D;
376 else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
377 *array_mode = RADEON_SURF_MODE_1D;
378 else
379 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
380
381 *is_scanout = metadata->u.legacy.scanout;
382 }
383 }
384
r600_eliminate_fast_color_clear(struct r600_common_context * rctx,struct r600_texture * rtex)385 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
386 struct r600_texture *rtex)
387 {
388 struct si_screen *sscreen = rctx->screen;
389 struct pipe_context *ctx = &rctx->b;
390
391 if (ctx == sscreen->aux_context)
392 mtx_lock(&sscreen->aux_context_lock);
393
394 ctx->flush_resource(ctx, &rtex->resource.b.b);
395 ctx->flush(ctx, NULL, 0);
396
397 if (ctx == sscreen->aux_context)
398 mtx_unlock(&sscreen->aux_context_lock);
399 }
400
r600_texture_discard_cmask(struct si_screen * sscreen,struct r600_texture * rtex)401 static void r600_texture_discard_cmask(struct si_screen *sscreen,
402 struct r600_texture *rtex)
403 {
404 if (!rtex->cmask.size)
405 return;
406
407 assert(rtex->resource.b.b.nr_samples <= 1);
408
409 /* Disable CMASK. */
410 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
411 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
412 rtex->dirty_level_mask = 0;
413
414 rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
415
416 if (rtex->cmask_buffer != &rtex->resource)
417 r600_resource_reference(&rtex->cmask_buffer, NULL);
418
419 /* Notify all contexts about the change. */
420 p_atomic_inc(&sscreen->dirty_tex_counter);
421 p_atomic_inc(&sscreen->compressed_colortex_counter);
422 }
423
r600_can_disable_dcc(struct r600_texture * rtex)424 static bool r600_can_disable_dcc(struct r600_texture *rtex)
425 {
426 /* We can't disable DCC if it can be written by another process. */
427 return rtex->dcc_offset &&
428 (!rtex->resource.b.is_shared ||
429 !(rtex->resource.external_usage & PIPE_HANDLE_USAGE_WRITE));
430 }
431
r600_texture_discard_dcc(struct si_screen * sscreen,struct r600_texture * rtex)432 static bool r600_texture_discard_dcc(struct si_screen *sscreen,
433 struct r600_texture *rtex)
434 {
435 if (!r600_can_disable_dcc(rtex))
436 return false;
437
438 assert(rtex->dcc_separate_buffer == NULL);
439
440 /* Disable DCC. */
441 rtex->dcc_offset = 0;
442
443 /* Notify all contexts about the change. */
444 p_atomic_inc(&sscreen->dirty_tex_counter);
445 return true;
446 }
447
448 /**
449 * Disable DCC for the texture. (first decompress, then discard metadata).
450 *
451 * There is unresolved multi-context synchronization issue between
452 * screen::aux_context and the current context. If applications do this with
453 * multiple contexts, it's already undefined behavior for them and we don't
454 * have to worry about that. The scenario is:
455 *
456 * If context 1 disables DCC and context 2 has queued commands that write
457 * to the texture via CB with DCC enabled, and the order of operations is
458 * as follows:
459 * context 2 queues draw calls rendering to the texture, but doesn't flush
460 * context 1 disables DCC and flushes
461 * context 1 & 2 reset descriptors and FB state
462 * context 2 flushes (new compressed tiles written by the draw calls)
463 * context 1 & 2 read garbage, because DCC is disabled, yet there are
464 * compressed tiled
465 *
466 * \param rctx the current context if you have one, or rscreen->aux_context
467 * if you don't.
468 */
si_texture_disable_dcc(struct r600_common_context * rctx,struct r600_texture * rtex)469 bool si_texture_disable_dcc(struct r600_common_context *rctx,
470 struct r600_texture *rtex)
471 {
472 struct si_screen *sscreen = rctx->screen;
473
474 if (!r600_can_disable_dcc(rtex))
475 return false;
476
477 if (&rctx->b == sscreen->aux_context)
478 mtx_lock(&sscreen->aux_context_lock);
479
480 /* Decompress DCC. */
481 rctx->decompress_dcc(&rctx->b, rtex);
482 rctx->b.flush(&rctx->b, NULL, 0);
483
484 if (&rctx->b == sscreen->aux_context)
485 mtx_unlock(&sscreen->aux_context_lock);
486
487 return r600_texture_discard_dcc(sscreen, rtex);
488 }
489
r600_reallocate_texture_inplace(struct r600_common_context * rctx,struct r600_texture * rtex,unsigned new_bind_flag,bool invalidate_storage)490 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
491 struct r600_texture *rtex,
492 unsigned new_bind_flag,
493 bool invalidate_storage)
494 {
495 struct pipe_screen *screen = rctx->b.screen;
496 struct r600_texture *new_tex;
497 struct pipe_resource templ = rtex->resource.b.b;
498 unsigned i;
499
500 templ.bind |= new_bind_flag;
501
502 if (rtex->resource.b.is_shared)
503 return;
504
505 if (new_bind_flag == PIPE_BIND_LINEAR) {
506 if (rtex->surface.is_linear)
507 return;
508
509 /* This fails with MSAA, depth, and compressed textures. */
510 if (r600_choose_tiling(rctx->screen, &templ) !=
511 RADEON_SURF_MODE_LINEAR_ALIGNED)
512 return;
513 }
514
515 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
516 if (!new_tex)
517 return;
518
519 /* Copy the pixels to the new texture. */
520 if (!invalidate_storage) {
521 for (i = 0; i <= templ.last_level; i++) {
522 struct pipe_box box;
523
524 u_box_3d(0, 0, 0,
525 u_minify(templ.width0, i), u_minify(templ.height0, i),
526 util_num_layers(&templ, i), &box);
527
528 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
529 &rtex->resource.b.b, i, &box);
530 }
531 }
532
533 if (new_bind_flag == PIPE_BIND_LINEAR) {
534 r600_texture_discard_cmask(rctx->screen, rtex);
535 r600_texture_discard_dcc(rctx->screen, rtex);
536 }
537
538 /* Replace the structure fields of rtex. */
539 rtex->resource.b.b.bind = templ.bind;
540 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
541 rtex->resource.gpu_address = new_tex->resource.gpu_address;
542 rtex->resource.vram_usage = new_tex->resource.vram_usage;
543 rtex->resource.gart_usage = new_tex->resource.gart_usage;
544 rtex->resource.bo_size = new_tex->resource.bo_size;
545 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
546 rtex->resource.domains = new_tex->resource.domains;
547 rtex->resource.flags = new_tex->resource.flags;
548 rtex->size = new_tex->size;
549 rtex->db_render_format = new_tex->db_render_format;
550 rtex->db_compatible = new_tex->db_compatible;
551 rtex->can_sample_z = new_tex->can_sample_z;
552 rtex->can_sample_s = new_tex->can_sample_s;
553 rtex->surface = new_tex->surface;
554 rtex->fmask = new_tex->fmask;
555 rtex->cmask = new_tex->cmask;
556 rtex->cb_color_info = new_tex->cb_color_info;
557 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
558 rtex->htile_offset = new_tex->htile_offset;
559 rtex->tc_compatible_htile = new_tex->tc_compatible_htile;
560 rtex->depth_cleared = new_tex->depth_cleared;
561 rtex->stencil_cleared = new_tex->stencil_cleared;
562 rtex->dcc_gather_statistics = new_tex->dcc_gather_statistics;
563 rtex->framebuffers_bound = new_tex->framebuffers_bound;
564
565 if (new_bind_flag == PIPE_BIND_LINEAR) {
566 assert(!rtex->htile_offset);
567 assert(!rtex->cmask.size);
568 assert(!rtex->fmask.size);
569 assert(!rtex->dcc_offset);
570 assert(!rtex->is_depth);
571 }
572
573 r600_texture_reference(&new_tex, NULL);
574
575 p_atomic_inc(&rctx->screen->dirty_tex_counter);
576 }
577
si_get_bo_metadata_word1(struct si_screen * sscreen)578 static uint32_t si_get_bo_metadata_word1(struct si_screen *sscreen)
579 {
580 return (ATI_VENDOR_ID << 16) | sscreen->info.pci_id;
581 }
582
si_query_opaque_metadata(struct si_screen * sscreen,struct r600_texture * rtex,struct radeon_bo_metadata * md)583 static void si_query_opaque_metadata(struct si_screen *sscreen,
584 struct r600_texture *rtex,
585 struct radeon_bo_metadata *md)
586 {
587 struct pipe_resource *res = &rtex->resource.b.b;
588 static const unsigned char swizzle[] = {
589 PIPE_SWIZZLE_X,
590 PIPE_SWIZZLE_Y,
591 PIPE_SWIZZLE_Z,
592 PIPE_SWIZZLE_W
593 };
594 uint32_t desc[8], i;
595 bool is_array = util_texture_is_array(res->target);
596
597 /* DRM 2.x.x doesn't support this. */
598 if (sscreen->info.drm_major != 3)
599 return;
600
601 assert(rtex->dcc_separate_buffer == NULL);
602 assert(rtex->fmask.size == 0);
603
604 /* Metadata image format format version 1:
605 * [0] = 1 (metadata format identifier)
606 * [1] = (VENDOR_ID << 16) | PCI_ID
607 * [2:9] = image descriptor for the whole resource
608 * [2] is always 0, because the base address is cleared
609 * [9] is the DCC offset bits [39:8] from the beginning of
610 * the buffer
611 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
612 */
613
614 md->metadata[0] = 1; /* metadata image format version 1 */
615
616 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
617 md->metadata[1] = si_get_bo_metadata_word1(sscreen);
618
619 si_make_texture_descriptor(sscreen, rtex, true,
620 res->target, res->format,
621 swizzle, 0, res->last_level, 0,
622 is_array ? res->array_size - 1 : 0,
623 res->width0, res->height0, res->depth0,
624 desc, NULL);
625
626 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
627 0, 0, rtex->surface.blk_w, false, desc);
628
629 /* Clear the base address and set the relative DCC offset. */
630 desc[0] = 0;
631 desc[1] &= C_008F14_BASE_ADDRESS_HI;
632 desc[7] = rtex->dcc_offset >> 8;
633
634 /* Dwords [2:9] contain the image descriptor. */
635 memcpy(&md->metadata[2], desc, sizeof(desc));
636 md->size_metadata = 10 * 4;
637
638 /* Dwords [10:..] contain the mipmap level offsets. */
639 if (sscreen->info.chip_class <= VI) {
640 for (i = 0; i <= res->last_level; i++)
641 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
642
643 md->size_metadata += (1 + res->last_level) * 4;
644 }
645 }
646
si_apply_opaque_metadata(struct si_screen * sscreen,struct r600_texture * rtex,struct radeon_bo_metadata * md)647 static void si_apply_opaque_metadata(struct si_screen *sscreen,
648 struct r600_texture *rtex,
649 struct radeon_bo_metadata *md)
650 {
651 uint32_t *desc = &md->metadata[2];
652
653 if (sscreen->info.chip_class < VI)
654 return;
655
656 /* Return if DCC is enabled. The texture should be set up with it
657 * already.
658 */
659 if (md->size_metadata >= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
660 md->metadata[0] != 0 &&
661 md->metadata[1] == si_get_bo_metadata_word1(sscreen) &&
662 G_008F28_COMPRESSION_EN(desc[6])) {
663 rtex->dcc_offset = (uint64_t)desc[7] << 8;
664 return;
665 }
666
667 /* Disable DCC. These are always set by texture_from_handle and must
668 * be cleared here.
669 */
670 rtex->dcc_offset = 0;
671 }
672
r600_texture_get_handle(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_resource * resource,struct winsys_handle * whandle,unsigned usage)673 static boolean r600_texture_get_handle(struct pipe_screen* screen,
674 struct pipe_context *ctx,
675 struct pipe_resource *resource,
676 struct winsys_handle *whandle,
677 unsigned usage)
678 {
679 struct si_screen *sscreen = (struct si_screen*)screen;
680 struct r600_common_context *rctx;
681 struct r600_resource *res = (struct r600_resource*)resource;
682 struct r600_texture *rtex = (struct r600_texture*)resource;
683 struct radeon_bo_metadata metadata;
684 bool update_metadata = false;
685 unsigned stride, offset, slice_size;
686 bool flush = false;
687
688 ctx = threaded_context_unwrap_sync(ctx);
689 rctx = (struct r600_common_context*)(ctx ? ctx : sscreen->aux_context);
690
691 if (resource->target != PIPE_BUFFER) {
692 /* This is not supported now, but it might be required for OpenCL
693 * interop in the future.
694 */
695 if (resource->nr_samples > 1 || rtex->is_depth)
696 return false;
697
698 /* Move a suballocated texture into a non-suballocated allocation. */
699 if (sscreen->ws->buffer_is_suballocated(res->buf) ||
700 rtex->surface.tile_swizzle ||
701 (rtex->resource.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
702 whandle->type != DRM_API_HANDLE_TYPE_KMS)) {
703 assert(!res->b.is_shared);
704 r600_reallocate_texture_inplace(rctx, rtex,
705 PIPE_BIND_SHARED, false);
706 flush = true;
707 assert(res->b.b.bind & PIPE_BIND_SHARED);
708 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
709 assert(!(res->flags & RADEON_FLAG_NO_INTERPROCESS_SHARING));
710 assert(rtex->surface.tile_swizzle == 0);
711 }
712
713 /* Since shader image stores don't support DCC on VI,
714 * disable it for external clients that want write
715 * access.
716 */
717 if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
718 if (si_texture_disable_dcc(rctx, rtex)) {
719 update_metadata = true;
720 /* si_texture_disable_dcc flushes the context */
721 flush = false;
722 }
723 }
724
725 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
726 (rtex->cmask.size || rtex->dcc_offset)) {
727 /* Eliminate fast clear (both CMASK and DCC) */
728 r600_eliminate_fast_color_clear(rctx, rtex);
729 /* eliminate_fast_color_clear flushes the context */
730 flush = false;
731
732 /* Disable CMASK if flush_resource isn't going
733 * to be called.
734 */
735 if (rtex->cmask.size)
736 r600_texture_discard_cmask(sscreen, rtex);
737 }
738
739 /* Set metadata. */
740 if (!res->b.is_shared || update_metadata) {
741 r600_texture_init_metadata(sscreen, rtex, &metadata);
742 si_query_opaque_metadata(sscreen, rtex, &metadata);
743
744 sscreen->ws->buffer_set_metadata(res->buf, &metadata);
745 }
746
747 if (sscreen->info.chip_class >= GFX9) {
748 offset = rtex->surface.u.gfx9.surf_offset;
749 stride = rtex->surface.u.gfx9.surf_pitch *
750 rtex->surface.bpe;
751 slice_size = rtex->surface.u.gfx9.surf_slice_size;
752 } else {
753 offset = rtex->surface.u.legacy.level[0].offset;
754 stride = rtex->surface.u.legacy.level[0].nblk_x *
755 rtex->surface.bpe;
756 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
757 }
758 } else {
759 /* Buffer exports are for the OpenCL interop. */
760 /* Move a suballocated buffer into a non-suballocated allocation. */
761 if (sscreen->ws->buffer_is_suballocated(res->buf) ||
762 /* A DMABUF export always fails if the BO is local. */
763 rtex->resource.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING) {
764 assert(!res->b.is_shared);
765
766 /* Allocate a new buffer with PIPE_BIND_SHARED. */
767 struct pipe_resource templ = res->b.b;
768 templ.bind |= PIPE_BIND_SHARED;
769
770 struct pipe_resource *newb =
771 screen->resource_create(screen, &templ);
772 if (!newb)
773 return false;
774
775 /* Copy the old buffer contents to the new one. */
776 struct pipe_box box;
777 u_box_1d(0, newb->width0, &box);
778 rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
779 &res->b.b, 0, &box);
780 flush = true;
781 /* Move the new buffer storage to the old pipe_resource. */
782 si_replace_buffer_storage(&rctx->b, &res->b.b, newb);
783 pipe_resource_reference(&newb, NULL);
784
785 assert(res->b.b.bind & PIPE_BIND_SHARED);
786 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
787 }
788
789 /* Buffers */
790 offset = 0;
791 stride = 0;
792 slice_size = 0;
793 }
794
795 if (flush)
796 rctx->b.flush(&rctx->b, NULL, 0);
797
798 if (res->b.is_shared) {
799 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
800 * doesn't set it.
801 */
802 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
803 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
804 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
805 } else {
806 res->b.is_shared = true;
807 res->external_usage = usage;
808 }
809
810 return sscreen->ws->buffer_get_handle(res->buf, stride, offset,
811 slice_size, whandle);
812 }
813
r600_texture_destroy(struct pipe_screen * screen,struct pipe_resource * ptex)814 static void r600_texture_destroy(struct pipe_screen *screen,
815 struct pipe_resource *ptex)
816 {
817 struct r600_texture *rtex = (struct r600_texture*)ptex;
818 struct r600_resource *resource = &rtex->resource;
819
820 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
821
822 if (rtex->cmask_buffer != &rtex->resource) {
823 r600_resource_reference(&rtex->cmask_buffer, NULL);
824 }
825 pb_reference(&resource->buf, NULL);
826 r600_resource_reference(&rtex->dcc_separate_buffer, NULL);
827 r600_resource_reference(&rtex->last_dcc_separate_buffer, NULL);
828 FREE(rtex);
829 }
830
831 static const struct u_resource_vtbl r600_texture_vtbl;
832
833 /* The number of samples can be specified independently of the texture. */
si_texture_get_fmask_info(struct si_screen * sscreen,struct r600_texture * rtex,unsigned nr_samples,struct r600_fmask_info * out)834 void si_texture_get_fmask_info(struct si_screen *sscreen,
835 struct r600_texture *rtex,
836 unsigned nr_samples,
837 struct r600_fmask_info *out)
838 {
839 /* FMASK is allocated like an ordinary texture. */
840 struct pipe_resource templ = rtex->resource.b.b;
841 struct radeon_surf fmask = {};
842 unsigned flags, bpe;
843
844 memset(out, 0, sizeof(*out));
845
846 if (sscreen->info.chip_class >= GFX9) {
847 out->alignment = rtex->surface.u.gfx9.fmask_alignment;
848 out->size = rtex->surface.u.gfx9.fmask_size;
849 return;
850 }
851
852 templ.nr_samples = 1;
853 flags = rtex->surface.flags | RADEON_SURF_FMASK;
854
855 switch (nr_samples) {
856 case 2:
857 case 4:
858 bpe = 1;
859 break;
860 case 8:
861 bpe = 4;
862 break;
863 default:
864 R600_ERR("Invalid sample count for FMASK allocation.\n");
865 return;
866 }
867
868 if (sscreen->ws->surface_init(sscreen->ws, &templ, flags, bpe,
869 RADEON_SURF_MODE_2D, &fmask)) {
870 R600_ERR("Got error in surface_init while allocating FMASK.\n");
871 return;
872 }
873
874 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
875
876 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
877 if (out->slice_tile_max)
878 out->slice_tile_max -= 1;
879
880 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
881 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
882 out->bank_height = fmask.u.legacy.bankh;
883 out->tile_swizzle = fmask.tile_swizzle;
884 out->alignment = MAX2(256, fmask.surf_alignment);
885 out->size = fmask.surf_size;
886 }
887
r600_texture_allocate_fmask(struct si_screen * sscreen,struct r600_texture * rtex)888 static void r600_texture_allocate_fmask(struct si_screen *sscreen,
889 struct r600_texture *rtex)
890 {
891 si_texture_get_fmask_info(sscreen, rtex,
892 rtex->resource.b.b.nr_samples, &rtex->fmask);
893
894 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
895 rtex->size = rtex->fmask.offset + rtex->fmask.size;
896 }
897
si_texture_get_cmask_info(struct si_screen * sscreen,struct r600_texture * rtex,struct r600_cmask_info * out)898 void si_texture_get_cmask_info(struct si_screen *sscreen,
899 struct r600_texture *rtex,
900 struct r600_cmask_info *out)
901 {
902 unsigned pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
903 unsigned num_pipes = sscreen->info.num_tile_pipes;
904 unsigned cl_width, cl_height;
905
906 if (sscreen->info.chip_class >= GFX9) {
907 out->alignment = rtex->surface.u.gfx9.cmask_alignment;
908 out->size = rtex->surface.u.gfx9.cmask_size;
909 return;
910 }
911
912 switch (num_pipes) {
913 case 2:
914 cl_width = 32;
915 cl_height = 16;
916 break;
917 case 4:
918 cl_width = 32;
919 cl_height = 32;
920 break;
921 case 8:
922 cl_width = 64;
923 cl_height = 32;
924 break;
925 case 16: /* Hawaii */
926 cl_width = 64;
927 cl_height = 64;
928 break;
929 default:
930 assert(0);
931 return;
932 }
933
934 unsigned base_align = num_pipes * pipe_interleave_bytes;
935
936 unsigned width = align(rtex->resource.b.b.width0, cl_width*8);
937 unsigned height = align(rtex->resource.b.b.height0, cl_height*8);
938 unsigned slice_elements = (width * height) / (8*8);
939
940 /* Each element of CMASK is a nibble. */
941 unsigned slice_bytes = slice_elements / 2;
942
943 out->slice_tile_max = (width * height) / (128*128);
944 if (out->slice_tile_max)
945 out->slice_tile_max -= 1;
946
947 out->alignment = MAX2(256, base_align);
948 out->size = util_num_layers(&rtex->resource.b.b, 0) *
949 align(slice_bytes, base_align);
950 }
951
r600_texture_allocate_cmask(struct si_screen * sscreen,struct r600_texture * rtex)952 static void r600_texture_allocate_cmask(struct si_screen *sscreen,
953 struct r600_texture *rtex)
954 {
955 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
956
957 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
958 rtex->size = rtex->cmask.offset + rtex->cmask.size;
959
960 rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
961 }
962
r600_texture_get_htile_size(struct si_screen * sscreen,struct r600_texture * rtex)963 static void r600_texture_get_htile_size(struct si_screen *sscreen,
964 struct r600_texture *rtex)
965 {
966 unsigned cl_width, cl_height, width, height;
967 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
968 unsigned num_pipes = sscreen->info.num_tile_pipes;
969
970 assert(sscreen->info.chip_class <= VI);
971
972 rtex->surface.htile_size = 0;
973
974 /* HTILE is broken with 1D tiling on old kernels and CIK. */
975 if (sscreen->info.chip_class >= CIK &&
976 rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
977 sscreen->info.drm_major == 2 && sscreen->info.drm_minor < 38)
978 return;
979
980 /* Overalign HTILE on P2 configs to work around GPU hangs in
981 * piglit/depthstencil-render-miplevels 585.
982 *
983 * This has been confirmed to help Kabini & Stoney, where the hangs
984 * are always reproducible. I think I have seen the test hang
985 * on Carrizo too, though it was very rare there.
986 */
987 if (sscreen->info.chip_class >= CIK && num_pipes < 4)
988 num_pipes = 4;
989
990 switch (num_pipes) {
991 case 1:
992 cl_width = 32;
993 cl_height = 16;
994 break;
995 case 2:
996 cl_width = 32;
997 cl_height = 32;
998 break;
999 case 4:
1000 cl_width = 64;
1001 cl_height = 32;
1002 break;
1003 case 8:
1004 cl_width = 64;
1005 cl_height = 64;
1006 break;
1007 case 16:
1008 cl_width = 128;
1009 cl_height = 64;
1010 break;
1011 default:
1012 assert(0);
1013 return;
1014 }
1015
1016 width = align(rtex->resource.b.b.width0, cl_width * 8);
1017 height = align(rtex->resource.b.b.height0, cl_height * 8);
1018
1019 slice_elements = (width * height) / (8 * 8);
1020 slice_bytes = slice_elements * 4;
1021
1022 pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
1023 base_align = num_pipes * pipe_interleave_bytes;
1024
1025 rtex->surface.htile_alignment = base_align;
1026 rtex->surface.htile_size =
1027 util_num_layers(&rtex->resource.b.b, 0) *
1028 align(slice_bytes, base_align);
1029 }
1030
r600_texture_allocate_htile(struct si_screen * sscreen,struct r600_texture * rtex)1031 static void r600_texture_allocate_htile(struct si_screen *sscreen,
1032 struct r600_texture *rtex)
1033 {
1034 if (sscreen->info.chip_class <= VI && !rtex->tc_compatible_htile)
1035 r600_texture_get_htile_size(sscreen, rtex);
1036
1037 if (!rtex->surface.htile_size)
1038 return;
1039
1040 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
1041 rtex->size = rtex->htile_offset + rtex->surface.htile_size;
1042 }
1043
si_print_texture_info(struct si_screen * sscreen,struct r600_texture * rtex,struct u_log_context * log)1044 void si_print_texture_info(struct si_screen *sscreen,
1045 struct r600_texture *rtex, struct u_log_context *log)
1046 {
1047 int i;
1048
1049 /* Common parameters. */
1050 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1051 "blk_h=%u, array_size=%u, last_level=%u, "
1052 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1053 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
1054 rtex->resource.b.b.depth0, rtex->surface.blk_w,
1055 rtex->surface.blk_h,
1056 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
1057 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
1058 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
1059
1060 if (sscreen->info.chip_class >= GFX9) {
1061 u_log_printf(log, " Surf: size=%"PRIu64", slice_size=%"PRIu64", "
1062 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1063 rtex->surface.surf_size,
1064 rtex->surface.u.gfx9.surf_slice_size,
1065 rtex->surface.surf_alignment,
1066 rtex->surface.u.gfx9.surf.swizzle_mode,
1067 rtex->surface.u.gfx9.surf.epitch,
1068 rtex->surface.u.gfx9.surf_pitch);
1069
1070 if (rtex->fmask.size) {
1071 u_log_printf(log, " FMASK: offset=%"PRIu64", size=%"PRIu64", "
1072 "alignment=%u, swmode=%u, epitch=%u\n",
1073 rtex->fmask.offset,
1074 rtex->surface.u.gfx9.fmask_size,
1075 rtex->surface.u.gfx9.fmask_alignment,
1076 rtex->surface.u.gfx9.fmask.swizzle_mode,
1077 rtex->surface.u.gfx9.fmask.epitch);
1078 }
1079
1080 if (rtex->cmask.size) {
1081 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", "
1082 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1083 rtex->cmask.offset,
1084 rtex->surface.u.gfx9.cmask_size,
1085 rtex->surface.u.gfx9.cmask_alignment,
1086 rtex->surface.u.gfx9.cmask.rb_aligned,
1087 rtex->surface.u.gfx9.cmask.pipe_aligned);
1088 }
1089
1090 if (rtex->htile_offset) {
1091 u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, alignment=%u, "
1092 "rb_aligned=%u, pipe_aligned=%u\n",
1093 rtex->htile_offset,
1094 rtex->surface.htile_size,
1095 rtex->surface.htile_alignment,
1096 rtex->surface.u.gfx9.htile.rb_aligned,
1097 rtex->surface.u.gfx9.htile.pipe_aligned);
1098 }
1099
1100 if (rtex->dcc_offset) {
1101 u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, "
1102 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1103 rtex->dcc_offset, rtex->surface.dcc_size,
1104 rtex->surface.dcc_alignment,
1105 rtex->surface.u.gfx9.dcc_pitch_max,
1106 rtex->surface.num_dcc_levels);
1107 }
1108
1109 if (rtex->surface.u.gfx9.stencil_offset) {
1110 u_log_printf(log, " Stencil: offset=%"PRIu64", swmode=%u, epitch=%u\n",
1111 rtex->surface.u.gfx9.stencil_offset,
1112 rtex->surface.u.gfx9.stencil.swizzle_mode,
1113 rtex->surface.u.gfx9.stencil.epitch);
1114 }
1115 return;
1116 }
1117
1118 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
1119 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1120 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
1121 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
1122 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
1123 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
1124
1125 if (rtex->fmask.size)
1126 u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
1127 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1128 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
1129 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
1130 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
1131
1132 if (rtex->cmask.size)
1133 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
1134 "slice_tile_max=%u\n",
1135 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
1136 rtex->cmask.slice_tile_max);
1137
1138 if (rtex->htile_offset)
1139 u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, "
1140 "alignment=%u, TC_compatible = %u\n",
1141 rtex->htile_offset, rtex->surface.htile_size,
1142 rtex->surface.htile_alignment,
1143 rtex->tc_compatible_htile);
1144
1145 if (rtex->dcc_offset) {
1146 u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, alignment=%u\n",
1147 rtex->dcc_offset, rtex->surface.dcc_size,
1148 rtex->surface.dcc_alignment);
1149 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
1150 u_log_printf(log, " DCCLevel[%i]: enabled=%u, offset=%u, "
1151 "fast_clear_size=%u\n",
1152 i, i < rtex->surface.num_dcc_levels,
1153 rtex->surface.u.legacy.level[i].dcc_offset,
1154 rtex->surface.u.legacy.level[i].dcc_fast_clear_size);
1155 }
1156
1157 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
1158 u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
1159 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1160 "mode=%u, tiling_index = %u\n",
1161 i, rtex->surface.u.legacy.level[i].offset,
1162 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
1163 u_minify(rtex->resource.b.b.width0, i),
1164 u_minify(rtex->resource.b.b.height0, i),
1165 u_minify(rtex->resource.b.b.depth0, i),
1166 rtex->surface.u.legacy.level[i].nblk_x,
1167 rtex->surface.u.legacy.level[i].nblk_y,
1168 rtex->surface.u.legacy.level[i].mode,
1169 rtex->surface.u.legacy.tiling_index[i]);
1170
1171 if (rtex->surface.has_stencil) {
1172 u_log_printf(log, " StencilLayout: tilesplit=%u\n",
1173 rtex->surface.u.legacy.stencil_tile_split);
1174 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
1175 u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
1176 "slice_size=%"PRIu64", npix_x=%u, "
1177 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1178 "mode=%u, tiling_index = %u\n",
1179 i, rtex->surface.u.legacy.stencil_level[i].offset,
1180 (uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4,
1181 u_minify(rtex->resource.b.b.width0, i),
1182 u_minify(rtex->resource.b.b.height0, i),
1183 u_minify(rtex->resource.b.b.depth0, i),
1184 rtex->surface.u.legacy.stencil_level[i].nblk_x,
1185 rtex->surface.u.legacy.stencil_level[i].nblk_y,
1186 rtex->surface.u.legacy.stencil_level[i].mode,
1187 rtex->surface.u.legacy.stencil_tiling_index[i]);
1188 }
1189 }
1190 }
1191
1192 /* Common processing for r600_texture_create and r600_texture_from_handle */
1193 static struct r600_texture *
r600_texture_create_object(struct pipe_screen * screen,const struct pipe_resource * base,struct pb_buffer * buf,struct radeon_surf * surface)1194 r600_texture_create_object(struct pipe_screen *screen,
1195 const struct pipe_resource *base,
1196 struct pb_buffer *buf,
1197 struct radeon_surf *surface)
1198 {
1199 struct r600_texture *rtex;
1200 struct r600_resource *resource;
1201 struct si_screen *sscreen = (struct si_screen*)screen;
1202
1203 rtex = CALLOC_STRUCT(r600_texture);
1204 if (!rtex)
1205 return NULL;
1206
1207 resource = &rtex->resource;
1208 resource->b.b = *base;
1209 resource->b.b.next = NULL;
1210 resource->b.vtbl = &r600_texture_vtbl;
1211 pipe_reference_init(&resource->b.b.reference, 1);
1212 resource->b.b.screen = screen;
1213
1214 /* don't include stencil-only formats which we don't support for rendering */
1215 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
1216
1217 rtex->surface = *surface;
1218 rtex->size = rtex->surface.surf_size;
1219
1220 rtex->tc_compatible_htile = rtex->surface.htile_size != 0 &&
1221 (rtex->surface.flags &
1222 RADEON_SURF_TC_COMPATIBLE_HTILE);
1223
1224 /* TC-compatible HTILE:
1225 * - VI only supports Z32_FLOAT.
1226 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1227 if (rtex->tc_compatible_htile) {
1228 if (sscreen->info.chip_class >= GFX9 &&
1229 base->format == PIPE_FORMAT_Z16_UNORM)
1230 rtex->db_render_format = base->format;
1231 else {
1232 rtex->db_render_format = PIPE_FORMAT_Z32_FLOAT;
1233 rtex->upgraded_depth = base->format != PIPE_FORMAT_Z32_FLOAT &&
1234 base->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT;
1235 }
1236 } else {
1237 rtex->db_render_format = base->format;
1238 }
1239
1240 /* Applies to GCN. */
1241 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
1242
1243 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1244 * between frames, so the only thing that can enable separate DCC
1245 * with DRI2 is multiple slow clears within a frame.
1246 */
1247 rtex->ps_draw_ratio = 0;
1248
1249 if (rtex->is_depth) {
1250 if (sscreen->info.chip_class >= GFX9) {
1251 rtex->can_sample_z = true;
1252 rtex->can_sample_s = true;
1253 } else {
1254 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
1255 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
1256 }
1257
1258 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
1259 R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
1260 rtex->db_compatible = true;
1261
1262 if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
1263 r600_texture_allocate_htile(sscreen, rtex);
1264 }
1265 } else {
1266 if (base->nr_samples > 1) {
1267 if (!buf) {
1268 r600_texture_allocate_fmask(sscreen, rtex);
1269 r600_texture_allocate_cmask(sscreen, rtex);
1270 rtex->cmask_buffer = &rtex->resource;
1271 }
1272 if (!rtex->fmask.size || !rtex->cmask.size) {
1273 FREE(rtex);
1274 return NULL;
1275 }
1276 }
1277
1278 /* Shared textures must always set up DCC here.
1279 * If it's not present, it will be disabled by
1280 * apply_opaque_metadata later.
1281 */
1282 if (rtex->surface.dcc_size &&
1283 (buf || !(sscreen->debug_flags & DBG(NO_DCC))) &&
1284 !(rtex->surface.flags & RADEON_SURF_SCANOUT)) {
1285 /* Reserve space for the DCC buffer. */
1286 rtex->dcc_offset = align64(rtex->size, rtex->surface.dcc_alignment);
1287 rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
1288 }
1289 }
1290
1291 /* Now create the backing buffer. */
1292 if (!buf) {
1293 si_init_resource_fields(sscreen, resource, rtex->size,
1294 rtex->surface.surf_alignment);
1295
1296 if (!si_alloc_resource(sscreen, resource)) {
1297 FREE(rtex);
1298 return NULL;
1299 }
1300 } else {
1301 resource->buf = buf;
1302 resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf);
1303 resource->bo_size = buf->size;
1304 resource->bo_alignment = buf->alignment;
1305 resource->domains = sscreen->ws->buffer_get_initial_domain(resource->buf);
1306 if (resource->domains & RADEON_DOMAIN_VRAM)
1307 resource->vram_usage = buf->size;
1308 else if (resource->domains & RADEON_DOMAIN_GTT)
1309 resource->gart_usage = buf->size;
1310 }
1311
1312 if (rtex->cmask.size) {
1313 /* Initialize the cmask to 0xCC (= compressed state). */
1314 si_screen_clear_buffer(sscreen, &rtex->cmask_buffer->b.b,
1315 rtex->cmask.offset, rtex->cmask.size,
1316 0xCCCCCCCC);
1317 }
1318 if (rtex->htile_offset) {
1319 uint32_t clear_value = 0;
1320
1321 if (sscreen->info.chip_class >= GFX9 || rtex->tc_compatible_htile)
1322 clear_value = 0x0000030F;
1323
1324 si_screen_clear_buffer(sscreen, &rtex->resource.b.b,
1325 rtex->htile_offset,
1326 rtex->surface.htile_size,
1327 clear_value);
1328 }
1329
1330 /* Initialize DCC only if the texture is not being imported. */
1331 if (!buf && rtex->dcc_offset) {
1332 si_screen_clear_buffer(sscreen, &rtex->resource.b.b,
1333 rtex->dcc_offset,
1334 rtex->surface.dcc_size,
1335 0xFFFFFFFF);
1336 }
1337
1338 /* Initialize the CMASK base register value. */
1339 rtex->cmask.base_address_reg =
1340 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1341
1342 if (sscreen->debug_flags & DBG(VM)) {
1343 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1344 rtex->resource.gpu_address,
1345 rtex->resource.gpu_address + rtex->resource.buf->size,
1346 base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
1347 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
1348 }
1349
1350 if (sscreen->debug_flags & DBG(TEX)) {
1351 puts("Texture:");
1352 struct u_log_context log;
1353 u_log_context_init(&log);
1354 si_print_texture_info(sscreen, rtex, &log);
1355 u_log_new_page_print(&log, stdout);
1356 fflush(stdout);
1357 u_log_context_destroy(&log);
1358 }
1359
1360 return rtex;
1361 }
1362
1363 static enum radeon_surf_mode
r600_choose_tiling(struct si_screen * sscreen,const struct pipe_resource * templ)1364 r600_choose_tiling(struct si_screen *sscreen,
1365 const struct pipe_resource *templ)
1366 {
1367 const struct util_format_description *desc = util_format_description(templ->format);
1368 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1369 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1370 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1371
1372 /* MSAA resources must be 2D tiled. */
1373 if (templ->nr_samples > 1)
1374 return RADEON_SURF_MODE_2D;
1375
1376 /* Transfer resources should be linear. */
1377 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1378 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1379
1380 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1381 * which requires 2D tiling.
1382 */
1383 if (sscreen->info.chip_class == VI &&
1384 is_depth_stencil &&
1385 (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY))
1386 return RADEON_SURF_MODE_2D;
1387
1388 /* Handle common candidates for the linear mode.
1389 * Compressed textures and DB surfaces must always be tiled.
1390 */
1391 if (!force_tiling &&
1392 !is_depth_stencil &&
1393 !util_format_is_compressed(templ->format)) {
1394 if (sscreen->debug_flags & DBG(NO_TILING))
1395 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1396
1397 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1398 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1399 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1400
1401 /* Cursors are linear on SI.
1402 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1403 if (templ->bind & PIPE_BIND_CURSOR)
1404 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1405
1406 if (templ->bind & PIPE_BIND_LINEAR)
1407 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1408
1409 /* Textures with a very small height are recommended to be linear. */
1410 if (templ->target == PIPE_TEXTURE_1D ||
1411 templ->target == PIPE_TEXTURE_1D_ARRAY ||
1412 /* Only very thin and long 2D textures should benefit from
1413 * linear_aligned. */
1414 (templ->width0 > 8 && templ->height0 <= 2))
1415 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1416
1417 /* Textures likely to be mapped often. */
1418 if (templ->usage == PIPE_USAGE_STAGING ||
1419 templ->usage == PIPE_USAGE_STREAM)
1420 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1421 }
1422
1423 /* Make small textures 1D tiled. */
1424 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1425 (sscreen->debug_flags & DBG(NO_2D_TILING)))
1426 return RADEON_SURF_MODE_1D;
1427
1428 /* The allocator will switch to 1D if needed. */
1429 return RADEON_SURF_MODE_2D;
1430 }
1431
si_texture_create(struct pipe_screen * screen,const struct pipe_resource * templ)1432 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1433 const struct pipe_resource *templ)
1434 {
1435 struct si_screen *sscreen = (struct si_screen*)screen;
1436 struct radeon_surf surface = {0};
1437 bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1438 bool tc_compatible_htile =
1439 sscreen->info.chip_class >= VI &&
1440 (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
1441 !(sscreen->debug_flags & DBG(NO_HYPERZ)) &&
1442 !is_flushed_depth &&
1443 templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient with MSAA */
1444 util_format_is_depth_or_stencil(templ->format);
1445
1446 int r;
1447
1448 r = r600_init_surface(sscreen, &surface, templ,
1449 r600_choose_tiling(sscreen, templ), 0, 0,
1450 false, false, is_flushed_depth,
1451 tc_compatible_htile);
1452 if (r) {
1453 return NULL;
1454 }
1455
1456 return (struct pipe_resource *)
1457 r600_texture_create_object(screen, templ, NULL, &surface);
1458 }
1459
r600_texture_from_handle(struct pipe_screen * screen,const struct pipe_resource * templ,struct winsys_handle * whandle,unsigned usage)1460 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1461 const struct pipe_resource *templ,
1462 struct winsys_handle *whandle,
1463 unsigned usage)
1464 {
1465 struct si_screen *sscreen = (struct si_screen*)screen;
1466 struct pb_buffer *buf = NULL;
1467 unsigned stride = 0, offset = 0;
1468 enum radeon_surf_mode array_mode;
1469 struct radeon_surf surface = {};
1470 int r;
1471 struct radeon_bo_metadata metadata = {};
1472 struct r600_texture *rtex;
1473 bool is_scanout;
1474
1475 /* Support only 2D textures without mipmaps */
1476 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1477 templ->depth0 != 1 || templ->last_level != 0)
1478 return NULL;
1479
1480 buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, &stride, &offset);
1481 if (!buf)
1482 return NULL;
1483
1484 sscreen->ws->buffer_get_metadata(buf, &metadata);
1485 r600_surface_import_metadata(sscreen, &surface, &metadata,
1486 &array_mode, &is_scanout);
1487
1488 r = r600_init_surface(sscreen, &surface, templ, array_mode, stride,
1489 offset, true, is_scanout, false, false);
1490 if (r) {
1491 return NULL;
1492 }
1493
1494 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1495 if (!rtex)
1496 return NULL;
1497
1498 rtex->resource.b.is_shared = true;
1499 rtex->resource.external_usage = usage;
1500
1501 si_apply_opaque_metadata(sscreen, rtex, &metadata);
1502
1503 assert(rtex->surface.tile_swizzle == 0);
1504 return &rtex->resource.b.b;
1505 }
1506
si_init_flushed_depth_texture(struct pipe_context * ctx,struct pipe_resource * texture,struct r600_texture ** staging)1507 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1508 struct pipe_resource *texture,
1509 struct r600_texture **staging)
1510 {
1511 struct r600_texture *rtex = (struct r600_texture*)texture;
1512 struct pipe_resource resource;
1513 struct r600_texture **flushed_depth_texture = staging ?
1514 staging : &rtex->flushed_depth_texture;
1515 enum pipe_format pipe_format = texture->format;
1516
1517 if (!staging) {
1518 if (rtex->flushed_depth_texture)
1519 return true; /* it's ready */
1520
1521 if (!rtex->can_sample_z && rtex->can_sample_s) {
1522 switch (pipe_format) {
1523 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1524 /* Save memory by not allocating the S plane. */
1525 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1526 break;
1527 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1528 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1529 /* Save memory bandwidth by not copying the
1530 * stencil part during flush.
1531 *
1532 * This potentially increases memory bandwidth
1533 * if an application uses both Z and S texturing
1534 * simultaneously (a flushed Z24S8 texture
1535 * would be stored compactly), but how often
1536 * does that really happen?
1537 */
1538 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1539 break;
1540 default:;
1541 }
1542 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1543 assert(util_format_has_stencil(util_format_description(pipe_format)));
1544
1545 /* DB->CB copies to an 8bpp surface don't work. */
1546 pipe_format = PIPE_FORMAT_X24S8_UINT;
1547 }
1548 }
1549
1550 memset(&resource, 0, sizeof(resource));
1551 resource.target = texture->target;
1552 resource.format = pipe_format;
1553 resource.width0 = texture->width0;
1554 resource.height0 = texture->height0;
1555 resource.depth0 = texture->depth0;
1556 resource.array_size = texture->array_size;
1557 resource.last_level = texture->last_level;
1558 resource.nr_samples = texture->nr_samples;
1559 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1560 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1561 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1562
1563 if (staging)
1564 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1565
1566 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1567 if (*flushed_depth_texture == NULL) {
1568 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1569 return false;
1570 }
1571 return true;
1572 }
1573
1574 /**
1575 * Initialize the pipe_resource descriptor to be of the same size as the box,
1576 * which is supposed to hold a subregion of the texture "orig" at the given
1577 * mipmap level.
1578 */
r600_init_temp_resource_from_box(struct pipe_resource * res,struct pipe_resource * orig,const struct pipe_box * box,unsigned level,unsigned flags)1579 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1580 struct pipe_resource *orig,
1581 const struct pipe_box *box,
1582 unsigned level, unsigned flags)
1583 {
1584 memset(res, 0, sizeof(*res));
1585 res->format = orig->format;
1586 res->width0 = box->width;
1587 res->height0 = box->height;
1588 res->depth0 = 1;
1589 res->array_size = 1;
1590 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1591 res->flags = flags;
1592
1593 /* We must set the correct texture target and dimensions for a 3D box. */
1594 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1595 res->target = PIPE_TEXTURE_2D_ARRAY;
1596 res->array_size = box->depth;
1597 } else {
1598 res->target = PIPE_TEXTURE_2D;
1599 }
1600 }
1601
r600_can_invalidate_texture(struct si_screen * sscreen,struct r600_texture * rtex,unsigned transfer_usage,const struct pipe_box * box)1602 static bool r600_can_invalidate_texture(struct si_screen *sscreen,
1603 struct r600_texture *rtex,
1604 unsigned transfer_usage,
1605 const struct pipe_box *box)
1606 {
1607 return !rtex->resource.b.is_shared &&
1608 !(transfer_usage & PIPE_TRANSFER_READ) &&
1609 rtex->resource.b.b.last_level == 0 &&
1610 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1611 box->x, box->y, box->z,
1612 box->width, box->height,
1613 box->depth);
1614 }
1615
r600_texture_invalidate_storage(struct r600_common_context * rctx,struct r600_texture * rtex)1616 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1617 struct r600_texture *rtex)
1618 {
1619 struct si_screen *sscreen = rctx->screen;
1620
1621 /* There is no point in discarding depth and tiled buffers. */
1622 assert(!rtex->is_depth);
1623 assert(rtex->surface.is_linear);
1624
1625 /* Reallocate the buffer in the same pipe_resource. */
1626 si_alloc_resource(sscreen, &rtex->resource);
1627
1628 /* Initialize the CMASK base address (needed even without CMASK). */
1629 rtex->cmask.base_address_reg =
1630 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1631
1632 p_atomic_inc(&sscreen->dirty_tex_counter);
1633
1634 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1635 }
1636
r600_texture_transfer_map(struct pipe_context * ctx,struct pipe_resource * texture,unsigned level,unsigned usage,const struct pipe_box * box,struct pipe_transfer ** ptransfer)1637 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1638 struct pipe_resource *texture,
1639 unsigned level,
1640 unsigned usage,
1641 const struct pipe_box *box,
1642 struct pipe_transfer **ptransfer)
1643 {
1644 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1645 struct r600_texture *rtex = (struct r600_texture*)texture;
1646 struct r600_transfer *trans;
1647 struct r600_resource *buf;
1648 unsigned offset = 0;
1649 char *map;
1650 bool use_staging_texture = false;
1651
1652 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1653 assert(box->width && box->height && box->depth);
1654
1655 /* Depth textures use staging unconditionally. */
1656 if (!rtex->is_depth) {
1657 /* Degrade the tile mode if we get too many transfers on APUs.
1658 * On dGPUs, the staging texture is always faster.
1659 * Only count uploads that are at least 4x4 pixels large.
1660 */
1661 if (!rctx->screen->info.has_dedicated_vram &&
1662 level == 0 &&
1663 box->width >= 4 && box->height >= 4 &&
1664 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1665 bool can_invalidate =
1666 r600_can_invalidate_texture(rctx->screen, rtex,
1667 usage, box);
1668
1669 r600_reallocate_texture_inplace(rctx, rtex,
1670 PIPE_BIND_LINEAR,
1671 can_invalidate);
1672 }
1673
1674 /* Tiled textures need to be converted into a linear texture for CPU
1675 * access. The staging texture is always linear and is placed in GART.
1676 *
1677 * Reading from VRAM or GTT WC is slow, always use the staging
1678 * texture in this case.
1679 *
1680 * Use the staging texture for uploads if the underlying BO
1681 * is busy.
1682 */
1683 if (!rtex->surface.is_linear)
1684 use_staging_texture = true;
1685 else if (usage & PIPE_TRANSFER_READ)
1686 use_staging_texture =
1687 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1688 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1689 /* Write & linear only: */
1690 else if (si_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1691 RADEON_USAGE_READWRITE) ||
1692 !rctx->ws->buffer_wait(rtex->resource.buf, 0,
1693 RADEON_USAGE_READWRITE)) {
1694 /* It's busy. */
1695 if (r600_can_invalidate_texture(rctx->screen, rtex,
1696 usage, box))
1697 r600_texture_invalidate_storage(rctx, rtex);
1698 else
1699 use_staging_texture = true;
1700 }
1701 }
1702
1703 trans = CALLOC_STRUCT(r600_transfer);
1704 if (!trans)
1705 return NULL;
1706 pipe_resource_reference(&trans->b.b.resource, texture);
1707 trans->b.b.level = level;
1708 trans->b.b.usage = usage;
1709 trans->b.b.box = *box;
1710
1711 if (rtex->is_depth) {
1712 struct r600_texture *staging_depth;
1713
1714 if (rtex->resource.b.b.nr_samples > 1) {
1715 /* MSAA depth buffers need to be converted to single sample buffers.
1716 *
1717 * Mapping MSAA depth buffers can occur if ReadPixels is called
1718 * with a multisample GLX visual.
1719 *
1720 * First downsample the depth buffer to a temporary texture,
1721 * then decompress the temporary one to staging.
1722 *
1723 * Only the region being mapped is transfered.
1724 */
1725 struct pipe_resource resource;
1726
1727 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1728
1729 if (!si_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1730 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1731 FREE(trans);
1732 return NULL;
1733 }
1734
1735 if (usage & PIPE_TRANSFER_READ) {
1736 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1737 if (!temp) {
1738 R600_ERR("failed to create a temporary depth texture\n");
1739 FREE(trans);
1740 return NULL;
1741 }
1742
1743 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1744 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1745 0, 0, 0, box->depth, 0, 0);
1746 pipe_resource_reference(&temp, NULL);
1747 }
1748
1749 /* Just get the strides. */
1750 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1751 &trans->b.b.stride,
1752 &trans->b.b.layer_stride);
1753 } else {
1754 /* XXX: only readback the rectangle which is being mapped? */
1755 /* XXX: when discard is true, no need to read back from depth texture */
1756 if (!si_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1757 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1758 FREE(trans);
1759 return NULL;
1760 }
1761
1762 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1763 level, level,
1764 box->z, box->z + box->depth - 1,
1765 0, 0);
1766
1767 offset = r600_texture_get_offset(rctx->screen, staging_depth,
1768 level, box,
1769 &trans->b.b.stride,
1770 &trans->b.b.layer_stride);
1771 }
1772
1773 trans->staging = (struct r600_resource*)staging_depth;
1774 buf = trans->staging;
1775 } else if (use_staging_texture) {
1776 struct pipe_resource resource;
1777 struct r600_texture *staging;
1778
1779 r600_init_temp_resource_from_box(&resource, texture, box, level,
1780 R600_RESOURCE_FLAG_TRANSFER);
1781 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1782 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1783
1784 /* Create the temporary texture. */
1785 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1786 if (!staging) {
1787 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1788 FREE(trans);
1789 return NULL;
1790 }
1791 trans->staging = &staging->resource;
1792
1793 /* Just get the strides. */
1794 r600_texture_get_offset(rctx->screen, staging, 0, NULL,
1795 &trans->b.b.stride,
1796 &trans->b.b.layer_stride);
1797
1798 if (usage & PIPE_TRANSFER_READ)
1799 r600_copy_to_staging_texture(ctx, trans);
1800 else
1801 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1802
1803 buf = trans->staging;
1804 } else {
1805 /* the resource is mapped directly */
1806 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1807 &trans->b.b.stride,
1808 &trans->b.b.layer_stride);
1809 buf = &rtex->resource;
1810 }
1811
1812 if (!(map = si_buffer_map_sync_with_rings(rctx, buf, usage))) {
1813 r600_resource_reference(&trans->staging, NULL);
1814 FREE(trans);
1815 return NULL;
1816 }
1817
1818 *ptransfer = &trans->b.b;
1819 return map + offset;
1820 }
1821
r600_texture_transfer_unmap(struct pipe_context * ctx,struct pipe_transfer * transfer)1822 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1823 struct pipe_transfer* transfer)
1824 {
1825 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1826 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1827 struct pipe_resource *texture = transfer->resource;
1828 struct r600_texture *rtex = (struct r600_texture*)texture;
1829
1830 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1831 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1832 ctx->resource_copy_region(ctx, texture, transfer->level,
1833 transfer->box.x, transfer->box.y, transfer->box.z,
1834 &rtransfer->staging->b.b, transfer->level,
1835 &transfer->box);
1836 } else {
1837 r600_copy_from_staging_texture(ctx, rtransfer);
1838 }
1839 }
1840
1841 if (rtransfer->staging) {
1842 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1843 r600_resource_reference(&rtransfer->staging, NULL);
1844 }
1845
1846 /* Heuristic for {upload, draw, upload, draw, ..}:
1847 *
1848 * Flush the gfx IB if we've allocated too much texture storage.
1849 *
1850 * The idea is that we don't want to build IBs that use too much
1851 * memory and put pressure on the kernel memory manager and we also
1852 * want to make temporary and invalidated buffers go idle ASAP to
1853 * decrease the total memory usage or make them reusable. The memory
1854 * usage will be slightly higher than given here because of the buffer
1855 * cache in the winsys.
1856 *
1857 * The result is that the kernel memory manager is never a bottleneck.
1858 */
1859 if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
1860 rctx->gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1861 rctx->num_alloc_tex_transfer_bytes = 0;
1862 }
1863
1864 pipe_resource_reference(&transfer->resource, NULL);
1865 FREE(transfer);
1866 }
1867
1868 static const struct u_resource_vtbl r600_texture_vtbl =
1869 {
1870 NULL, /* get_handle */
1871 r600_texture_destroy, /* resource_destroy */
1872 r600_texture_transfer_map, /* transfer_map */
1873 u_default_transfer_flush_region, /* transfer_flush_region */
1874 r600_texture_transfer_unmap, /* transfer_unmap */
1875 };
1876
1877 /* DCC channel type categories within which formats can be reinterpreted
1878 * while keeping the same DCC encoding. The swizzle must also match. */
1879 enum dcc_channel_type {
1880 dcc_channel_float32,
1881 dcc_channel_uint32,
1882 dcc_channel_sint32,
1883 dcc_channel_float16,
1884 dcc_channel_uint16,
1885 dcc_channel_sint16,
1886 dcc_channel_uint_10_10_10_2,
1887 dcc_channel_uint8,
1888 dcc_channel_sint8,
1889 dcc_channel_incompatible,
1890 };
1891
1892 /* Return the type of DCC encoding. */
1893 static enum dcc_channel_type
vi_get_dcc_channel_type(const struct util_format_description * desc)1894 vi_get_dcc_channel_type(const struct util_format_description *desc)
1895 {
1896 int i;
1897
1898 /* Find the first non-void channel. */
1899 for (i = 0; i < desc->nr_channels; i++)
1900 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID)
1901 break;
1902 if (i == desc->nr_channels)
1903 return dcc_channel_incompatible;
1904
1905 switch (desc->channel[i].size) {
1906 case 32:
1907 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)
1908 return dcc_channel_float32;
1909 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED)
1910 return dcc_channel_uint32;
1911 return dcc_channel_sint32;
1912 case 16:
1913 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)
1914 return dcc_channel_float16;
1915 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED)
1916 return dcc_channel_uint16;
1917 return dcc_channel_sint16;
1918 case 10:
1919 return dcc_channel_uint_10_10_10_2;
1920 case 8:
1921 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED)
1922 return dcc_channel_uint8;
1923 return dcc_channel_sint8;
1924 default:
1925 return dcc_channel_incompatible;
1926 }
1927 }
1928
1929 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
vi_dcc_formats_compatible(enum pipe_format format1,enum pipe_format format2)1930 bool vi_dcc_formats_compatible(enum pipe_format format1,
1931 enum pipe_format format2)
1932 {
1933 const struct util_format_description *desc1, *desc2;
1934 enum dcc_channel_type type1, type2;
1935 int i;
1936
1937 if (format1 == format2)
1938 return true;
1939
1940 desc1 = util_format_description(format1);
1941 desc2 = util_format_description(format2);
1942
1943 if (desc1->nr_channels != desc2->nr_channels)
1944 return false;
1945
1946 /* Swizzles must be the same. */
1947 for (i = 0; i < desc1->nr_channels; i++)
1948 if (desc1->swizzle[i] <= PIPE_SWIZZLE_W &&
1949 desc2->swizzle[i] <= PIPE_SWIZZLE_W &&
1950 desc1->swizzle[i] != desc2->swizzle[i])
1951 return false;
1952
1953 type1 = vi_get_dcc_channel_type(desc1);
1954 type2 = vi_get_dcc_channel_type(desc2);
1955
1956 return type1 != dcc_channel_incompatible &&
1957 type2 != dcc_channel_incompatible &&
1958 type1 == type2;
1959 }
1960
vi_dcc_formats_are_incompatible(struct pipe_resource * tex,unsigned level,enum pipe_format view_format)1961 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1962 unsigned level,
1963 enum pipe_format view_format)
1964 {
1965 struct r600_texture *rtex = (struct r600_texture *)tex;
1966
1967 return vi_dcc_enabled(rtex, level) &&
1968 !vi_dcc_formats_compatible(tex->format, view_format);
1969 }
1970
1971 /* This can't be merged with the above function, because
1972 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
vi_disable_dcc_if_incompatible_format(struct r600_common_context * rctx,struct pipe_resource * tex,unsigned level,enum pipe_format view_format)1973 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
1974 struct pipe_resource *tex,
1975 unsigned level,
1976 enum pipe_format view_format)
1977 {
1978 struct r600_texture *rtex = (struct r600_texture *)tex;
1979
1980 if (vi_dcc_formats_are_incompatible(tex, level, view_format))
1981 if (!si_texture_disable_dcc(rctx, (struct r600_texture*)tex))
1982 rctx->decompress_dcc(&rctx->b, rtex);
1983 }
1984
si_create_surface_custom(struct pipe_context * pipe,struct pipe_resource * texture,const struct pipe_surface * templ,unsigned width0,unsigned height0,unsigned width,unsigned height)1985 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1986 struct pipe_resource *texture,
1987 const struct pipe_surface *templ,
1988 unsigned width0, unsigned height0,
1989 unsigned width, unsigned height)
1990 {
1991 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1992
1993 if (!surface)
1994 return NULL;
1995
1996 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1997 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1998
1999 pipe_reference_init(&surface->base.reference, 1);
2000 pipe_resource_reference(&surface->base.texture, texture);
2001 surface->base.context = pipe;
2002 surface->base.format = templ->format;
2003 surface->base.width = width;
2004 surface->base.height = height;
2005 surface->base.u = templ->u;
2006
2007 surface->width0 = width0;
2008 surface->height0 = height0;
2009
2010 surface->dcc_incompatible =
2011 texture->target != PIPE_BUFFER &&
2012 vi_dcc_formats_are_incompatible(texture, templ->u.tex.level,
2013 templ->format);
2014 return &surface->base;
2015 }
2016
r600_create_surface(struct pipe_context * pipe,struct pipe_resource * tex,const struct pipe_surface * templ)2017 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
2018 struct pipe_resource *tex,
2019 const struct pipe_surface *templ)
2020 {
2021 unsigned level = templ->u.tex.level;
2022 unsigned width = u_minify(tex->width0, level);
2023 unsigned height = u_minify(tex->height0, level);
2024 unsigned width0 = tex->width0;
2025 unsigned height0 = tex->height0;
2026
2027 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
2028 const struct util_format_description *tex_desc
2029 = util_format_description(tex->format);
2030 const struct util_format_description *templ_desc
2031 = util_format_description(templ->format);
2032
2033 assert(tex_desc->block.bits == templ_desc->block.bits);
2034
2035 /* Adjust size of surface if and only if the block width or
2036 * height is changed. */
2037 if (tex_desc->block.width != templ_desc->block.width ||
2038 tex_desc->block.height != templ_desc->block.height) {
2039 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
2040 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
2041
2042 width = nblks_x * templ_desc->block.width;
2043 height = nblks_y * templ_desc->block.height;
2044
2045 width0 = util_format_get_nblocksx(tex->format, width0);
2046 height0 = util_format_get_nblocksy(tex->format, height0);
2047 }
2048 }
2049
2050 return si_create_surface_custom(pipe, tex, templ,
2051 width0, height0,
2052 width, height);
2053 }
2054
r600_surface_destroy(struct pipe_context * pipe,struct pipe_surface * surface)2055 static void r600_surface_destroy(struct pipe_context *pipe,
2056 struct pipe_surface *surface)
2057 {
2058 pipe_resource_reference(&surface->texture, NULL);
2059 FREE(surface);
2060 }
2061
si_translate_colorswap(enum pipe_format format,bool do_endian_swap)2062 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap)
2063 {
2064 const struct util_format_description *desc = util_format_description(format);
2065
2066 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2067
2068 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2069 return V_028C70_SWAP_STD;
2070
2071 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
2072 return ~0U;
2073
2074 switch (desc->nr_channels) {
2075 case 1:
2076 if (HAS_SWIZZLE(0,X))
2077 return V_028C70_SWAP_STD; /* X___ */
2078 else if (HAS_SWIZZLE(3,X))
2079 return V_028C70_SWAP_ALT_REV; /* ___X */
2080 break;
2081 case 2:
2082 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
2083 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
2084 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
2085 return V_028C70_SWAP_STD; /* XY__ */
2086 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
2087 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
2088 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
2089 /* YX__ */
2090 return (do_endian_swap ? V_028C70_SWAP_STD : V_028C70_SWAP_STD_REV);
2091 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
2092 return V_028C70_SWAP_ALT; /* X__Y */
2093 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
2094 return V_028C70_SWAP_ALT_REV; /* Y__X */
2095 break;
2096 case 3:
2097 if (HAS_SWIZZLE(0,X))
2098 return (do_endian_swap ? V_028C70_SWAP_STD_REV : V_028C70_SWAP_STD);
2099 else if (HAS_SWIZZLE(0,Z))
2100 return V_028C70_SWAP_STD_REV; /* ZYX */
2101 break;
2102 case 4:
2103 /* check the middle channels, the 1st and 4th channel can be NONE */
2104 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
2105 return V_028C70_SWAP_STD; /* XYZW */
2106 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
2107 return V_028C70_SWAP_STD_REV; /* WZYX */
2108 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
2109 return V_028C70_SWAP_ALT; /* ZYXW */
2110 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
2111 /* YZWX */
2112 if (desc->is_array)
2113 return V_028C70_SWAP_ALT_REV;
2114 else
2115 return (do_endian_swap ? V_028C70_SWAP_ALT : V_028C70_SWAP_ALT_REV);
2116 }
2117 break;
2118 }
2119 return ~0U;
2120 }
2121
2122 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2123
vi_dcc_clean_up_context_slot(struct r600_common_context * rctx,int slot)2124 static void vi_dcc_clean_up_context_slot(struct r600_common_context *rctx,
2125 int slot)
2126 {
2127 int i;
2128
2129 if (rctx->dcc_stats[slot].query_active)
2130 vi_separate_dcc_stop_query(&rctx->b,
2131 rctx->dcc_stats[slot].tex);
2132
2133 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats[slot].ps_stats); i++)
2134 if (rctx->dcc_stats[slot].ps_stats[i]) {
2135 rctx->b.destroy_query(&rctx->b,
2136 rctx->dcc_stats[slot].ps_stats[i]);
2137 rctx->dcc_stats[slot].ps_stats[i] = NULL;
2138 }
2139
2140 r600_texture_reference(&rctx->dcc_stats[slot].tex, NULL);
2141 }
2142
2143 /**
2144 * Return the per-context slot where DCC statistics queries for the texture live.
2145 */
vi_get_context_dcc_stats_index(struct r600_common_context * rctx,struct r600_texture * tex)2146 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context *rctx,
2147 struct r600_texture *tex)
2148 {
2149 int i, empty_slot = -1;
2150
2151 /* Remove zombie textures (textures kept alive by this array only). */
2152 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++)
2153 if (rctx->dcc_stats[i].tex &&
2154 rctx->dcc_stats[i].tex->resource.b.b.reference.count == 1)
2155 vi_dcc_clean_up_context_slot(rctx, i);
2156
2157 /* Find the texture. */
2158 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
2159 /* Return if found. */
2160 if (rctx->dcc_stats[i].tex == tex) {
2161 rctx->dcc_stats[i].last_use_timestamp = os_time_get();
2162 return i;
2163 }
2164
2165 /* Record the first seen empty slot. */
2166 if (empty_slot == -1 && !rctx->dcc_stats[i].tex)
2167 empty_slot = i;
2168 }
2169
2170 /* Not found. Remove the oldest member to make space in the array. */
2171 if (empty_slot == -1) {
2172 int oldest_slot = 0;
2173
2174 /* Find the oldest slot. */
2175 for (i = 1; i < ARRAY_SIZE(rctx->dcc_stats); i++)
2176 if (rctx->dcc_stats[oldest_slot].last_use_timestamp >
2177 rctx->dcc_stats[i].last_use_timestamp)
2178 oldest_slot = i;
2179
2180 /* Clean up the oldest slot. */
2181 vi_dcc_clean_up_context_slot(rctx, oldest_slot);
2182 empty_slot = oldest_slot;
2183 }
2184
2185 /* Add the texture to the new slot. */
2186 r600_texture_reference(&rctx->dcc_stats[empty_slot].tex, tex);
2187 rctx->dcc_stats[empty_slot].last_use_timestamp = os_time_get();
2188 return empty_slot;
2189 }
2190
2191 static struct pipe_query *
vi_create_resuming_pipestats_query(struct pipe_context * ctx)2192 vi_create_resuming_pipestats_query(struct pipe_context *ctx)
2193 {
2194 struct r600_query_hw *query = (struct r600_query_hw*)
2195 ctx->create_query(ctx, PIPE_QUERY_PIPELINE_STATISTICS, 0);
2196
2197 query->flags |= R600_QUERY_HW_FLAG_BEGIN_RESUMES;
2198 return (struct pipe_query*)query;
2199 }
2200
2201 /**
2202 * Called when binding a color buffer.
2203 */
vi_separate_dcc_start_query(struct pipe_context * ctx,struct r600_texture * tex)2204 void vi_separate_dcc_start_query(struct pipe_context *ctx,
2205 struct r600_texture *tex)
2206 {
2207 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
2208 unsigned i = vi_get_context_dcc_stats_index(rctx, tex);
2209
2210 assert(!rctx->dcc_stats[i].query_active);
2211
2212 if (!rctx->dcc_stats[i].ps_stats[0])
2213 rctx->dcc_stats[i].ps_stats[0] = vi_create_resuming_pipestats_query(ctx);
2214
2215 /* begin or resume the query */
2216 ctx->begin_query(ctx, rctx->dcc_stats[i].ps_stats[0]);
2217 rctx->dcc_stats[i].query_active = true;
2218 }
2219
2220 /**
2221 * Called when unbinding a color buffer.
2222 */
vi_separate_dcc_stop_query(struct pipe_context * ctx,struct r600_texture * tex)2223 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
2224 struct r600_texture *tex)
2225 {
2226 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
2227 unsigned i = vi_get_context_dcc_stats_index(rctx, tex);
2228
2229 assert(rctx->dcc_stats[i].query_active);
2230 assert(rctx->dcc_stats[i].ps_stats[0]);
2231
2232 /* pause or end the query */
2233 ctx->end_query(ctx, rctx->dcc_stats[i].ps_stats[0]);
2234 rctx->dcc_stats[i].query_active = false;
2235 }
2236
vi_should_enable_separate_dcc(struct r600_texture * tex)2237 static bool vi_should_enable_separate_dcc(struct r600_texture *tex)
2238 {
2239 /* The minimum number of fullscreen draws per frame that is required
2240 * to enable DCC. */
2241 return tex->ps_draw_ratio + tex->num_slow_clears >= 5;
2242 }
2243
2244 /* Called by fast clear. */
vi_separate_dcc_try_enable(struct r600_common_context * rctx,struct r600_texture * tex)2245 void vi_separate_dcc_try_enable(struct r600_common_context *rctx,
2246 struct r600_texture *tex)
2247 {
2248 /* The intent is to use this with shared displayable back buffers,
2249 * but it's not strictly limited only to them.
2250 */
2251 if (!tex->resource.b.is_shared ||
2252 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) ||
2253 tex->resource.b.b.target != PIPE_TEXTURE_2D ||
2254 tex->resource.b.b.last_level > 0 ||
2255 !tex->surface.dcc_size)
2256 return;
2257
2258 if (tex->dcc_offset)
2259 return; /* already enabled */
2260
2261 /* Enable the DCC stat gathering. */
2262 if (!tex->dcc_gather_statistics) {
2263 tex->dcc_gather_statistics = true;
2264 vi_separate_dcc_start_query(&rctx->b, tex);
2265 }
2266
2267 if (!vi_should_enable_separate_dcc(tex))
2268 return; /* stats show that DCC decompression is too expensive */
2269
2270 assert(tex->surface.num_dcc_levels);
2271 assert(!tex->dcc_separate_buffer);
2272
2273 r600_texture_discard_cmask(rctx->screen, tex);
2274
2275 /* Get a DCC buffer. */
2276 if (tex->last_dcc_separate_buffer) {
2277 assert(tex->dcc_gather_statistics);
2278 assert(!tex->dcc_separate_buffer);
2279 tex->dcc_separate_buffer = tex->last_dcc_separate_buffer;
2280 tex->last_dcc_separate_buffer = NULL;
2281 } else {
2282 tex->dcc_separate_buffer = (struct r600_resource*)
2283 si_aligned_buffer_create(rctx->b.screen,
2284 R600_RESOURCE_FLAG_UNMAPPABLE,
2285 PIPE_USAGE_DEFAULT,
2286 tex->surface.dcc_size,
2287 tex->surface.dcc_alignment);
2288 if (!tex->dcc_separate_buffer)
2289 return;
2290 }
2291
2292 /* dcc_offset is the absolute GPUVM address. */
2293 tex->dcc_offset = tex->dcc_separate_buffer->gpu_address;
2294
2295 /* no need to flag anything since this is called by fast clear that
2296 * flags framebuffer state
2297 */
2298 }
2299
2300 /**
2301 * Called by pipe_context::flush_resource, the place where DCC decompression
2302 * takes place.
2303 */
vi_separate_dcc_process_and_reset_stats(struct pipe_context * ctx,struct r600_texture * tex)2304 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
2305 struct r600_texture *tex)
2306 {
2307 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
2308 struct pipe_query *tmp;
2309 unsigned i = vi_get_context_dcc_stats_index(rctx, tex);
2310 bool query_active = rctx->dcc_stats[i].query_active;
2311 bool disable = false;
2312
2313 if (rctx->dcc_stats[i].ps_stats[2]) {
2314 union pipe_query_result result;
2315
2316 /* Read the results. */
2317 ctx->get_query_result(ctx, rctx->dcc_stats[i].ps_stats[2],
2318 true, &result);
2319 si_query_hw_reset_buffers(rctx,
2320 (struct r600_query_hw*)
2321 rctx->dcc_stats[i].ps_stats[2]);
2322
2323 /* Compute the approximate number of fullscreen draws. */
2324 tex->ps_draw_ratio =
2325 result.pipeline_statistics.ps_invocations /
2326 (tex->resource.b.b.width0 * tex->resource.b.b.height0);
2327 rctx->last_tex_ps_draw_ratio = tex->ps_draw_ratio;
2328
2329 disable = tex->dcc_separate_buffer &&
2330 !vi_should_enable_separate_dcc(tex);
2331 }
2332
2333 tex->num_slow_clears = 0;
2334
2335 /* stop the statistics query for ps_stats[0] */
2336 if (query_active)
2337 vi_separate_dcc_stop_query(ctx, tex);
2338
2339 /* Move the queries in the queue by one. */
2340 tmp = rctx->dcc_stats[i].ps_stats[2];
2341 rctx->dcc_stats[i].ps_stats[2] = rctx->dcc_stats[i].ps_stats[1];
2342 rctx->dcc_stats[i].ps_stats[1] = rctx->dcc_stats[i].ps_stats[0];
2343 rctx->dcc_stats[i].ps_stats[0] = tmp;
2344
2345 /* create and start a new query as ps_stats[0] */
2346 if (query_active)
2347 vi_separate_dcc_start_query(ctx, tex);
2348
2349 if (disable) {
2350 assert(!tex->last_dcc_separate_buffer);
2351 tex->last_dcc_separate_buffer = tex->dcc_separate_buffer;
2352 tex->dcc_separate_buffer = NULL;
2353 tex->dcc_offset = 0;
2354 /* no need to flag anything since this is called after
2355 * decompression that re-sets framebuffer state
2356 */
2357 }
2358 }
2359
2360 static struct pipe_memory_object *
r600_memobj_from_handle(struct pipe_screen * screen,struct winsys_handle * whandle,bool dedicated)2361 r600_memobj_from_handle(struct pipe_screen *screen,
2362 struct winsys_handle *whandle,
2363 bool dedicated)
2364 {
2365 struct si_screen *sscreen = (struct si_screen*)screen;
2366 struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
2367 struct pb_buffer *buf = NULL;
2368 uint32_t stride, offset;
2369
2370 if (!memobj)
2371 return NULL;
2372
2373 buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
2374 &stride, &offset);
2375 if (!buf) {
2376 free(memobj);
2377 return NULL;
2378 }
2379
2380 memobj->b.dedicated = dedicated;
2381 memobj->buf = buf;
2382 memobj->stride = stride;
2383 memobj->offset = offset;
2384
2385 return (struct pipe_memory_object *)memobj;
2386
2387 }
2388
2389 static void
r600_memobj_destroy(struct pipe_screen * screen,struct pipe_memory_object * _memobj)2390 r600_memobj_destroy(struct pipe_screen *screen,
2391 struct pipe_memory_object *_memobj)
2392 {
2393 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
2394
2395 pb_reference(&memobj->buf, NULL);
2396 free(memobj);
2397 }
2398
2399 static struct pipe_resource *
r600_texture_from_memobj(struct pipe_screen * screen,const struct pipe_resource * templ,struct pipe_memory_object * _memobj,uint64_t offset)2400 r600_texture_from_memobj(struct pipe_screen *screen,
2401 const struct pipe_resource *templ,
2402 struct pipe_memory_object *_memobj,
2403 uint64_t offset)
2404 {
2405 int r;
2406 struct si_screen *sscreen = (struct si_screen*)screen;
2407 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
2408 struct r600_texture *rtex;
2409 struct radeon_surf surface = {};
2410 struct radeon_bo_metadata metadata = {};
2411 enum radeon_surf_mode array_mode;
2412 bool is_scanout;
2413 struct pb_buffer *buf = NULL;
2414
2415 if (memobj->b.dedicated) {
2416 sscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
2417 r600_surface_import_metadata(sscreen, &surface, &metadata,
2418 &array_mode, &is_scanout);
2419 } else {
2420 /**
2421 * The bo metadata is unset for un-dedicated images. So we fall
2422 * back to linear. See answer to question 5 of the
2423 * VK_KHX_external_memory spec for some details.
2424 *
2425 * It is possible that this case isn't going to work if the
2426 * surface pitch isn't correctly aligned by default.
2427 *
2428 * In order to support it correctly we require multi-image
2429 * metadata to be syncrhonized between radv and radeonsi. The
2430 * semantics of associating multiple image metadata to a memory
2431 * object on the vulkan export side are not concretely defined
2432 * either.
2433 *
2434 * All the use cases we are aware of at the moment for memory
2435 * objects use dedicated allocations. So lets keep the initial
2436 * implementation simple.
2437 *
2438 * A possible alternative is to attempt to reconstruct the
2439 * tiling information when the TexParameter TEXTURE_TILING_EXT
2440 * is set.
2441 */
2442 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
2443 is_scanout = false;
2444
2445 }
2446
2447 r = r600_init_surface(sscreen, &surface, templ,
2448 array_mode, memobj->stride,
2449 offset, true, is_scanout,
2450 false, false);
2451 if (r)
2452 return NULL;
2453
2454 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
2455 if (!rtex)
2456 return NULL;
2457
2458 /* r600_texture_create_object doesn't increment refcount of
2459 * memobj->buf, so increment it here.
2460 */
2461 pb_reference(&buf, memobj->buf);
2462
2463 rtex->resource.b.is_shared = true;
2464 rtex->resource.external_usage = PIPE_HANDLE_USAGE_READ_WRITE;
2465
2466 si_apply_opaque_metadata(sscreen, rtex, &metadata);
2467
2468 return &rtex->resource.b.b;
2469 }
2470
si_check_resource_capability(struct pipe_screen * screen,struct pipe_resource * resource,unsigned bind)2471 static bool si_check_resource_capability(struct pipe_screen *screen,
2472 struct pipe_resource *resource,
2473 unsigned bind)
2474 {
2475 struct r600_texture *tex = (struct r600_texture*)resource;
2476
2477 /* Buffers only support the linear flag. */
2478 if (resource->target == PIPE_BUFFER)
2479 return (bind & ~PIPE_BIND_LINEAR) == 0;
2480
2481 if (bind & PIPE_BIND_LINEAR && !tex->surface.is_linear)
2482 return false;
2483
2484 if (bind & PIPE_BIND_SCANOUT && !tex->surface.is_displayable)
2485 return false;
2486
2487 /* TODO: PIPE_BIND_CURSOR - do we care? */
2488 return true;
2489 }
2490
si_init_screen_texture_functions(struct si_screen * sscreen)2491 void si_init_screen_texture_functions(struct si_screen *sscreen)
2492 {
2493 sscreen->b.resource_from_handle = r600_texture_from_handle;
2494 sscreen->b.resource_get_handle = r600_texture_get_handle;
2495 sscreen->b.resource_from_memobj = r600_texture_from_memobj;
2496 sscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
2497 sscreen->b.memobj_destroy = r600_memobj_destroy;
2498 sscreen->b.check_resource_capability = si_check_resource_capability;
2499 }
2500
si_init_context_texture_functions(struct r600_common_context * rctx)2501 void si_init_context_texture_functions(struct r600_common_context *rctx)
2502 {
2503 rctx->b.create_surface = r600_create_surface;
2504 rctx->b.surface_destroy = r600_surface_destroy;
2505 }
2506