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1 /*
2  * Copyright 2013 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  */
23 
24 #include "si_pipe.h"
25 #include "si_state.h"
26 #include "sid.h"
27 #include "radeon/r600_cs.h"
28 
29 #include "util/u_memory.h"
30 
31 static void si_set_streamout_enable(struct si_context *sctx, bool enable);
32 
si_so_target_reference(struct si_streamout_target ** dst,struct pipe_stream_output_target * src)33 static inline void si_so_target_reference(struct si_streamout_target **dst,
34 					  struct pipe_stream_output_target *src)
35 {
36 	pipe_so_target_reference((struct pipe_stream_output_target**)dst, src);
37 }
38 
39 static struct pipe_stream_output_target *
si_create_so_target(struct pipe_context * ctx,struct pipe_resource * buffer,unsigned buffer_offset,unsigned buffer_size)40 si_create_so_target(struct pipe_context *ctx,
41 		    struct pipe_resource *buffer,
42 		    unsigned buffer_offset,
43 		    unsigned buffer_size)
44 {
45 	struct si_context *sctx = (struct si_context *)ctx;
46 	struct si_streamout_target *t;
47 	struct r600_resource *rbuffer = (struct r600_resource*)buffer;
48 
49 	t = CALLOC_STRUCT(si_streamout_target);
50 	if (!t) {
51 		return NULL;
52 	}
53 
54 	u_suballocator_alloc(sctx->b.allocator_zeroed_memory, 4, 4,
55 			     &t->buf_filled_size_offset,
56 			     (struct pipe_resource**)&t->buf_filled_size);
57 	if (!t->buf_filled_size) {
58 		FREE(t);
59 		return NULL;
60 	}
61 
62 	t->b.reference.count = 1;
63 	t->b.context = ctx;
64 	pipe_resource_reference(&t->b.buffer, buffer);
65 	t->b.buffer_offset = buffer_offset;
66 	t->b.buffer_size = buffer_size;
67 
68 	util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
69 		       buffer_offset + buffer_size);
70 	return &t->b;
71 }
72 
si_so_target_destroy(struct pipe_context * ctx,struct pipe_stream_output_target * target)73 static void si_so_target_destroy(struct pipe_context *ctx,
74 				 struct pipe_stream_output_target *target)
75 {
76 	struct si_streamout_target *t = (struct si_streamout_target*)target;
77 	pipe_resource_reference(&t->b.buffer, NULL);
78 	r600_resource_reference(&t->buf_filled_size, NULL);
79 	FREE(t);
80 }
81 
si_streamout_buffers_dirty(struct si_context * sctx)82 void si_streamout_buffers_dirty(struct si_context *sctx)
83 {
84 	if (!sctx->streamout.enabled_mask)
85 		return;
86 
87 	si_mark_atom_dirty(sctx, &sctx->streamout.begin_atom);
88 	si_set_streamout_enable(sctx, true);
89 }
90 
si_set_streamout_targets(struct pipe_context * ctx,unsigned num_targets,struct pipe_stream_output_target ** targets,const unsigned * offsets)91 static void si_set_streamout_targets(struct pipe_context *ctx,
92 				     unsigned num_targets,
93 				     struct pipe_stream_output_target **targets,
94 				     const unsigned *offsets)
95 {
96 	struct si_context *sctx = (struct si_context *)ctx;
97 	struct si_buffer_resources *buffers = &sctx->rw_buffers;
98 	struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
99 	unsigned old_num_targets = sctx->streamout.num_targets;
100 	unsigned i, bufidx;
101 
102 	/* We are going to unbind the buffers. Mark which caches need to be flushed. */
103 	if (sctx->streamout.num_targets && sctx->streamout.begin_emitted) {
104 		/* Since streamout uses vector writes which go through TC L2
105 		 * and most other clients can use TC L2 as well, we don't need
106 		 * to flush it.
107 		 *
108 		 * The only cases which requires flushing it is VGT DMA index
109 		 * fetching (on <= CIK) and indirect draw data, which are rare
110 		 * cases. Thus, flag the TC L2 dirtiness in the resource and
111 		 * handle it at draw call time.
112 		 */
113 		for (i = 0; i < sctx->streamout.num_targets; i++)
114 			if (sctx->streamout.targets[i])
115 				r600_resource(sctx->streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
116 
117 		/* Invalidate the scalar cache in case a streamout buffer is
118 		 * going to be used as a constant buffer.
119 		 *
120 		 * Invalidate TC L1, because streamout bypasses it (done by
121 		 * setting GLC=1 in the store instruction), but it can contain
122 		 * outdated data of streamout buffers.
123 		 *
124 		 * VS_PARTIAL_FLUSH is required if the buffers are going to be
125 		 * used as an input immediately.
126 		 */
127 		sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
128 				 SI_CONTEXT_INV_VMEM_L1 |
129 				 SI_CONTEXT_VS_PARTIAL_FLUSH;
130 	}
131 
132 	/* All readers of the streamout targets need to be finished before we can
133 	 * start writing to the targets.
134 	 */
135 	if (num_targets)
136 		sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
137 		                 SI_CONTEXT_CS_PARTIAL_FLUSH;
138 
139 	/* Streamout buffers must be bound in 2 places:
140 	 * 1) in VGT by setting the VGT_STRMOUT registers
141 	 * 2) as shader resources
142 	 */
143 
144 	/* Stop streamout. */
145 	if (sctx->streamout.num_targets && sctx->streamout.begin_emitted)
146 		si_emit_streamout_end(sctx);
147 
148 	/* Set the new targets. */
149 	unsigned enabled_mask = 0, append_bitmask = 0;
150 	for (i = 0; i < num_targets; i++) {
151 		si_so_target_reference(&sctx->streamout.targets[i], targets[i]);
152 		if (!targets[i])
153 			continue;
154 
155 		si_context_add_resource_size(ctx, targets[i]->buffer);
156 		enabled_mask |= 1 << i;
157 
158 		if (offsets[i] == ((unsigned)-1))
159 			append_bitmask |= 1 << i;
160 	}
161 
162 	for (; i < sctx->streamout.num_targets; i++)
163 		si_so_target_reference(&sctx->streamout.targets[i], NULL);
164 
165 	sctx->streamout.enabled_mask = enabled_mask;
166 	sctx->streamout.num_targets = num_targets;
167 	sctx->streamout.append_bitmask = append_bitmask;
168 
169 	/* Update dirty state bits. */
170 	if (num_targets) {
171 		si_streamout_buffers_dirty(sctx);
172 	} else {
173 		si_set_atom_dirty(sctx, &sctx->streamout.begin_atom, false);
174 		si_set_streamout_enable(sctx, false);
175 	}
176 
177 	/* Set the shader resources.*/
178 	for (i = 0; i < num_targets; i++) {
179 		bufidx = SI_VS_STREAMOUT_BUF0 + i;
180 
181 		if (targets[i]) {
182 			struct pipe_resource *buffer = targets[i]->buffer;
183 			uint64_t va = r600_resource(buffer)->gpu_address;
184 
185 			/* Set the descriptor.
186 			 *
187 			 * On VI, the format must be non-INVALID, otherwise
188 			 * the buffer will be considered not bound and store
189 			 * instructions will be no-ops.
190 			 */
191 			uint32_t *desc = descs->list + bufidx*4;
192 			desc[0] = va;
193 			desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
194 			desc[2] = 0xffffffff;
195 			desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
196 				  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
197 				  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
198 				  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
199 				  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
200 
201 			/* Set the resource. */
202 			pipe_resource_reference(&buffers->buffers[bufidx],
203 						buffer);
204 			radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
205 							    (struct r600_resource*)buffer,
206 							    buffers->shader_usage,
207 							    RADEON_PRIO_SHADER_RW_BUFFER,
208 							    true);
209 			r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT;
210 
211 			buffers->enabled_mask |= 1u << bufidx;
212 		} else {
213 			/* Clear the descriptor and unset the resource. */
214 			memset(descs->list + bufidx*4, 0,
215 			       sizeof(uint32_t) * 4);
216 			pipe_resource_reference(&buffers->buffers[bufidx],
217 						NULL);
218 			buffers->enabled_mask &= ~(1u << bufidx);
219 		}
220 	}
221 	for (; i < old_num_targets; i++) {
222 		bufidx = SI_VS_STREAMOUT_BUF0 + i;
223 		/* Clear the descriptor and unset the resource. */
224 		memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
225 		pipe_resource_reference(&buffers->buffers[bufidx], NULL);
226 		buffers->enabled_mask &= ~(1u << bufidx);
227 	}
228 
229 	sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
230 }
231 
si_flush_vgt_streamout(struct si_context * sctx)232 static void si_flush_vgt_streamout(struct si_context *sctx)
233 {
234 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
235 	unsigned reg_strmout_cntl;
236 
237 	/* The register is at different places on different ASICs. */
238 	if (sctx->b.chip_class >= CIK) {
239 		reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
240 		radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
241 	} else {
242 		reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
243 		radeon_set_config_reg(cs, reg_strmout_cntl, 0);
244 	}
245 
246 	radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
247 	radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
248 
249 	radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
250 	radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
251 	radeon_emit(cs, reg_strmout_cntl >> 2);  /* register */
252 	radeon_emit(cs, 0);
253 	radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
254 	radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
255 	radeon_emit(cs, 4); /* poll interval */
256 }
257 
si_emit_streamout_begin(struct r600_common_context * rctx,struct r600_atom * atom)258 static void si_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
259 {
260 	struct si_context *sctx = (struct si_context*)rctx;
261 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
262 	struct si_streamout_target **t = sctx->streamout.targets;
263 	uint16_t *stride_in_dw = sctx->streamout.stride_in_dw;
264 	unsigned i;
265 
266 	si_flush_vgt_streamout(sctx);
267 
268 	for (i = 0; i < sctx->streamout.num_targets; i++) {
269 		if (!t[i])
270 			continue;
271 
272 		t[i]->stride_in_dw = stride_in_dw[i];
273 
274 		/* SI binds streamout buffers as shader resources.
275 		 * VGT only counts primitives and tells the shader
276 		 * through SGPRs what to do. */
277 		radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
278 		radeon_emit(cs, (t[i]->b.buffer_offset +
279 				 t[i]->b.buffer_size) >> 2);	/* BUFFER_SIZE (in DW) */
280 		radeon_emit(cs, stride_in_dw[i]);		/* VTX_STRIDE (in DW) */
281 
282 		if (sctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
283 			uint64_t va = t[i]->buf_filled_size->gpu_address +
284 				      t[i]->buf_filled_size_offset;
285 
286 			/* Append. */
287 			radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
288 			radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
289 				    STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
290 			radeon_emit(cs, 0); /* unused */
291 			radeon_emit(cs, 0); /* unused */
292 			radeon_emit(cs, va); /* src address lo */
293 			radeon_emit(cs, va >> 32); /* src address hi */
294 
295 			radeon_add_to_buffer_list(&sctx->b,  &sctx->b.gfx,
296 						  t[i]->buf_filled_size,
297 						  RADEON_USAGE_READ,
298 						  RADEON_PRIO_SO_FILLED_SIZE);
299 		} else {
300 			/* Start from the beginning. */
301 			radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
302 			radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
303 				    STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
304 			radeon_emit(cs, 0); /* unused */
305 			radeon_emit(cs, 0); /* unused */
306 			radeon_emit(cs, t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
307 			radeon_emit(cs, 0); /* unused */
308 		}
309 	}
310 
311 	sctx->streamout.begin_emitted = true;
312 }
313 
si_emit_streamout_end(struct si_context * sctx)314 void si_emit_streamout_end(struct si_context *sctx)
315 {
316 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
317 	struct si_streamout_target **t = sctx->streamout.targets;
318 	unsigned i;
319 	uint64_t va;
320 
321 	si_flush_vgt_streamout(sctx);
322 
323 	for (i = 0; i < sctx->streamout.num_targets; i++) {
324 		if (!t[i])
325 			continue;
326 
327 		va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
328 		radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
329 		radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
330 			    STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
331 			    STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
332 		radeon_emit(cs, va);     /* dst address lo */
333 		radeon_emit(cs, va >> 32); /* dst address hi */
334 		radeon_emit(cs, 0); /* unused */
335 		radeon_emit(cs, 0); /* unused */
336 
337 		radeon_add_to_buffer_list(&sctx->b,  &sctx->b.gfx,
338 					  t[i]->buf_filled_size,
339 					  RADEON_USAGE_WRITE,
340 					  RADEON_PRIO_SO_FILLED_SIZE);
341 
342 		/* Zero the buffer size. The counters (primitives generated,
343 		 * primitives emitted) may be enabled even if there is not
344 		 * buffer bound. This ensures that the primitives-emitted query
345 		 * won't increment. */
346 		radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
347 
348 		t[i]->buf_filled_size_valid = true;
349 	}
350 
351 	sctx->streamout.begin_emitted = false;
352 }
353 
354 /* STREAMOUT CONFIG DERIVED STATE
355  *
356  * Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
357  * The buffer mask is an independent state, so no writes occur if there
358  * are no buffers bound.
359  */
360 
si_emit_streamout_enable(struct r600_common_context * rctx,struct r600_atom * atom)361 static void si_emit_streamout_enable(struct r600_common_context *rctx,
362 				     struct r600_atom *atom)
363 {
364 	struct si_context *sctx = (struct si_context*)rctx;
365 
366 	radeon_set_context_reg_seq(sctx->b.gfx.cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
367 	radeon_emit(sctx->b.gfx.cs,
368 		    S_028B94_STREAMOUT_0_EN(si_get_strmout_en(sctx)) |
369 		    S_028B94_RAST_STREAM(0) |
370 		    S_028B94_STREAMOUT_1_EN(si_get_strmout_en(sctx)) |
371 		    S_028B94_STREAMOUT_2_EN(si_get_strmout_en(sctx)) |
372 		    S_028B94_STREAMOUT_3_EN(si_get_strmout_en(sctx)));
373 	radeon_emit(sctx->b.gfx.cs,
374 		    sctx->streamout.hw_enabled_mask &
375 		    sctx->streamout.enabled_stream_buffers_mask);
376 }
377 
si_set_streamout_enable(struct si_context * sctx,bool enable)378 static void si_set_streamout_enable(struct si_context *sctx, bool enable)
379 {
380 	bool old_strmout_en = si_get_strmout_en(sctx);
381 	unsigned old_hw_enabled_mask = sctx->streamout.hw_enabled_mask;
382 
383 	sctx->streamout.streamout_enabled = enable;
384 
385 	sctx->streamout.hw_enabled_mask = sctx->streamout.enabled_mask |
386 					  (sctx->streamout.enabled_mask << 4) |
387 					  (sctx->streamout.enabled_mask << 8) |
388 					  (sctx->streamout.enabled_mask << 12);
389 
390 	if ((old_strmout_en != si_get_strmout_en(sctx)) ||
391             (old_hw_enabled_mask != sctx->streamout.hw_enabled_mask))
392 		si_mark_atom_dirty(sctx, &sctx->streamout.enable_atom);
393 }
394 
si_update_prims_generated_query_state(struct si_context * sctx,unsigned type,int diff)395 void si_update_prims_generated_query_state(struct si_context *sctx,
396 					   unsigned type, int diff)
397 {
398 	if (type == PIPE_QUERY_PRIMITIVES_GENERATED) {
399 		bool old_strmout_en = si_get_strmout_en(sctx);
400 
401 		sctx->streamout.num_prims_gen_queries += diff;
402 		assert(sctx->streamout.num_prims_gen_queries >= 0);
403 
404 		sctx->streamout.prims_gen_query_enabled =
405 			sctx->streamout.num_prims_gen_queries != 0;
406 
407 		if (old_strmout_en != si_get_strmout_en(sctx))
408 			si_mark_atom_dirty(sctx, &sctx->streamout.enable_atom);
409 	}
410 }
411 
si_init_streamout_functions(struct si_context * sctx)412 void si_init_streamout_functions(struct si_context *sctx)
413 {
414 	sctx->b.b.create_stream_output_target = si_create_so_target;
415 	sctx->b.b.stream_output_target_destroy = si_so_target_destroy;
416 	sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
417 	sctx->streamout.begin_atom.emit = si_emit_streamout_begin;
418 	sctx->streamout.enable_atom.emit = si_emit_streamout_enable;
419 }
420