1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <linux/libfdt.h>
11 #include <altera.h>
12 #include <miiphy.h>
13 #include <netdev.h>
14 #include <watchdog.h>
15 #include <asm/arch/misc.h>
16 #include <asm/arch/reset_manager.h>
17 #include <asm/arch/scan_manager.h>
18 #include <asm/arch/system_manager.h>
19 #include <asm/arch/nic301.h>
20 #include <asm/arch/scu.h>
21 #include <asm/pl310.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #ifdef CONFIG_SYS_L2_PL310
26 static const struct pl310_regs *const pl310 =
27 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
28 #endif
29
30 struct bsel bsel_str[] = {
31 { "rsvd", "Reserved", },
32 { "fpga", "FPGA (HPS2FPGA Bridge)", },
33 { "nand", "NAND Flash (1.8V)", },
34 { "nand", "NAND Flash (3.0V)", },
35 { "sd", "SD/MMC External Transceiver (1.8V)", },
36 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
37 { "qspi", "QSPI Flash (1.8V)", },
38 { "qspi", "QSPI Flash (3.0V)", },
39 };
40
dram_init(void)41 int dram_init(void)
42 {
43 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
44 return 0;
45 }
46
enable_caches(void)47 void enable_caches(void)
48 {
49 #ifndef CONFIG_SYS_ICACHE_OFF
50 icache_enable();
51 #endif
52 #ifndef CONFIG_SYS_DCACHE_OFF
53 dcache_enable();
54 #endif
55 }
56
57 #ifdef CONFIG_SYS_L2_PL310
v7_outer_cache_enable(void)58 void v7_outer_cache_enable(void)
59 {
60 /* Disable the L2 cache */
61 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
62
63 /* enable BRESP, instruction and data prefetch, full line of zeroes */
64 setbits_le32(&pl310->pl310_aux_ctrl,
65 L310_AUX_CTRL_DATA_PREFETCH_MASK |
66 L310_AUX_CTRL_INST_PREFETCH_MASK |
67 L310_SHARED_ATT_OVERRIDE_ENABLE);
68
69 /* Enable the L2 cache */
70 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
71 }
72
v7_outer_cache_disable(void)73 void v7_outer_cache_disable(void)
74 {
75 /* Disable the L2 cache */
76 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
77 }
78 #endif
79
80 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
81 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
overwrite_console(void)82 int overwrite_console(void)
83 {
84 return 0;
85 }
86 #endif
87
88 #ifdef CONFIG_FPGA
89 /*
90 * FPGA programming support for SoC FPGA Cyclone V
91 */
92 static Altera_desc altera_fpga[] = {
93 {
94 /* Family */
95 Altera_SoCFPGA,
96 /* Interface type */
97 fast_passive_parallel,
98 /* No limitation as additional data will be ignored */
99 -1,
100 /* No device function table */
101 NULL,
102 /* Base interface address specified in driver */
103 NULL,
104 /* No cookie implementation */
105 0
106 },
107 };
108
109 /* add device descriptor to FPGA device table */
socfpga_fpga_add(void)110 void socfpga_fpga_add(void)
111 {
112 int i;
113 fpga_init();
114 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
115 fpga_add(fpga_altera, &altera_fpga[i]);
116 }
117 #endif
118
arch_cpu_init(void)119 int arch_cpu_init(void)
120 {
121 #ifdef CONFIG_HW_WATCHDOG
122 /*
123 * In case the watchdog is enabled, make sure to (re-)configure it
124 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
125 * timeout value is still active which might too short for Linux
126 * booting.
127 */
128 hw_watchdog_init();
129 #else
130 /*
131 * If the HW watchdog is NOT enabled, make sure it is not running,
132 * for example because it was enabled in the preloader. This might
133 * trigger a watchdog-triggered reboot of Linux kernel later.
134 * Toggle watchdog reset, so watchdog in not running state.
135 */
136 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
137 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
138 #endif
139
140 return 0;
141 }
142
143 #ifdef CONFIG_ETH_DESIGNWARE
dwmac_phymode_to_modereg(const char * phymode,u32 * modereg)144 static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
145 {
146 if (!phymode)
147 return -EINVAL;
148
149 if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
150 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
151 return 0;
152 }
153
154 if (!strcmp(phymode, "rgmii")) {
155 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
156 return 0;
157 }
158
159 if (!strcmp(phymode, "rmii")) {
160 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
161 return 0;
162 }
163
164 return -EINVAL;
165 }
166
socfpga_eth_reset_common(void (* resetfn)(const u8 of_reset_id,const u8 phymode))167 int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
168 const u8 phymode))
169 {
170 const void *fdt = gd->fdt_blob;
171 struct fdtdec_phandle_args args;
172 const char *phy_mode;
173 u32 phy_modereg;
174 int nodes[2]; /* Max. two GMACs */
175 int ret, count;
176 int i, node;
177
178 count = fdtdec_find_aliases_for_id(fdt, "ethernet",
179 COMPAT_ALTERA_SOCFPGA_DWMAC,
180 nodes, ARRAY_SIZE(nodes));
181 for (i = 0; i < count; i++) {
182 node = nodes[i];
183 if (node <= 0)
184 continue;
185
186 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
187 "#reset-cells", 1, 0,
188 &args);
189 if (ret || (args.args_count != 1)) {
190 debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
191 continue;
192 }
193
194 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
195 ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
196 if (ret) {
197 debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
198 continue;
199 }
200
201 resetfn(args.args[0], phy_modereg);
202 }
203
204 return 0;
205 }
206 #endif
207