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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2007-2008
4  * Stelian Pop <stelian@popies.net>
5  * Lead Tech Design <www.leadtechdesign.com>
6  *
7  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8  *
9  * Add Programmable Multibit ECC support for various AT91 SoC
10  *     (C) Copyright 2012 ATMEL, Hong Xu
11  */
12 
13 #include <common.h>
14 #include <asm/gpio.h>
15 #include <asm/arch/gpio.h>
16 
17 #include <malloc.h>
18 #include <nand.h>
19 #include <watchdog.h>
20 #include <linux/mtd/nand_ecc.h>
21 
22 #ifdef CONFIG_ATMEL_NAND_HWECC
23 
24 /* Register access macros */
25 #define ecc_readl(add, reg)				\
26 	readl(add + ATMEL_ECC_##reg)
27 #define ecc_writel(add, reg, value)			\
28 	writel((value), add + ATMEL_ECC_##reg)
29 
30 #include "atmel_nand_ecc.h"	/* Hardware ECC registers */
31 
32 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
33 
34 #ifdef CONFIG_SPL_BUILD
35 #undef CONFIG_SYS_NAND_ONFI_DETECTION
36 #endif
37 
38 struct atmel_nand_host {
39 	struct pmecc_regs __iomem *pmecc;
40 	struct pmecc_errloc_regs __iomem *pmerrloc;
41 	void __iomem		*pmecc_rom_base;
42 
43 	u8		pmecc_corr_cap;
44 	u16		pmecc_sector_size;
45 	u32		pmecc_index_table_offset;
46 	u32		pmecc_version;
47 
48 	int		pmecc_bytes_per_sector;
49 	int		pmecc_sector_number;
50 	int		pmecc_degree;	/* Degree of remainders */
51 	int		pmecc_cw_len;	/* Length of codeword */
52 
53 	/* lookup table for alpha_to and index_of */
54 	void __iomem	*pmecc_alpha_to;
55 	void __iomem	*pmecc_index_of;
56 
57 	/* data for pmecc computation */
58 	int16_t	*pmecc_smu;
59 	int16_t	*pmecc_partial_syn;
60 	int16_t	*pmecc_si;
61 	int16_t	*pmecc_lmu; /* polynomal order */
62 	int	*pmecc_mu;
63 	int	*pmecc_dmu;
64 	int	*pmecc_delta;
65 };
66 
67 static struct atmel_nand_host pmecc_host;
68 static struct nand_ecclayout atmel_pmecc_oobinfo;
69 
70 /*
71  * Return number of ecc bytes per sector according to sector size and
72  * correction capability
73  *
74  * Following table shows what at91 PMECC supported:
75  * Correction Capability	Sector_512_bytes	Sector_1024_bytes
76  * =====================	================	=================
77  *                2-bits                 4-bytes                  4-bytes
78  *                4-bits                 7-bytes                  7-bytes
79  *                8-bits                13-bytes                 14-bytes
80  *               12-bits                20-bytes                 21-bytes
81  *               24-bits                39-bytes                 42-bytes
82  *               32-bits                52-bytes                 56-bytes
83  */
pmecc_get_ecc_bytes(int cap,int sector_size)84 static int pmecc_get_ecc_bytes(int cap, int sector_size)
85 {
86 	int m = 12 + sector_size / 512;
87 	return (m * cap + 7) / 8;
88 }
89 
pmecc_config_ecc_layout(struct nand_ecclayout * layout,int oobsize,int ecc_len)90 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
91 	int oobsize, int ecc_len)
92 {
93 	int i;
94 
95 	layout->eccbytes = ecc_len;
96 
97 	/* ECC will occupy the last ecc_len bytes continuously */
98 	for (i = 0; i < ecc_len; i++)
99 		layout->eccpos[i] = oobsize - ecc_len + i;
100 
101 	layout->oobfree[0].offset = 2;
102 	layout->oobfree[0].length =
103 		oobsize - ecc_len - layout->oobfree[0].offset;
104 }
105 
pmecc_get_alpha_to(struct atmel_nand_host * host)106 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
107 {
108 	int table_size;
109 
110 	table_size = host->pmecc_sector_size == 512 ?
111 		PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
112 
113 	/* the ALPHA lookup table is right behind the INDEX lookup table. */
114 	return host->pmecc_rom_base + host->pmecc_index_table_offset +
115 			table_size * sizeof(int16_t);
116 }
117 
pmecc_data_free(struct atmel_nand_host * host)118 static void pmecc_data_free(struct atmel_nand_host *host)
119 {
120 	free(host->pmecc_partial_syn);
121 	free(host->pmecc_si);
122 	free(host->pmecc_lmu);
123 	free(host->pmecc_smu);
124 	free(host->pmecc_mu);
125 	free(host->pmecc_dmu);
126 	free(host->pmecc_delta);
127 }
128 
pmecc_data_alloc(struct atmel_nand_host * host)129 static int pmecc_data_alloc(struct atmel_nand_host *host)
130 {
131 	const int cap = host->pmecc_corr_cap;
132 	int size;
133 
134 	size = (2 * cap + 1) * sizeof(int16_t);
135 	host->pmecc_partial_syn = malloc(size);
136 	host->pmecc_si = malloc(size);
137 	host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
138 	host->pmecc_smu = malloc((cap + 2) * size);
139 
140 	size = (cap + 1) * sizeof(int);
141 	host->pmecc_mu = malloc(size);
142 	host->pmecc_dmu = malloc(size);
143 	host->pmecc_delta = malloc(size);
144 
145 	if (host->pmecc_partial_syn &&
146 			host->pmecc_si &&
147 			host->pmecc_lmu &&
148 			host->pmecc_smu &&
149 			host->pmecc_mu &&
150 			host->pmecc_dmu &&
151 			host->pmecc_delta)
152 		return 0;
153 
154 	/* error happened */
155 	pmecc_data_free(host);
156 	return -ENOMEM;
157 
158 }
159 
pmecc_gen_syndrome(struct mtd_info * mtd,int sector)160 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
161 {
162 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
163 	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
164 	int i;
165 	uint32_t value;
166 
167 	/* Fill odd syndromes */
168 	for (i = 0; i < host->pmecc_corr_cap; i++) {
169 		value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
170 		if (i & 1)
171 			value >>= 16;
172 		value &= 0xffff;
173 		host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
174 	}
175 }
176 
pmecc_substitute(struct mtd_info * mtd)177 static void pmecc_substitute(struct mtd_info *mtd)
178 {
179 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
180 	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
181 	int16_t __iomem *alpha_to = host->pmecc_alpha_to;
182 	int16_t __iomem *index_of = host->pmecc_index_of;
183 	int16_t *partial_syn = host->pmecc_partial_syn;
184 	const int cap = host->pmecc_corr_cap;
185 	int16_t *si;
186 	int i, j;
187 
188 	/* si[] is a table that holds the current syndrome value,
189 	 * an element of that table belongs to the field
190 	 */
191 	si = host->pmecc_si;
192 
193 	memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
194 
195 	/* Computation 2t syndromes based on S(x) */
196 	/* Odd syndromes */
197 	for (i = 1; i < 2 * cap; i += 2) {
198 		for (j = 0; j < host->pmecc_degree; j++) {
199 			if (partial_syn[i] & (0x1 << j))
200 				si[i] = readw(alpha_to + i * j) ^ si[i];
201 		}
202 	}
203 	/* Even syndrome = (Odd syndrome) ** 2 */
204 	for (i = 2, j = 1; j <= cap; i = ++j << 1) {
205 		if (si[j] == 0) {
206 			si[i] = 0;
207 		} else {
208 			int16_t tmp;
209 
210 			tmp = readw(index_of + si[j]);
211 			tmp = (tmp * 2) % host->pmecc_cw_len;
212 			si[i] = readw(alpha_to + tmp);
213 		}
214 	}
215 }
216 
217 /*
218  * This function defines a Berlekamp iterative procedure for
219  * finding the value of the error location polynomial.
220  * The input is si[], initialize by pmecc_substitute().
221  * The output is smu[][].
222  *
223  * This function is written according to chip datasheet Chapter:
224  * Find the Error Location Polynomial Sigma(x) of Section:
225  * Programmable Multibit ECC Control (PMECC).
226  */
pmecc_get_sigma(struct mtd_info * mtd)227 static void pmecc_get_sigma(struct mtd_info *mtd)
228 {
229 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
230 	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
231 
232 	int16_t *lmu = host->pmecc_lmu;
233 	int16_t *si = host->pmecc_si;
234 	int *mu = host->pmecc_mu;
235 	int *dmu = host->pmecc_dmu;	/* Discrepancy */
236 	int *delta = host->pmecc_delta; /* Delta order */
237 	int cw_len = host->pmecc_cw_len;
238 	const int16_t cap = host->pmecc_corr_cap;
239 	const int num = 2 * cap + 1;
240 	int16_t __iomem	*index_of = host->pmecc_index_of;
241 	int16_t __iomem	*alpha_to = host->pmecc_alpha_to;
242 	int i, j, k;
243 	uint32_t dmu_0_count, tmp;
244 	int16_t *smu = host->pmecc_smu;
245 
246 	/* index of largest delta */
247 	int ro;
248 	int largest;
249 	int diff;
250 
251 	/* Init the Sigma(x) */
252 	memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
253 
254 	dmu_0_count = 0;
255 
256 	/* First Row */
257 
258 	/* Mu */
259 	mu[0] = -1;
260 
261 	smu[0] = 1;
262 
263 	/* discrepancy set to 1 */
264 	dmu[0] = 1;
265 	/* polynom order set to 0 */
266 	lmu[0] = 0;
267 	/* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
268 	delta[0] = -1;
269 
270 	/* Second Row */
271 
272 	/* Mu */
273 	mu[1] = 0;
274 	/* Sigma(x) set to 1 */
275 	smu[num] = 1;
276 
277 	/* discrepancy set to S1 */
278 	dmu[1] = si[1];
279 
280 	/* polynom order set to 0 */
281 	lmu[1] = 0;
282 
283 	/* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
284 	delta[1] = 0;
285 
286 	for (i = 1; i <= cap; i++) {
287 		mu[i + 1] = i << 1;
288 		/* Begin Computing Sigma (Mu+1) and L(mu) */
289 		/* check if discrepancy is set to 0 */
290 		if (dmu[i] == 0) {
291 			dmu_0_count++;
292 
293 			tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
294 			if ((cap - (lmu[i] >> 1) - 1) & 0x1)
295 				tmp += 2;
296 			else
297 				tmp += 1;
298 
299 			if (dmu_0_count == tmp) {
300 				for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
301 					smu[(cap + 1) * num + j] =
302 							smu[i * num + j];
303 
304 				lmu[cap + 1] = lmu[i];
305 				return;
306 			}
307 
308 			/* copy polynom */
309 			for (j = 0; j <= lmu[i] >> 1; j++)
310 				smu[(i + 1) * num + j] = smu[i * num + j];
311 
312 			/* copy previous polynom order to the next */
313 			lmu[i + 1] = lmu[i];
314 		} else {
315 			ro = 0;
316 			largest = -1;
317 			/* find largest delta with dmu != 0 */
318 			for (j = 0; j < i; j++) {
319 				if ((dmu[j]) && (delta[j] > largest)) {
320 					largest = delta[j];
321 					ro = j;
322 				}
323 			}
324 
325 			/* compute difference */
326 			diff = (mu[i] - mu[ro]);
327 
328 			/* Compute degree of the new smu polynomial */
329 			if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
330 				lmu[i + 1] = lmu[i];
331 			else
332 				lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
333 
334 			/* Init smu[i+1] with 0 */
335 			for (k = 0; k < num; k++)
336 				smu[(i + 1) * num + k] = 0;
337 
338 			/* Compute smu[i+1] */
339 			for (k = 0; k <= lmu[ro] >> 1; k++) {
340 				int16_t a, b, c;
341 
342 				if (!(smu[ro * num + k] && dmu[i]))
343 					continue;
344 				a = readw(index_of + dmu[i]);
345 				b = readw(index_of + dmu[ro]);
346 				c = readw(index_of + smu[ro * num + k]);
347 				tmp = a + (cw_len - b) + c;
348 				a = readw(alpha_to + tmp % cw_len);
349 				smu[(i + 1) * num + (k + diff)] = a;
350 			}
351 
352 			for (k = 0; k <= lmu[i] >> 1; k++)
353 				smu[(i + 1) * num + k] ^= smu[i * num + k];
354 		}
355 
356 		/* End Computing Sigma (Mu+1) and L(mu) */
357 		/* In either case compute delta */
358 		delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
359 
360 		/* Do not compute discrepancy for the last iteration */
361 		if (i >= cap)
362 			continue;
363 
364 		for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
365 			tmp = 2 * (i - 1);
366 			if (k == 0) {
367 				dmu[i + 1] = si[tmp + 3];
368 			} else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
369 				int16_t a, b, c;
370 				a = readw(index_of +
371 						smu[(i + 1) * num + k]);
372 				b = si[2 * (i - 1) + 3 - k];
373 				c = readw(index_of + b);
374 				tmp = a + c;
375 				tmp %= cw_len;
376 				dmu[i + 1] = readw(alpha_to + tmp) ^
377 					dmu[i + 1];
378 			}
379 		}
380 	}
381 }
382 
pmecc_err_location(struct mtd_info * mtd)383 static int pmecc_err_location(struct mtd_info *mtd)
384 {
385 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
386 	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
387 	const int cap = host->pmecc_corr_cap;
388 	const int num = 2 * cap + 1;
389 	int sector_size = host->pmecc_sector_size;
390 	int err_nbr = 0;	/* number of error */
391 	int roots_nbr;		/* number of roots */
392 	int i;
393 	uint32_t val;
394 	int16_t *smu = host->pmecc_smu;
395 	int timeout = PMECC_MAX_TIMEOUT_US;
396 
397 	pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
398 
399 	for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
400 		pmecc_writel(host->pmerrloc, sigma[i],
401 			     smu[(cap + 1) * num + i]);
402 		err_nbr++;
403 	}
404 
405 	val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
406 	if (sector_size == 1024)
407 		val |= PMERRLOC_ELCFG_SECTOR_1024;
408 
409 	pmecc_writel(host->pmerrloc, elcfg, val);
410 	pmecc_writel(host->pmerrloc, elen,
411 		     sector_size * 8 + host->pmecc_degree * cap);
412 
413 	while (--timeout) {
414 		if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
415 			break;
416 		WATCHDOG_RESET();
417 		udelay(1);
418 	}
419 
420 	if (!timeout) {
421 		dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
422 		return -1;
423 	}
424 
425 	roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
426 			>> 8;
427 	/* Number of roots == degree of smu hence <= cap */
428 	if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
429 		return err_nbr - 1;
430 
431 	/* Number of roots does not match the degree of smu
432 	 * unable to correct error */
433 	return -1;
434 }
435 
pmecc_correct_data(struct mtd_info * mtd,uint8_t * buf,uint8_t * ecc,int sector_num,int extra_bytes,int err_nbr)436 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
437 		int sector_num, int extra_bytes, int err_nbr)
438 {
439 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
440 	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
441 	int i = 0;
442 	int byte_pos, bit_pos, sector_size, pos;
443 	uint32_t tmp;
444 	uint8_t err_byte;
445 
446 	sector_size = host->pmecc_sector_size;
447 
448 	while (err_nbr) {
449 		tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
450 		byte_pos = tmp / 8;
451 		bit_pos  = tmp % 8;
452 
453 		if (byte_pos >= (sector_size + extra_bytes))
454 			BUG();	/* should never happen */
455 
456 		if (byte_pos < sector_size) {
457 			err_byte = *(buf + byte_pos);
458 			*(buf + byte_pos) ^= (1 << bit_pos);
459 
460 			pos = sector_num * host->pmecc_sector_size + byte_pos;
461 			dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
462 				pos, bit_pos, err_byte, *(buf + byte_pos));
463 		} else {
464 			/* Bit flip in OOB area */
465 			tmp = sector_num * host->pmecc_bytes_per_sector
466 					+ (byte_pos - sector_size);
467 			err_byte = ecc[tmp];
468 			ecc[tmp] ^= (1 << bit_pos);
469 
470 			pos = tmp + nand_chip->ecc.layout->eccpos[0];
471 			dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
472 				pos, bit_pos, err_byte, ecc[tmp]);
473 		}
474 
475 		i++;
476 		err_nbr--;
477 	}
478 
479 	return;
480 }
481 
pmecc_correction(struct mtd_info * mtd,u32 pmecc_stat,uint8_t * buf,u8 * ecc)482 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
483 	u8 *ecc)
484 {
485 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
486 	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
487 	int i, err_nbr, eccbytes;
488 	uint8_t *buf_pos;
489 
490 	/* SAMA5D4 PMECC IP can correct errors for all 0xff page */
491 	if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
492 		goto normal_check;
493 
494 	eccbytes = nand_chip->ecc.bytes;
495 	for (i = 0; i < eccbytes; i++)
496 		if (ecc[i] != 0xff)
497 			goto normal_check;
498 	/* Erased page, return OK */
499 	return 0;
500 
501 normal_check:
502 	for (i = 0; i < host->pmecc_sector_number; i++) {
503 		err_nbr = 0;
504 		if (pmecc_stat & 0x1) {
505 			buf_pos = buf + i * host->pmecc_sector_size;
506 
507 			pmecc_gen_syndrome(mtd, i);
508 			pmecc_substitute(mtd);
509 			pmecc_get_sigma(mtd);
510 
511 			err_nbr = pmecc_err_location(mtd);
512 			if (err_nbr == -1) {
513 				dev_err(host->dev, "PMECC: Too many errors\n");
514 				mtd->ecc_stats.failed++;
515 				return -EBADMSG;
516 			} else {
517 				pmecc_correct_data(mtd, buf_pos, ecc, i,
518 					host->pmecc_bytes_per_sector, err_nbr);
519 				mtd->ecc_stats.corrected += err_nbr;
520 			}
521 		}
522 		pmecc_stat >>= 1;
523 	}
524 
525 	return 0;
526 }
527 
atmel_nand_pmecc_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)528 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
529 	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
530 {
531 	struct atmel_nand_host *host = nand_get_controller_data(chip);
532 	int eccsize = chip->ecc.size;
533 	uint8_t *oob = chip->oob_poi;
534 	uint32_t *eccpos = chip->ecc.layout->eccpos;
535 	uint32_t stat;
536 	int timeout = PMECC_MAX_TIMEOUT_US;
537 
538 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
539 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
540 	pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
541 		& ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
542 
543 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
544 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
545 
546 	chip->read_buf(mtd, buf, eccsize);
547 	chip->read_buf(mtd, oob, mtd->oobsize);
548 
549 	while (--timeout) {
550 		if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
551 			break;
552 		WATCHDOG_RESET();
553 		udelay(1);
554 	}
555 
556 	if (!timeout) {
557 		dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
558 		return -1;
559 	}
560 
561 	stat = pmecc_readl(host->pmecc, isr);
562 	if (stat != 0)
563 		if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
564 			return -EBADMSG;
565 
566 	return 0;
567 }
568 
atmel_nand_pmecc_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)569 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
570 		struct nand_chip *chip, const uint8_t *buf,
571 		int oob_required, int page)
572 {
573 	struct atmel_nand_host *host = nand_get_controller_data(chip);
574 	uint32_t *eccpos = chip->ecc.layout->eccpos;
575 	int i, j;
576 	int timeout = PMECC_MAX_TIMEOUT_US;
577 
578 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
579 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
580 
581 	pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
582 		PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
583 
584 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
585 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
586 
587 	chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
588 
589 	while (--timeout) {
590 		if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
591 			break;
592 		WATCHDOG_RESET();
593 		udelay(1);
594 	}
595 
596 	if (!timeout) {
597 		dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
598 		goto out;
599 	}
600 
601 	for (i = 0; i < host->pmecc_sector_number; i++) {
602 		for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
603 			int pos;
604 
605 			pos = i * host->pmecc_bytes_per_sector + j;
606 			chip->oob_poi[eccpos[pos]] =
607 				pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
608 		}
609 	}
610 	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
611 out:
612 	return 0;
613 }
614 
atmel_pmecc_core_init(struct mtd_info * mtd)615 static void atmel_pmecc_core_init(struct mtd_info *mtd)
616 {
617 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
618 	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
619 	uint32_t val = 0;
620 	struct nand_ecclayout *ecc_layout;
621 
622 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
623 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
624 
625 	switch (host->pmecc_corr_cap) {
626 	case 2:
627 		val = PMECC_CFG_BCH_ERR2;
628 		break;
629 	case 4:
630 		val = PMECC_CFG_BCH_ERR4;
631 		break;
632 	case 8:
633 		val = PMECC_CFG_BCH_ERR8;
634 		break;
635 	case 12:
636 		val = PMECC_CFG_BCH_ERR12;
637 		break;
638 	case 24:
639 		val = PMECC_CFG_BCH_ERR24;
640 		break;
641 	case 32:
642 		val = PMECC_CFG_BCH_ERR32;
643 		break;
644 	}
645 
646 	if (host->pmecc_sector_size == 512)
647 		val |= PMECC_CFG_SECTOR512;
648 	else if (host->pmecc_sector_size == 1024)
649 		val |= PMECC_CFG_SECTOR1024;
650 
651 	switch (host->pmecc_sector_number) {
652 	case 1:
653 		val |= PMECC_CFG_PAGE_1SECTOR;
654 		break;
655 	case 2:
656 		val |= PMECC_CFG_PAGE_2SECTORS;
657 		break;
658 	case 4:
659 		val |= PMECC_CFG_PAGE_4SECTORS;
660 		break;
661 	case 8:
662 		val |= PMECC_CFG_PAGE_8SECTORS;
663 		break;
664 	}
665 
666 	val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
667 		| PMECC_CFG_AUTO_DISABLE);
668 	pmecc_writel(host->pmecc, cfg, val);
669 
670 	ecc_layout = nand_chip->ecc.layout;
671 	pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
672 	pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
673 	pmecc_writel(host->pmecc, eaddr,
674 			ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
675 	/* See datasheet about PMECC Clock Control Register */
676 	pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
677 	pmecc_writel(host->pmecc, idr, 0xff);
678 	pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
679 }
680 
681 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
682 /*
683  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
684  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
685  *                    ONFI ECC parameters.
686  * @host: point to an atmel_nand_host structure.
687  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
688  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
689  * @chip: point to an nand_chip structure.
690  * @cap: store the ONFI ECC correct bits capbility
691  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
692  *
693  * Return 0 if success. otherwise return the error code.
694  */
pmecc_choose_ecc(struct atmel_nand_host * host,struct nand_chip * chip,int * cap,int * sector_size)695 static int pmecc_choose_ecc(struct atmel_nand_host *host,
696 		struct nand_chip *chip,
697 		int *cap, int *sector_size)
698 {
699 	/* Get ECC requirement from ONFI parameters */
700 	*cap = *sector_size = 0;
701 	if (chip->onfi_version) {
702 		*cap = chip->ecc_strength_ds;
703 		*sector_size = chip->ecc_step_ds;
704 		pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
705 			 *cap, *sector_size);
706 	}
707 
708 	if (*cap == 0 && *sector_size == 0) {
709 		/* Non-ONFI compliant */
710 		dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
711 		*cap = 2;
712 		*sector_size = 512;
713 	}
714 
715 	/* If head file doesn't specify then use the one in ONFI parameters */
716 	if (host->pmecc_corr_cap == 0) {
717 		/* use the most fitable ecc bits (the near bigger one ) */
718 		if (*cap <= 2)
719 			host->pmecc_corr_cap = 2;
720 		else if (*cap <= 4)
721 			host->pmecc_corr_cap = 4;
722 		else if (*cap <= 8)
723 			host->pmecc_corr_cap = 8;
724 		else if (*cap <= 12)
725 			host->pmecc_corr_cap = 12;
726 		else if (*cap <= 24)
727 			host->pmecc_corr_cap = 24;
728 		else
729 #ifdef CONFIG_SAMA5D2
730 			host->pmecc_corr_cap = 32;
731 #else
732 			host->pmecc_corr_cap = 24;
733 #endif
734 	}
735 	if (host->pmecc_sector_size == 0) {
736 		/* use the most fitable sector size (the near smaller one ) */
737 		if (*sector_size >= 1024)
738 			host->pmecc_sector_size = 1024;
739 		else if (*sector_size >= 512)
740 			host->pmecc_sector_size = 512;
741 		else
742 			return -EINVAL;
743 	}
744 	return 0;
745 }
746 #endif
747 
748 #if defined(NO_GALOIS_TABLE_IN_ROM)
749 static uint16_t *pmecc_galois_table;
deg(unsigned int poly)750 static inline int deg(unsigned int poly)
751 {
752 	/* polynomial degree is the most-significant bit index */
753 	return fls(poly) - 1;
754 }
755 
build_gf_tables(int mm,unsigned int poly,int16_t * index_of,int16_t * alpha_to)756 static int build_gf_tables(int mm, unsigned int poly,
757 			   int16_t *index_of, int16_t *alpha_to)
758 {
759 	unsigned int i, x = 1;
760 	const unsigned int k = 1 << deg(poly);
761 	unsigned int nn = (1 << mm) - 1;
762 
763 	/* primitive polynomial must be of degree m */
764 	if (k != (1u << mm))
765 		return -EINVAL;
766 
767 	for (i = 0; i < nn; i++) {
768 		alpha_to[i] = x;
769 		index_of[x] = i;
770 		if (i && (x == 1))
771 			/* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
772 			return -EINVAL;
773 		x <<= 1;
774 		if (x & k)
775 			x ^= poly;
776 	}
777 
778 	alpha_to[nn] = 1;
779 	index_of[0] = 0;
780 
781 	return 0;
782 }
783 
create_lookup_table(int sector_size)784 static uint16_t *create_lookup_table(int sector_size)
785 {
786 	int degree = (sector_size == 512) ?
787 			PMECC_GF_DIMENSION_13 :
788 			PMECC_GF_DIMENSION_14;
789 	unsigned int poly = (sector_size == 512) ?
790 			PMECC_GF_13_PRIMITIVE_POLY :
791 			PMECC_GF_14_PRIMITIVE_POLY;
792 	int table_size = (sector_size == 512) ?
793 			PMECC_INDEX_TABLE_SIZE_512 :
794 			PMECC_INDEX_TABLE_SIZE_1024;
795 
796 	int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
797 	if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
798 		return NULL;
799 
800 	return (uint16_t *)addr;
801 }
802 #endif
803 
atmel_pmecc_nand_init_params(struct nand_chip * nand,struct mtd_info * mtd)804 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
805 		struct mtd_info *mtd)
806 {
807 	struct atmel_nand_host *host;
808 	int cap, sector_size;
809 
810 	host = &pmecc_host;
811 	nand_set_controller_data(nand, host);
812 
813 	nand->ecc.mode = NAND_ECC_HW;
814 	nand->ecc.calculate = NULL;
815 	nand->ecc.correct = NULL;
816 	nand->ecc.hwctl = NULL;
817 
818 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
819 	host->pmecc_corr_cap = host->pmecc_sector_size = 0;
820 
821 #ifdef CONFIG_PMECC_CAP
822 	host->pmecc_corr_cap = CONFIG_PMECC_CAP;
823 #endif
824 #ifdef CONFIG_PMECC_SECTOR_SIZE
825 	host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
826 #endif
827 	/* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
828 	 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
829 	 * from ONFI.
830 	 */
831 	if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
832 		dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
833 			cap, sector_size);
834 		return -EINVAL;
835 	}
836 
837 	if (cap > host->pmecc_corr_cap)
838 		dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
839 				host->pmecc_corr_cap, cap);
840 	if (sector_size < host->pmecc_sector_size)
841 		dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
842 				host->pmecc_sector_size, sector_size);
843 #else	/* CONFIG_SYS_NAND_ONFI_DETECTION */
844 	host->pmecc_corr_cap = CONFIG_PMECC_CAP;
845 	host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
846 #endif
847 
848 	cap = host->pmecc_corr_cap;
849 	sector_size = host->pmecc_sector_size;
850 
851 	/* TODO: need check whether cap & sector_size is validate */
852 #if defined(NO_GALOIS_TABLE_IN_ROM)
853 	/*
854 	 * As pmecc_rom_base is the begin of the gallois field table, So the
855 	 * index offset just set as 0.
856 	 */
857 	host->pmecc_index_table_offset = 0;
858 #else
859 	if (host->pmecc_sector_size == 512)
860 		host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
861 	else
862 		host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
863 #endif
864 
865 	pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
866 		 cap, sector_size);
867 
868 	host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
869 	host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
870 			ATMEL_BASE_PMERRLOC;
871 #if defined(NO_GALOIS_TABLE_IN_ROM)
872 	pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
873 	if (!pmecc_galois_table) {
874 		dev_err(host->dev, "out of memory\n");
875 		return -ENOMEM;
876 	}
877 
878 	host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
879 #else
880 	host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
881 #endif
882 
883 	/* ECC is calculated for the whole page (1 step) */
884 	nand->ecc.size = mtd->writesize;
885 
886 	/* set ECC page size and oob layout */
887 	switch (mtd->writesize) {
888 	case 2048:
889 	case 4096:
890 	case 8192:
891 		host->pmecc_degree = (sector_size == 512) ?
892 			PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
893 		host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
894 		host->pmecc_sector_number = mtd->writesize / sector_size;
895 		host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
896 			cap, sector_size);
897 		host->pmecc_alpha_to = pmecc_get_alpha_to(host);
898 		host->pmecc_index_of = host->pmecc_rom_base +
899 			host->pmecc_index_table_offset;
900 
901 		nand->ecc.steps = 1;
902 		nand->ecc.bytes = host->pmecc_bytes_per_sector *
903 				       host->pmecc_sector_number;
904 
905 		if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
906 			dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
907 					MTD_MAX_ECCPOS_ENTRIES_LARGE);
908 			return -EINVAL;
909 		}
910 
911 		if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
912 			dev_err(host->dev, "No room for ECC bytes\n");
913 			return -EINVAL;
914 		}
915 		pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
916 					mtd->oobsize,
917 					nand->ecc.bytes);
918 		nand->ecc.layout = &atmel_pmecc_oobinfo;
919 		break;
920 	case 512:
921 	case 1024:
922 		/* TODO */
923 		dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
924 	default:
925 		/* page size not handled by HW ECC */
926 		/* switching back to soft ECC */
927 		nand->ecc.mode = NAND_ECC_SOFT;
928 		nand->ecc.read_page = NULL;
929 		nand->ecc.postpad = 0;
930 		nand->ecc.prepad = 0;
931 		nand->ecc.bytes = 0;
932 		return 0;
933 	}
934 
935 	/* Allocate data for PMECC computation */
936 	if (pmecc_data_alloc(host)) {
937 		dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
938 		return -ENOMEM;
939 	}
940 
941 	nand->options |= NAND_NO_SUBPAGE_WRITE;
942 	nand->ecc.read_page = atmel_nand_pmecc_read_page;
943 	nand->ecc.write_page = atmel_nand_pmecc_write_page;
944 	nand->ecc.strength = cap;
945 
946 	/* Check the PMECC ip version */
947 	host->pmecc_version = pmecc_readl(host->pmerrloc, version);
948 	dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
949 
950 	atmel_pmecc_core_init(mtd);
951 
952 	return 0;
953 }
954 
955 #else
956 
957 /* oob layout for large page size
958  * bad block info is on bytes 0 and 1
959  * the bytes have to be consecutives to avoid
960  * several NAND_CMD_RNDOUT during read
961  */
962 static struct nand_ecclayout atmel_oobinfo_large = {
963 	.eccbytes = 4,
964 	.eccpos = {60, 61, 62, 63},
965 	.oobfree = {
966 		{2, 58}
967 	},
968 };
969 
970 /* oob layout for small page size
971  * bad block info is on bytes 4 and 5
972  * the bytes have to be consecutives to avoid
973  * several NAND_CMD_RNDOUT during read
974  */
975 static struct nand_ecclayout atmel_oobinfo_small = {
976 	.eccbytes = 4,
977 	.eccpos = {0, 1, 2, 3},
978 	.oobfree = {
979 		{6, 10}
980 	},
981 };
982 
983 /*
984  * Calculate HW ECC
985  *
986  * function called after a write
987  *
988  * mtd:        MTD block structure
989  * dat:        raw data (unused)
990  * ecc_code:   buffer for ECC
991  */
atmel_nand_calculate(struct mtd_info * mtd,const u_char * dat,unsigned char * ecc_code)992 static int atmel_nand_calculate(struct mtd_info *mtd,
993 		const u_char *dat, unsigned char *ecc_code)
994 {
995 	unsigned int ecc_value;
996 
997 	/* get the first 2 ECC bytes */
998 	ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
999 
1000 	ecc_code[0] = ecc_value & 0xFF;
1001 	ecc_code[1] = (ecc_value >> 8) & 0xFF;
1002 
1003 	/* get the last 2 ECC bytes */
1004 	ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1005 
1006 	ecc_code[2] = ecc_value & 0xFF;
1007 	ecc_code[3] = (ecc_value >> 8) & 0xFF;
1008 
1009 	return 0;
1010 }
1011 
1012 /*
1013  * HW ECC read page function
1014  *
1015  * mtd:        mtd info structure
1016  * chip:       nand chip info structure
1017  * buf:        buffer to store read data
1018  * oob_required:    caller expects OOB data read to chip->oob_poi
1019  */
atmel_nand_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1020 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1021 				uint8_t *buf, int oob_required, int page)
1022 {
1023 	int eccsize = chip->ecc.size;
1024 	int eccbytes = chip->ecc.bytes;
1025 	uint32_t *eccpos = chip->ecc.layout->eccpos;
1026 	uint8_t *p = buf;
1027 	uint8_t *oob = chip->oob_poi;
1028 	uint8_t *ecc_pos;
1029 	int stat;
1030 
1031 	/* read the page */
1032 	chip->read_buf(mtd, p, eccsize);
1033 
1034 	/* move to ECC position if needed */
1035 	if (eccpos[0] != 0) {
1036 		/* This only works on large pages
1037 		 * because the ECC controller waits for
1038 		 * NAND_CMD_RNDOUTSTART after the
1039 		 * NAND_CMD_RNDOUT.
1040 		 * anyway, for small pages, the eccpos[0] == 0
1041 		 */
1042 		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1043 				mtd->writesize + eccpos[0], -1);
1044 	}
1045 
1046 	/* the ECC controller needs to read the ECC just after the data */
1047 	ecc_pos = oob + eccpos[0];
1048 	chip->read_buf(mtd, ecc_pos, eccbytes);
1049 
1050 	/* check if there's an error */
1051 	stat = chip->ecc.correct(mtd, p, oob, NULL);
1052 
1053 	if (stat < 0)
1054 		mtd->ecc_stats.failed++;
1055 	else
1056 		mtd->ecc_stats.corrected += stat;
1057 
1058 	/* get back to oob start (end of page) */
1059 	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1060 
1061 	/* read the oob */
1062 	chip->read_buf(mtd, oob, mtd->oobsize);
1063 
1064 	return 0;
1065 }
1066 
1067 /*
1068  * HW ECC Correction
1069  *
1070  * function called after a read
1071  *
1072  * mtd:        MTD block structure
1073  * dat:        raw data read from the chip
1074  * read_ecc:   ECC from the chip (unused)
1075  * isnull:     unused
1076  *
1077  * Detect and correct a 1 bit error for a page
1078  */
atmel_nand_correct(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * isnull)1079 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1080 		u_char *read_ecc, u_char *isnull)
1081 {
1082 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
1083 	unsigned int ecc_status;
1084 	unsigned int ecc_word, ecc_bit;
1085 
1086 	/* get the status from the Status Register */
1087 	ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1088 
1089 	/* if there's no error */
1090 	if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1091 		return 0;
1092 
1093 	/* get error bit offset (4 bits) */
1094 	ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1095 	/* get word address (12 bits) */
1096 	ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1097 	ecc_word >>= 4;
1098 
1099 	/* if there are multiple errors */
1100 	if (ecc_status & ATMEL_ECC_MULERR) {
1101 		/* check if it is a freshly erased block
1102 		 * (filled with 0xff) */
1103 		if ((ecc_bit == ATMEL_ECC_BITADDR)
1104 				&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1105 			/* the block has just been erased, return OK */
1106 			return 0;
1107 		}
1108 		/* it doesn't seems to be a freshly
1109 		 * erased block.
1110 		 * We can't correct so many errors */
1111 		dev_warn(host->dev, "atmel_nand : multiple errors detected."
1112 				" Unable to correct.\n");
1113 		return -EBADMSG;
1114 	}
1115 
1116 	/* if there's a single bit error : we can correct it */
1117 	if (ecc_status & ATMEL_ECC_ECCERR) {
1118 		/* there's nothing much to do here.
1119 		 * the bit error is on the ECC itself.
1120 		 */
1121 		dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1122 				" Nothing to correct\n");
1123 		return 0;
1124 	}
1125 
1126 	dev_warn(host->dev, "atmel_nand : one bit error on data."
1127 			" (word offset in the page :"
1128 			" 0x%x bit offset : 0x%x)\n",
1129 			ecc_word, ecc_bit);
1130 	/* correct the error */
1131 	if (nand_chip->options & NAND_BUSWIDTH_16) {
1132 		/* 16 bits words */
1133 		((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1134 	} else {
1135 		/* 8 bits words */
1136 		dat[ecc_word] ^= (1 << ecc_bit);
1137 	}
1138 	dev_warn(host->dev, "atmel_nand : error corrected\n");
1139 	return 1;
1140 }
1141 
1142 /*
1143  * Enable HW ECC : unused on most chips
1144  */
atmel_nand_hwctl(struct mtd_info * mtd,int mode)1145 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1146 {
1147 }
1148 
atmel_hwecc_nand_init_param(struct nand_chip * nand,struct mtd_info * mtd)1149 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1150 {
1151 	nand->ecc.mode = NAND_ECC_HW;
1152 	nand->ecc.calculate = atmel_nand_calculate;
1153 	nand->ecc.correct = atmel_nand_correct;
1154 	nand->ecc.hwctl = atmel_nand_hwctl;
1155 	nand->ecc.read_page = atmel_nand_read_page;
1156 	nand->ecc.bytes = 4;
1157 	nand->ecc.strength = 4;
1158 
1159 	if (nand->ecc.mode == NAND_ECC_HW) {
1160 		/* ECC is calculated for the whole page (1 step) */
1161 		nand->ecc.size = mtd->writesize;
1162 
1163 		/* set ECC page size and oob layout */
1164 		switch (mtd->writesize) {
1165 		case 512:
1166 			nand->ecc.layout = &atmel_oobinfo_small;
1167 			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1168 					ATMEL_ECC_PAGESIZE_528);
1169 			break;
1170 		case 1024:
1171 			nand->ecc.layout = &atmel_oobinfo_large;
1172 			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1173 					ATMEL_ECC_PAGESIZE_1056);
1174 			break;
1175 		case 2048:
1176 			nand->ecc.layout = &atmel_oobinfo_large;
1177 			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1178 					ATMEL_ECC_PAGESIZE_2112);
1179 			break;
1180 		case 4096:
1181 			nand->ecc.layout = &atmel_oobinfo_large;
1182 			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1183 					ATMEL_ECC_PAGESIZE_4224);
1184 			break;
1185 		default:
1186 			/* page size not handled by HW ECC */
1187 			/* switching back to soft ECC */
1188 			nand->ecc.mode = NAND_ECC_SOFT;
1189 			nand->ecc.calculate = NULL;
1190 			nand->ecc.correct = NULL;
1191 			nand->ecc.hwctl = NULL;
1192 			nand->ecc.read_page = NULL;
1193 			nand->ecc.postpad = 0;
1194 			nand->ecc.prepad = 0;
1195 			nand->ecc.bytes = 0;
1196 			break;
1197 		}
1198 	}
1199 
1200 	return 0;
1201 }
1202 
1203 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1204 
1205 #endif /* CONFIG_ATMEL_NAND_HWECC */
1206 
at91_nand_hwcontrol(struct mtd_info * mtd,int cmd,unsigned int ctrl)1207 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1208 					 int cmd, unsigned int ctrl)
1209 {
1210 	struct nand_chip *this = mtd_to_nand(mtd);
1211 
1212 	if (ctrl & NAND_CTRL_CHANGE) {
1213 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1214 		IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1215 			     | CONFIG_SYS_NAND_MASK_CLE);
1216 
1217 		if (ctrl & NAND_CLE)
1218 			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1219 		if (ctrl & NAND_ALE)
1220 			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1221 
1222 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1223 		at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1224 				    !(ctrl & NAND_NCE));
1225 #endif
1226 		this->IO_ADDR_W = (void *) IO_ADDR_W;
1227 	}
1228 
1229 	if (cmd != NAND_CMD_NONE)
1230 		writeb(cmd, this->IO_ADDR_W);
1231 }
1232 
1233 #ifdef CONFIG_SYS_NAND_READY_PIN
at91_nand_ready(struct mtd_info * mtd)1234 static int at91_nand_ready(struct mtd_info *mtd)
1235 {
1236 	return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1237 }
1238 #endif
1239 
1240 #ifdef CONFIG_SPL_BUILD
1241 /* The following code is for SPL */
1242 static struct mtd_info *mtd;
1243 static struct nand_chip nand_chip;
1244 
nand_command(int block,int page,uint32_t offs,u8 cmd)1245 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1246 {
1247 	struct nand_chip *this = mtd_to_nand(mtd);
1248 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1249 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
1250 			unsigned int ctrl) = this->cmd_ctrl;
1251 
1252 	while (!this->dev_ready(mtd))
1253 		;
1254 
1255 	if (cmd == NAND_CMD_READOOB) {
1256 		offs += CONFIG_SYS_NAND_PAGE_SIZE;
1257 		cmd = NAND_CMD_READ0;
1258 	}
1259 
1260 	hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1261 
1262 	if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1263 		offs >>= 1;
1264 
1265 	hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1266 	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1267 	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1268 	hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1269 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1270 	hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1271 #endif
1272 	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1273 
1274 	hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1275 	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1276 
1277 	while (!this->dev_ready(mtd))
1278 		;
1279 
1280 	return 0;
1281 }
1282 
nand_is_bad_block(int block)1283 static int nand_is_bad_block(int block)
1284 {
1285 	struct nand_chip *this = mtd_to_nand(mtd);
1286 
1287 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1288 
1289 	if (this->options & NAND_BUSWIDTH_16) {
1290 		if (readw(this->IO_ADDR_R) != 0xffff)
1291 			return 1;
1292 	} else {
1293 		if (readb(this->IO_ADDR_R) != 0xff)
1294 			return 1;
1295 	}
1296 
1297 	return 0;
1298 }
1299 
1300 #ifdef CONFIG_SPL_NAND_ECC
1301 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1302 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1303 		  CONFIG_SYS_NAND_ECCSIZE)
1304 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1305 
nand_read_page(int block,int page,void * dst)1306 static int nand_read_page(int block, int page, void *dst)
1307 {
1308 	struct nand_chip *this = mtd_to_nand(mtd);
1309 	u_char ecc_calc[ECCTOTAL];
1310 	u_char ecc_code[ECCTOTAL];
1311 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1312 	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1313 	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1314 	int eccsteps = ECCSTEPS;
1315 	int i;
1316 	uint8_t *p = dst;
1317 	nand_command(block, page, 0, NAND_CMD_READ0);
1318 
1319 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1320 		if (this->ecc.mode != NAND_ECC_SOFT)
1321 			this->ecc.hwctl(mtd, NAND_ECC_READ);
1322 		this->read_buf(mtd, p, eccsize);
1323 		this->ecc.calculate(mtd, p, &ecc_calc[i]);
1324 	}
1325 	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1326 
1327 	for (i = 0; i < ECCTOTAL; i++)
1328 		ecc_code[i] = oob_data[nand_ecc_pos[i]];
1329 
1330 	eccsteps = ECCSTEPS;
1331 	p = dst;
1332 
1333 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1334 		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1335 
1336 	return 0;
1337 }
1338 
spl_nand_erase_one(int block,int page)1339 int spl_nand_erase_one(int block, int page)
1340 {
1341 	struct nand_chip *this = mtd_to_nand(mtd);
1342 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
1343 			unsigned int ctrl) = this->cmd_ctrl;
1344 	int page_addr;
1345 
1346 	if (nand_chip.select_chip)
1347 		nand_chip.select_chip(mtd, 0);
1348 
1349 	page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1350 	hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1351 	/* Row address */
1352 	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1353 	hwctrl(mtd, ((page_addr >> 8) & 0xff),
1354 	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1355 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1356 	/* One more address cycle for devices > 128MiB */
1357 	hwctrl(mtd, (page_addr >> 16) & 0x0f,
1358 	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1359 #endif
1360 	hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1361 
1362 	while (!this->dev_ready(mtd))
1363 		;
1364 
1365 	nand_deselect();
1366 
1367 	return 0;
1368 }
1369 #else
nand_read_page(int block,int page,void * dst)1370 static int nand_read_page(int block, int page, void *dst)
1371 {
1372 	struct nand_chip *this = mtd_to_nand(mtd);
1373 
1374 	nand_command(block, page, 0, NAND_CMD_READ0);
1375 	atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1376 
1377 	return 0;
1378 }
1379 #endif /* CONFIG_SPL_NAND_ECC */
1380 
at91_nand_wait_ready(struct mtd_info * mtd)1381 int at91_nand_wait_ready(struct mtd_info *mtd)
1382 {
1383 	struct nand_chip *this = mtd_to_nand(mtd);
1384 
1385 	udelay(this->chip_delay);
1386 
1387 	return 1;
1388 }
1389 
board_nand_init(struct nand_chip * nand)1390 int board_nand_init(struct nand_chip *nand)
1391 {
1392 	int ret = 0;
1393 
1394 	nand->ecc.mode = NAND_ECC_SOFT;
1395 #ifdef CONFIG_SYS_NAND_DBW_16
1396 	nand->options = NAND_BUSWIDTH_16;
1397 	nand->read_buf = nand_read_buf16;
1398 #else
1399 	nand->read_buf = nand_read_buf;
1400 #endif
1401 	nand->cmd_ctrl = at91_nand_hwcontrol;
1402 #ifdef CONFIG_SYS_NAND_READY_PIN
1403 	nand->dev_ready = at91_nand_ready;
1404 #else
1405 	nand->dev_ready = at91_nand_wait_ready;
1406 #endif
1407 	nand->chip_delay = 20;
1408 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1409 	nand->bbt_options |= NAND_BBT_USE_FLASH;
1410 #endif
1411 
1412 #ifdef CONFIG_ATMEL_NAND_HWECC
1413 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1414 	ret = atmel_pmecc_nand_init_params(nand, mtd);
1415 #endif
1416 #endif
1417 
1418 	return ret;
1419 }
1420 
nand_init(void)1421 void nand_init(void)
1422 {
1423 	mtd = nand_to_mtd(&nand_chip);
1424 	mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1425 	mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1426 	nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1427 	nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1428 	board_nand_init(&nand_chip);
1429 
1430 #ifdef CONFIG_SPL_NAND_ECC
1431 	if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1432 		nand_chip.ecc.calculate = nand_calculate_ecc;
1433 		nand_chip.ecc.correct = nand_correct_data;
1434 	}
1435 #endif
1436 
1437 	if (nand_chip.select_chip)
1438 		nand_chip.select_chip(mtd, 0);
1439 }
1440 
nand_deselect(void)1441 void nand_deselect(void)
1442 {
1443 	if (nand_chip.select_chip)
1444 		nand_chip.select_chip(mtd, -1);
1445 }
1446 
1447 #include "nand_spl_loaders.c"
1448 
1449 #else
1450 
1451 #ifndef CONFIG_SYS_NAND_BASE_LIST
1452 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1453 #endif
1454 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1455 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1456 
atmel_nand_chip_init(int devnum,ulong base_addr)1457 int atmel_nand_chip_init(int devnum, ulong base_addr)
1458 {
1459 	int ret;
1460 	struct nand_chip *nand = &nand_chip[devnum];
1461 	struct mtd_info *mtd = nand_to_mtd(nand);
1462 
1463 	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1464 
1465 #ifdef CONFIG_NAND_ECC_BCH
1466 	nand->ecc.mode = NAND_ECC_SOFT_BCH;
1467 #else
1468 	nand->ecc.mode = NAND_ECC_SOFT;
1469 #endif
1470 #ifdef CONFIG_SYS_NAND_DBW_16
1471 	nand->options = NAND_BUSWIDTH_16;
1472 #endif
1473 	nand->cmd_ctrl = at91_nand_hwcontrol;
1474 #ifdef CONFIG_SYS_NAND_READY_PIN
1475 	nand->dev_ready = at91_nand_ready;
1476 #endif
1477 	nand->chip_delay = 75;
1478 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1479 	nand->bbt_options |= NAND_BBT_USE_FLASH;
1480 #endif
1481 
1482 	ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1483 	if (ret)
1484 		return ret;
1485 
1486 #ifdef CONFIG_ATMEL_NAND_HWECC
1487 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1488 	ret = atmel_pmecc_nand_init_params(nand, mtd);
1489 #else
1490 	ret = atmel_hwecc_nand_init_param(nand, mtd);
1491 #endif
1492 	if (ret)
1493 		return ret;
1494 #endif
1495 
1496 	ret = nand_scan_tail(mtd);
1497 	if (!ret)
1498 		nand_register(devnum, mtd);
1499 
1500 	return ret;
1501 }
1502 
board_nand_init(void)1503 void board_nand_init(void)
1504 {
1505 	int i;
1506 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1507 		if (atmel_nand_chip_init(i, base_addr[i]))
1508 			dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1509 				i);
1510 }
1511 #endif /* CONFIG_SPL_BUILD */
1512