| /external/libgsm/src/ |
| D | short_term.c | 275 register word sri, tmp1, tmp2; variable
328 register float sri = *wt++; variable
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| /external/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1374 sri d0, d0, #1 define
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1374 sri d0, d0, #1 define
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| /external/tensorflow/tensorflow/core/common_runtime/ |
| D | hierarchical_tree_broadcaster.cc | 179 for (int sri = 0; sri < num_subdivs; sri++) { in InitializeCollectiveParams() local
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 802 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { in runTargetDesc() local
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| D | CodeGenRegisters.cpp | 770 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { in computeInferredRegisterClasses() local
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| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1719 __ sri(d14, d14, 49); in GenerateTestSequenceNEON() local
1720 __ sri(v23.V16B(), v8.V16B(), 4); in GenerateTestSequenceNEON() local
1721 __ sri(v20.V2D(), v13.V2D(), 20); in GenerateTestSequenceNEON() local
1722 __ sri(v16.V2S(), v2.V2S(), 24); in GenerateTestSequenceNEON() local
1723 __ sri(v5.V4H(), v23.V4H(), 11); in GenerateTestSequenceNEON() local
1724 __ sri(v27.V4S(), v15.V4S(), 23); in GenerateTestSequenceNEON() local
1725 __ sri(v19.V8B(), v29.V8B(), 4); in GenerateTestSequenceNEON() local
1726 __ sri(v7.V8H(), v29.V8H(), 3); in GenerateTestSequenceNEON() local
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| /external/nist-sip/java/gov/nist/javax/sip/stack/ |
| D | SIPTransactionStack.java | 1313 ServerResponseInterface sri = sipMessageFactory.newSIPServerResponse( in newSIPServerResponse() local
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 2081 void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) { in sri() function in v8::internal::Assembler
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| D | simulator-logic-arm64.cc | 1434 LogicVRegister Simulator::sri(VectorFormat vform, LogicVRegister dst, in sri() function in v8::internal::Simulator
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 4794 void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) { in sri() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 1575 LogicVRegister Simulator::sri(VectorFormat vform, in sri() function in vixl::aarch64::Simulator
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