1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <stdio.h>
25
26 #include "CUnit/Basic.h"
27
28 #include "util_math.h"
29
30 #include "amdgpu_test.h"
31 #include "decode_messages.h"
32 #include "amdgpu_drm.h"
33 #include "amdgpu_internal.h"
34
35 #define IB_SIZE 4096
36 #define MAX_RESOURCES 16
37
38 static amdgpu_device_handle device_handle;
39 static uint32_t major_version;
40 static uint32_t minor_version;
41 static uint32_t family_id;
42 static uint32_t chip_rev;
43 static uint32_t chip_id;
44
45 static amdgpu_context_handle context_handle;
46 static amdgpu_bo_handle ib_handle;
47 static uint64_t ib_mc_address;
48 static uint32_t *ib_cpu;
49 static amdgpu_va_handle ib_va_handle;
50
51 static amdgpu_bo_handle resources[MAX_RESOURCES];
52 static unsigned num_resources;
53
54 static void amdgpu_cs_uvd_create(void);
55 static void amdgpu_cs_uvd_decode(void);
56 static void amdgpu_cs_uvd_destroy(void);
57
58 CU_TestInfo cs_tests[] = {
59 { "UVD create", amdgpu_cs_uvd_create },
60 { "UVD decode", amdgpu_cs_uvd_decode },
61 { "UVD destroy", amdgpu_cs_uvd_destroy },
62 CU_TEST_INFO_NULL,
63 };
64
suite_cs_tests_enable(void)65 CU_BOOL suite_cs_tests_enable(void)
66 {
67 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
68 &minor_version, &device_handle))
69 return CU_FALSE;
70
71 family_id = device_handle->info.family_id;
72
73 if (amdgpu_device_deinitialize(device_handle))
74 return CU_FALSE;
75
76
77 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
78 printf("\n\nThe ASIC NOT support UVD, suite disabled\n");
79 return CU_FALSE;
80 }
81
82 return CU_TRUE;
83 }
84
suite_cs_tests_init(void)85 int suite_cs_tests_init(void)
86 {
87 amdgpu_bo_handle ib_result_handle;
88 void *ib_result_cpu;
89 uint64_t ib_result_mc_address;
90 amdgpu_va_handle ib_result_va_handle;
91 int r;
92
93 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
94 &minor_version, &device_handle);
95 if (r) {
96 if ((r == -EACCES) && (errno == EACCES))
97 printf("\n\nError:%s. "
98 "Hint:Try to run this test program as root.",
99 strerror(errno));
100
101 return CUE_SINIT_FAILED;
102 }
103
104 family_id = device_handle->info.family_id;
105 /* VI asic POLARIS10/11 have specific external_rev_id */
106 chip_rev = device_handle->info.chip_rev;
107 chip_id = device_handle->info.chip_external_rev;
108
109 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
110 if (r)
111 return CUE_SINIT_FAILED;
112
113 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
114 AMDGPU_GEM_DOMAIN_GTT, 0,
115 &ib_result_handle, &ib_result_cpu,
116 &ib_result_mc_address,
117 &ib_result_va_handle);
118 if (r)
119 return CUE_SINIT_FAILED;
120
121 ib_handle = ib_result_handle;
122 ib_mc_address = ib_result_mc_address;
123 ib_cpu = ib_result_cpu;
124 ib_va_handle = ib_result_va_handle;
125
126 return CUE_SUCCESS;
127 }
128
suite_cs_tests_clean(void)129 int suite_cs_tests_clean(void)
130 {
131 int r;
132
133 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
134 ib_mc_address, IB_SIZE);
135 if (r)
136 return CUE_SCLEAN_FAILED;
137
138 r = amdgpu_cs_ctx_free(context_handle);
139 if (r)
140 return CUE_SCLEAN_FAILED;
141
142 r = amdgpu_device_deinitialize(device_handle);
143 if (r)
144 return CUE_SCLEAN_FAILED;
145
146 return CUE_SUCCESS;
147 }
148
submit(unsigned ndw,unsigned ip)149 static int submit(unsigned ndw, unsigned ip)
150 {
151 struct amdgpu_cs_request ibs_request = {0};
152 struct amdgpu_cs_ib_info ib_info = {0};
153 struct amdgpu_cs_fence fence_status = {0};
154 uint32_t expired;
155 int r;
156
157 ib_info.ib_mc_address = ib_mc_address;
158 ib_info.size = ndw;
159
160 ibs_request.ip_type = ip;
161
162 r = amdgpu_bo_list_create(device_handle, num_resources, resources,
163 NULL, &ibs_request.resources);
164 if (r)
165 return r;
166
167 ibs_request.number_of_ibs = 1;
168 ibs_request.ibs = &ib_info;
169 ibs_request.fence_info.handle = NULL;
170
171 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
172 if (r)
173 return r;
174
175 r = amdgpu_bo_list_destroy(ibs_request.resources);
176 if (r)
177 return r;
178
179 fence_status.context = context_handle;
180 fence_status.ip_type = ip;
181 fence_status.fence = ibs_request.seq_no;
182
183 r = amdgpu_cs_query_fence_status(&fence_status,
184 AMDGPU_TIMEOUT_INFINITE,
185 0, &expired);
186 if (r)
187 return r;
188
189 return 0;
190 }
191
uvd_cmd(uint64_t addr,unsigned cmd,int * idx)192 static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
193 {
194 ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4;
195 ib_cpu[(*idx)++] = addr;
196 ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5;
197 ib_cpu[(*idx)++] = addr >> 32;
198 ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3;
199 ib_cpu[(*idx)++] = cmd << 1;
200 }
201
amdgpu_cs_uvd_create(void)202 static void amdgpu_cs_uvd_create(void)
203 {
204 struct amdgpu_bo_alloc_request req = {0};
205 amdgpu_bo_handle buf_handle;
206 uint64_t va = 0;
207 amdgpu_va_handle va_handle;
208 void *msg;
209 int i, r;
210
211 req.alloc_size = 4*1024;
212 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
213
214 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
215 CU_ASSERT_EQUAL(r, 0);
216
217 r = amdgpu_va_range_alloc(device_handle,
218 amdgpu_gpu_va_range_general,
219 4096, 1, 0, &va,
220 &va_handle, 0);
221 CU_ASSERT_EQUAL(r, 0);
222
223 r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
224 CU_ASSERT_EQUAL(r, 0);
225
226 r = amdgpu_bo_cpu_map(buf_handle, &msg);
227 CU_ASSERT_EQUAL(r, 0);
228
229 memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
230
231 if (family_id >= AMDGPU_FAMILY_VI) {
232 ((uint8_t*)msg)[0x10] = 7;
233 /* chip beyond polaris 10/11 */
234 if ((family_id == AMDGPU_FAMILY_AI) ||
235 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
236 chip_id == chip_rev+0x64)) {
237 /* dpb size */
238 ((uint8_t*)msg)[0x28] = 0x00;
239 ((uint8_t*)msg)[0x29] = 0x94;
240 ((uint8_t*)msg)[0x2A] = 0x6B;
241 ((uint8_t*)msg)[0x2B] = 0x00;
242 }
243 }
244
245 r = amdgpu_bo_cpu_unmap(buf_handle);
246 CU_ASSERT_EQUAL(r, 0);
247
248 num_resources = 0;
249 resources[num_resources++] = buf_handle;
250 resources[num_resources++] = ib_handle;
251
252 i = 0;
253 uvd_cmd(va, 0x0, &i);
254 for (; i % 16; ++i)
255 ib_cpu[i] = 0x80000000;
256
257 r = submit(i, AMDGPU_HW_IP_UVD);
258 CU_ASSERT_EQUAL(r, 0);
259
260 r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP);
261 CU_ASSERT_EQUAL(r, 0);
262
263 r = amdgpu_va_range_free(va_handle);
264 CU_ASSERT_EQUAL(r, 0);
265
266 r = amdgpu_bo_free(buf_handle);
267 CU_ASSERT_EQUAL(r, 0);
268 }
269
amdgpu_cs_uvd_decode(void)270 static void amdgpu_cs_uvd_decode(void)
271 {
272 const unsigned dpb_size = 15923584, dt_size = 737280;
273 uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
274 struct amdgpu_bo_alloc_request req = {0};
275 amdgpu_bo_handle buf_handle;
276 amdgpu_va_handle va_handle;
277 uint64_t va = 0;
278 uint64_t sum;
279 uint8_t *ptr;
280 int i, r;
281
282 req.alloc_size = 4*1024; /* msg */
283 req.alloc_size += 4*1024; /* fb */
284 if (family_id >= AMDGPU_FAMILY_VI)
285 req.alloc_size += 4096; /*it_scaling_table*/
286 req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
287 req.alloc_size += ALIGN(dpb_size, 4*1024);
288 req.alloc_size += ALIGN(dt_size, 4*1024);
289
290 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
291
292 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
293 CU_ASSERT_EQUAL(r, 0);
294
295 r = amdgpu_va_range_alloc(device_handle,
296 amdgpu_gpu_va_range_general,
297 req.alloc_size, 1, 0, &va,
298 &va_handle, 0);
299 CU_ASSERT_EQUAL(r, 0);
300
301 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
302 AMDGPU_VA_OP_MAP);
303 CU_ASSERT_EQUAL(r, 0);
304
305 r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
306 CU_ASSERT_EQUAL(r, 0);
307
308 memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg));
309 memcpy(ptr + sizeof(uvd_decode_msg), avc_decode_msg, sizeof(avc_decode_msg));
310
311 if (family_id >= AMDGPU_FAMILY_VI) {
312 ptr[0x10] = 7;
313 ptr[0x98] = 0x00;
314 ptr[0x99] = 0x02;
315 /* chip beyond polaris10/11 */
316 if ((family_id == AMDGPU_FAMILY_AI) ||
317 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
318 chip_id == chip_rev+0x64)) {
319 /* dpb size */
320 ptr[0x24] = 0x00;
321 ptr[0x25] = 0x94;
322 ptr[0x26] = 0x6B;
323 ptr[0x27] = 0x00;
324 /*ctx size */
325 ptr[0x2C] = 0x00;
326 ptr[0x2D] = 0xAF;
327 ptr[0x2E] = 0x50;
328 ptr[0x2F] = 0x00;
329 }
330 }
331
332 ptr += 4*1024;
333 memset(ptr, 0, 4*1024);
334 if (family_id >= AMDGPU_FAMILY_VI) {
335 ptr += 4*1024;
336 memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
337 }
338
339 ptr += 4*1024;
340 memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
341
342 ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
343 memset(ptr, 0, dpb_size);
344
345 ptr += ALIGN(dpb_size, 4*1024);
346 memset(ptr, 0, dt_size);
347
348 num_resources = 0;
349 resources[num_resources++] = buf_handle;
350 resources[num_resources++] = ib_handle;
351
352 msg_addr = va;
353 fb_addr = msg_addr + 4*1024;
354 if (family_id >= AMDGPU_FAMILY_VI) {
355 it_addr = fb_addr + 4*1024;
356 bs_addr = it_addr + 4*1024;
357 } else
358 bs_addr = fb_addr + 4*1024;
359 dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
360
361 if (family_id >= AMDGPU_FAMILY_VI) {
362 if ((family_id == AMDGPU_FAMILY_AI) ||
363 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
364 chip_id == chip_rev+0x64)) {
365 ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
366 }
367 }
368
369 dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
370
371 i = 0;
372 uvd_cmd(msg_addr, 0x0, &i);
373 uvd_cmd(dpb_addr, 0x1, &i);
374 uvd_cmd(dt_addr, 0x2, &i);
375 uvd_cmd(fb_addr, 0x3, &i);
376 uvd_cmd(bs_addr, 0x100, &i);
377
378 if (family_id >= AMDGPU_FAMILY_VI) {
379 uvd_cmd(it_addr, 0x204, &i);
380 if ((family_id == AMDGPU_FAMILY_AI) ||
381 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
382 chip_id == chip_rev+0x64))
383 uvd_cmd(ctx_addr, 0x206, &i);
384 }
385
386 ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
387 ib_cpu[i++] = 0x1;
388 for (; i % 16; ++i)
389 ib_cpu[i] = 0x80000000;
390
391 r = submit(i, AMDGPU_HW_IP_UVD);
392 CU_ASSERT_EQUAL(r, 0);
393
394 /* TODO: use a real CRC32 */
395 for (i = 0, sum = 0; i < dt_size; ++i)
396 sum += ptr[i];
397 CU_ASSERT_EQUAL(sum, SUM_DECODE);
398
399 r = amdgpu_bo_cpu_unmap(buf_handle);
400 CU_ASSERT_EQUAL(r, 0);
401
402 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
403 CU_ASSERT_EQUAL(r, 0);
404
405 r = amdgpu_va_range_free(va_handle);
406 CU_ASSERT_EQUAL(r, 0);
407
408 r = amdgpu_bo_free(buf_handle);
409 CU_ASSERT_EQUAL(r, 0);
410 }
411
amdgpu_cs_uvd_destroy(void)412 static void amdgpu_cs_uvd_destroy(void)
413 {
414 struct amdgpu_bo_alloc_request req = {0};
415 amdgpu_bo_handle buf_handle;
416 amdgpu_va_handle va_handle;
417 uint64_t va = 0;
418 void *msg;
419 int i, r;
420
421 req.alloc_size = 4*1024;
422 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
423
424 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
425 CU_ASSERT_EQUAL(r, 0);
426
427 r = amdgpu_va_range_alloc(device_handle,
428 amdgpu_gpu_va_range_general,
429 req.alloc_size, 1, 0, &va,
430 &va_handle, 0);
431 CU_ASSERT_EQUAL(r, 0);
432
433 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
434 AMDGPU_VA_OP_MAP);
435 CU_ASSERT_EQUAL(r, 0);
436
437 r = amdgpu_bo_cpu_map(buf_handle, &msg);
438 CU_ASSERT_EQUAL(r, 0);
439
440 memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg));
441 if (family_id >= AMDGPU_FAMILY_VI)
442 ((uint8_t*)msg)[0x10] = 7;
443
444 r = amdgpu_bo_cpu_unmap(buf_handle);
445 CU_ASSERT_EQUAL(r, 0);
446
447 num_resources = 0;
448 resources[num_resources++] = buf_handle;
449 resources[num_resources++] = ib_handle;
450
451 i = 0;
452 uvd_cmd(va, 0x0, &i);
453 for (; i % 16; ++i)
454 ib_cpu[i] = 0x80000000;
455
456 r = submit(i, AMDGPU_HW_IP_UVD);
457 CU_ASSERT_EQUAL(r, 0);
458
459 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
460 CU_ASSERT_EQUAL(r, 0);
461
462 r = amdgpu_va_range_free(va_handle);
463 CU_ASSERT_EQUAL(r, 0);
464
465 r = amdgpu_bo_free(buf_handle);
466 CU_ASSERT_EQUAL(r, 0);
467 }
468