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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <common.h>
7 #include <errno.h>
8 
9 #include <asm/io.h>
10 #include <asm/types.h>
11 #include <asm/arch/flow.h>
12 #include <asm/arch/powergate.h>
13 #include <asm/arch/tegra.h>
14 
15 #define PWRGATE_TOGGLE 0x30
16 #define  PWRGATE_TOGGLE_START (1 << 8)
17 
18 #define REMOVE_CLAMPING 0x34
19 
20 #define PWRGATE_STATUS 0x38
21 
tegra_powergate_set(enum tegra_powergate id,bool state)22 static int tegra_powergate_set(enum tegra_powergate id, bool state)
23 {
24 	u32 value, mask = state ? (1 << id) : 0, old_mask;
25 	unsigned long start, timeout = 25;
26 
27 	value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
28 	old_mask = value & (1 << id);
29 
30 	if (mask == old_mask)
31 		return 0;
32 
33 	writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
34 
35 	start = get_timer(0);
36 
37 	while (get_timer(start) < timeout) {
38 		value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
39 		if ((value & (1 << id)) == mask)
40 			return 0;
41 	}
42 
43 	return -ETIMEDOUT;
44 }
45 
tegra_powergate_power_on(enum tegra_powergate id)46 int tegra_powergate_power_on(enum tegra_powergate id)
47 {
48 	return tegra_powergate_set(id, true);
49 }
50 
tegra_powergate_power_off(enum tegra_powergate id)51 int tegra_powergate_power_off(enum tegra_powergate id)
52 {
53 	return tegra_powergate_set(id, false);
54 }
55 
tegra_powergate_remove_clamping(enum tegra_powergate id)56 static int tegra_powergate_remove_clamping(enum tegra_powergate id)
57 {
58 	unsigned long value;
59 
60 	/*
61 	 * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
62 	 * partitions reversed. This was originally introduced on Tegra20 but
63 	 * has since been carried forward for backwards-compatibility.
64 	 */
65 	if (id == TEGRA_POWERGATE_VDEC)
66 		value = 1 << TEGRA_POWERGATE_PCIE;
67 	else if (id == TEGRA_POWERGATE_PCIE)
68 		value = 1 << TEGRA_POWERGATE_VDEC;
69 	else
70 		value = 1 << id;
71 
72 	writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
73 
74 	return 0;
75 }
76 
tegra_powergate_ram_repair(void)77 static void tegra_powergate_ram_repair(void)
78 {
79 #ifdef CONFIG_TEGRA124
80 	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
81 
82 	/* Request RAM repair for cluster 0 and wait until complete */
83 	setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
84 	while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
85 		;
86 
87 	/* Same for cluster 1 */
88 	setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
89 	while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
90 		;
91 #endif
92 }
93 
tegra_powergate_sequence_power_up(enum tegra_powergate id,enum periph_id periph)94 int tegra_powergate_sequence_power_up(enum tegra_powergate id,
95 				      enum periph_id periph)
96 {
97 	int err;
98 
99 	tegra_powergate_ram_repair();
100 	reset_set_enable(periph, 1);
101 
102 	err = tegra_powergate_power_on(id);
103 	if (err < 0)
104 		return err;
105 
106 	clock_enable(periph);
107 
108 	udelay(10);
109 
110 	err = tegra_powergate_remove_clamping(id);
111 	if (err < 0)
112 		return err;
113 
114 	udelay(10);
115 
116 	reset_set_enable(periph, 0);
117 
118 	return 0;
119 }
120