1 /*
2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <bl_common.h>
9 #include <debug.h>
10 #include <platform_def.h>
11 #include <smmu.h>
12 #include <string.h>
13 #include <tegra_private.h>
14
15 /* SMMU IDs currently supported by the driver */
16 enum {
17 TEGRA_SMMU0,
18 TEGRA_SMMU1,
19 TEGRA_SMMU2
20 };
21
tegra_smmu_read_32(uint32_t smmu_id,uint32_t off)22 static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
23 {
24 #if defined(TEGRA_SMMU0_BASE)
25 if (smmu_id == TEGRA_SMMU0)
26 return mmio_read_32(TEGRA_SMMU0_BASE + off);
27 #endif
28
29 #if defined(TEGRA_SMMU1_BASE)
30 if (smmu_id == TEGRA_SMMU1)
31 return mmio_read_32(TEGRA_SMMU1_BASE + off);
32 #endif
33
34 #if defined(TEGRA_SMMU2_BASE)
35 if (smmu_id == TEGRA_SMMU2)
36 return mmio_read_32(TEGRA_SMMU2_BASE + off);
37 #endif
38
39 return 0;
40 }
41
tegra_smmu_write_32(uint32_t smmu_id,uint32_t off,uint32_t val)42 static void tegra_smmu_write_32(uint32_t smmu_id,
43 uint32_t off, uint32_t val)
44 {
45 #if defined(TEGRA_SMMU0_BASE)
46 if (smmu_id == TEGRA_SMMU0)
47 mmio_write_32(TEGRA_SMMU0_BASE + off, val);
48 #endif
49
50 #if defined(TEGRA_SMMU1_BASE)
51 if (smmu_id == TEGRA_SMMU1)
52 mmio_write_32(TEGRA_SMMU1_BASE + off, val);
53 #endif
54
55 #if defined(TEGRA_SMMU2_BASE)
56 if (smmu_id == TEGRA_SMMU2)
57 mmio_write_32(TEGRA_SMMU2_BASE + off, val);
58 #endif
59 }
60
61 /*
62 * Save SMMU settings before "System Suspend" to TZDRAM
63 */
tegra_smmu_save_context(uint64_t smmu_ctx_addr)64 void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
65 {
66 uint32_t i, num_entries = 0;
67 smmu_regs_t *smmu_ctx_regs;
68 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
69 uint64_t tzdram_base = params_from_bl2->tzdram_base;
70 uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
71 uint32_t reg_id1, pgshift, cb_size;
72
73 /* sanity check SMMU settings c*/
74 reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
75 pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
76 cb_size = (2 << pgshift) * \
77 (1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
78
79 assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
80 assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
81
82 /* get SMMU context table */
83 smmu_ctx_regs = plat_get_smmu_ctx();
84 assert(smmu_ctx_regs);
85
86 /*
87 * smmu_ctx_regs[0].val contains the size of the context table minus
88 * the last entry. Sanity check the table size before we start with
89 * the context save operation.
90 */
91 while (smmu_ctx_regs[num_entries].val != 0xFFFFFFFFU) {
92 num_entries++;
93 }
94
95 /* panic if the sizes do not match */
96 if (num_entries != smmu_ctx_regs[0].val)
97 panic();
98
99 /* save SMMU register values */
100 for (i = 1; i < num_entries; i++)
101 smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
102
103 /* increment by 1 to take care of the last entry */
104 num_entries++;
105
106 /* Save SMMU config settings */
107 memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
108 (sizeof(smmu_regs_t) * num_entries));
109
110 /* save the SMMU table address */
111 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,
112 (uint32_t)smmu_ctx_addr);
113 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI,
114 (uint32_t)(smmu_ctx_addr >> 32));
115 }
116
117 #define SMMU_NUM_CONTEXTS 64
118 #define SMMU_CONTEXT_BANK_MAX_IDX 64
119
120 /*
121 * Init SMMU during boot or "System Suspend" exit
122 */
tegra_smmu_init(void)123 void tegra_smmu_init(void)
124 {
125 uint32_t val, cb_idx, smmu_id, ctx_base;
126
127 for (smmu_id = 0; smmu_id < NUM_SMMU_DEVICES; smmu_id++) {
128 /* Program the SMMU pagesize and reset CACHE_LOCK bit */
129 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
130 val |= SMMU_GSR0_PGSIZE_64K;
131 val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
132 tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
133
134 /* reset CACHE LOCK bit for NS Aux. Config. Register */
135 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
136 val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
137 tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
138
139 /* disable TCU prefetch for all contexts */
140 ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS)
141 + SMMU_CBn_ACTLR;
142 for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
143 val = tegra_smmu_read_32(smmu_id,
144 ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
145 val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
146 tegra_smmu_write_32(smmu_id, ctx_base +
147 (SMMU_GSR0_PGSIZE_64K * cb_idx), val);
148 }
149
150 /* set CACHE LOCK bit for NS Aux. Config. Register */
151 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
152 val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
153 tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
154
155 /* set CACHE LOCK bit for S Aux. Config. Register */
156 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
157 val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
158 tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
159 }
160 }
161