1 /**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef SP_TEX_TILE_CACHE_H
29 #define SP_TEX_TILE_CACHE_H
30
31
32 #include "pipe/p_compiler.h"
33 #include "sp_limits.h"
34
35
36 struct softpipe_context;
37 struct softpipe_tex_tile_cache;
38
39
40 /**
41 * Cache tile size (width and height). This needs to be a power of two.
42 */
43 #define TEX_TILE_SIZE_LOG2 5
44 #define TEX_TILE_SIZE (1 << TEX_TILE_SIZE_LOG2)
45
46
47 #define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TEX_TILE_SIZE_LOG2)
48 #define TEX_Z_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1)
49
50 /**
51 * Texture tile address as a union for fast compares.
52 */
53 union tex_tile_address {
54 struct {
55 unsigned x:TEX_ADDR_BITS; /* 16K / TILE_SIZE */
56 unsigned y:TEX_ADDR_BITS; /* 16K / TILE_SIZE */
57 unsigned z:TEX_Z_BITS; /* 16K -- z not tiled */
58 unsigned level:4;
59 unsigned invalid:1;
60 } bits;
61 uint64_t value;
62 };
63
64
65 struct softpipe_tex_cached_tile
66 {
67 union tex_tile_address addr;
68 union {
69 float color[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
70 unsigned int colorui[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
71 int colori[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
72 } data;
73 };
74
75 /*
76 * The number of cache entries.
77 * Should not be decreased to lower than 16, and even that
78 * seems too low to avoid cache thrashing in some cases (because
79 * the cache is direct mapped, see tex_cache_pos() function).
80 */
81 #define NUM_TEX_TILE_ENTRIES 16
82
83 struct softpipe_tex_tile_cache
84 {
85 struct pipe_context *pipe;
86 struct pipe_transfer *transfer;
87 void *transfer_map;
88
89 struct pipe_resource *texture; /**< if caching a texture */
90 unsigned timestamp;
91
92 struct softpipe_tex_cached_tile entries[NUM_TEX_TILE_ENTRIES];
93
94 struct pipe_transfer *tex_trans;
95 void *tex_trans_map;
96 int tex_level, tex_z;
97
98 unsigned swizzle_r;
99 unsigned swizzle_g;
100 unsigned swizzle_b;
101 unsigned swizzle_a;
102 enum pipe_format format;
103
104 struct softpipe_tex_cached_tile *last_tile; /**< most recently retrieved tile */
105 };
106
107
108 extern struct softpipe_tex_tile_cache *
109 sp_create_tex_tile_cache( struct pipe_context *pipe );
110
111 extern void
112 sp_destroy_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
113
114 extern void
115 sp_tex_tile_cache_set_sampler_view(struct softpipe_tex_tile_cache *tc,
116 struct pipe_sampler_view *view);
117
118 void
119 sp_tex_tile_cache_validate_texture(struct softpipe_tex_tile_cache *tc);
120
121 extern void
122 sp_flush_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
123
124
125
126 extern const struct softpipe_tex_cached_tile *
127 sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
128 union tex_tile_address addr );
129
130 static inline union tex_tile_address
tex_tile_address(unsigned x,unsigned y,unsigned z,unsigned face,unsigned level)131 tex_tile_address( unsigned x,
132 unsigned y,
133 unsigned z,
134 unsigned face,
135 unsigned level )
136 {
137 union tex_tile_address addr;
138
139 addr.value = 0;
140 addr.bits.x = x / TEX_TILE_SIZE;
141 addr.bits.y = y / TEX_TILE_SIZE;
142 addr.bits.z = z;
143 addr.bits.level = level;
144
145 return addr;
146 }
147
148 /* Quickly retrieve tile if it matches last lookup.
149 */
150 static inline const struct softpipe_tex_cached_tile *
sp_get_cached_tile_tex(struct softpipe_tex_tile_cache * tc,union tex_tile_address addr)151 sp_get_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
152 union tex_tile_address addr )
153 {
154 if (tc->last_tile->addr.value == addr.value)
155 return tc->last_tile;
156
157 return sp_find_cached_tile_tex( tc, addr );
158 }
159
160
161 #endif /* SP_TEX_TILE_CACHE_H */
162
163