Searched defs:uaddlp (Results 1 – 5 of 5) sorted by relevance
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2206 __ uaddlp(v7.V1D(), v9.V2S()); in GenerateTestSequenceNEON() local
2207 __ uaddlp(v26.V2D(), v4.V4S()); in GenerateTestSequenceNEON() local
2208 __ uaddlp(v28.V2S(), v1.V4H()); in GenerateTestSequenceNEON() local
2209 __ uaddlp(v20.V4H(), v31.V8B()); in GenerateTestSequenceNEON() local
2210 __ uaddlp(v16.V4S(), v17.V8H()); in GenerateTestSequenceNEON() local
2211 __ uaddlp(v6.V8H(), v2.V16B()); in GenerateTestSequenceNEON() local
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 2388 void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) { in uaddlp() function in v8::internal::Assembler
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| D | simulator-logic-arm64.cc | 1962 LogicVRegister Simulator::uaddlp(VectorFormat vform, LogicVRegister dst, in uaddlp() function in v8::internal::Simulator
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 4473 void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) { in uaddlp() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 2192 LogicVRegister Simulator::uaddlp(VectorFormat vform, in uaddlp() function in vixl::aarch64::Simulator
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