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Searched defs:uaddlv (Results 1 – 9 of 9) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-across.s25 uaddlv d0, v1.4s define
Dneon-diagnostics.s3749 uaddlv d0, v1.2s define
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-across.s25 uaddlv d0, v1.4s define
Dneon-diagnostics.s3689 uaddlv d0, v1.2s define
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2212 __ uaddlv(d28, v22.V4S()); in GenerateTestSequenceNEON() local
2213 __ uaddlv(h0, v19.V16B()); in GenerateTestSequenceNEON() local
2214 __ uaddlv(h30, v30.V8B()); in GenerateTestSequenceNEON() local
2215 __ uaddlv(s24, v18.V4H()); in GenerateTestSequenceNEON() local
2216 __ uaddlv(s10, v0.V8H()); in GenerateTestSequenceNEON() local
/external/v8/src/arm64/
Dassembler-arm64.cc2412 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) { in uaddlv() function in v8::internal::Assembler
Dsimulator-logic-arm64.cc1202 LogicVRegister Simulator::uaddlv(VectorFormat vform, LogicVRegister dst, in uaddlv() function in v8::internal::Simulator
/external/vixl/src/aarch64/
Dassembler-aarch64.cc4507 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) { in uaddlv() function in vixl::aarch64::Assembler
Dlogic-aarch64.cc1282 LogicVRegister Simulator::uaddlv(VectorFormat vform, in uaddlv() function in vixl::aarch64::Simulator