1 /*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <gicv3.h>
9 #include <interrupt_props.h>
10 #include <platform.h>
11 #include <platform_def.h>
12
13 #include "uniphier.h"
14
15 static uintptr_t uniphier_rdistif_base_addrs[PLATFORM_CORE_COUNT];
16
17 static const interrupt_prop_t uniphier_interrupt_props[] = {
18 /* G0 interrupts */
19
20 /* SGI0 */
21 INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
22 GIC_INTR_CFG_EDGE),
23 /* SGI6 */
24 INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
25 GIC_INTR_CFG_EDGE),
26
27 /* G1S interrupts */
28
29 /* Timer */
30 INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
31 GIC_INTR_CFG_LEVEL),
32 /* SGI1 */
33 INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
34 GIC_INTR_CFG_EDGE),
35 /* SGI2 */
36 INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
37 GIC_INTR_CFG_EDGE),
38 /* SGI3 */
39 INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
40 GIC_INTR_CFG_EDGE),
41 /* SGI4 */
42 INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
43 GIC_INTR_CFG_EDGE),
44 /* SGI5 */
45 INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
46 GIC_INTR_CFG_EDGE),
47 /* SGI7 */
48 INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
49 GIC_INTR_CFG_EDGE)
50 };
51
uniphier_mpidr_to_core_pos(u_register_t mpidr)52 static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
53 {
54 return plat_core_pos_by_mpidr(mpidr);
55 }
56
57 static const struct gicv3_driver_data uniphier_gic_driver_data[] = {
58 [UNIPHIER_SOC_LD11] = {
59 .gicd_base = 0x5fe00000,
60 .gicr_base = 0x5fe40000,
61 .interrupt_props = uniphier_interrupt_props,
62 .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
63 .rdistif_num = PLATFORM_CORE_COUNT,
64 .rdistif_base_addrs = uniphier_rdistif_base_addrs,
65 .mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
66 },
67 [UNIPHIER_SOC_LD20] = {
68 .gicd_base = 0x5fe00000,
69 .gicr_base = 0x5fe80000,
70 .interrupt_props = uniphier_interrupt_props,
71 .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
72 .rdistif_num = PLATFORM_CORE_COUNT,
73 .rdistif_base_addrs = uniphier_rdistif_base_addrs,
74 .mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
75 },
76 [UNIPHIER_SOC_PXS3] = {
77 .gicd_base = 0x5fe00000,
78 .gicr_base = 0x5fe80000,
79 .interrupt_props = uniphier_interrupt_props,
80 .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
81 .rdistif_num = PLATFORM_CORE_COUNT,
82 .rdistif_base_addrs = uniphier_rdistif_base_addrs,
83 .mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
84 },
85 };
86
uniphier_gic_driver_init(unsigned int soc)87 void uniphier_gic_driver_init(unsigned int soc)
88 {
89 assert(soc < ARRAY_SIZE(uniphier_gic_driver_data));
90
91 gicv3_driver_init(&uniphier_gic_driver_data[soc]);
92 }
93
uniphier_gic_init(void)94 void uniphier_gic_init(void)
95 {
96 gicv3_distif_init();
97 gicv3_rdistif_init(plat_my_core_pos());
98 gicv3_cpuif_enable(plat_my_core_pos());
99 }
100
uniphier_gic_cpuif_enable(void)101 void uniphier_gic_cpuif_enable(void)
102 {
103 gicv3_cpuif_enable(plat_my_core_pos());
104 }
105
uniphier_gic_cpuif_disable(void)106 void uniphier_gic_cpuif_disable(void)
107 {
108 gicv3_cpuif_disable(plat_my_core_pos());
109 }
110
uniphier_gic_pcpu_init(void)111 void uniphier_gic_pcpu_init(void)
112 {
113 gicv3_rdistif_init(plat_my_core_pos());
114 }
115