1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016-2017 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 */ 6 7 #include "clk-uniphier.h" 8 9 /* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ 10 #define UNIPHIER_LD4_SYS_CLK_NAND(_id) \ 11 UNIPHIER_CLK_RATE(128, 200000000), \ 12 UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) 13 14 #define UNIPHIER_LD11_SYS_CLK_NAND(_id) \ 15 UNIPHIER_CLK_RATE(128, 200000000), \ 16 UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0) 17 18 const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { 19 #if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\ 20 defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ 21 defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) 22 UNIPHIER_LD4_SYS_CLK_NAND(2), 23 UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ 24 UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ 25 UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ 26 UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */ 27 UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ 28 UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ 29 UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ 30 UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */ 31 UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */ 32 { /* sentinel */ } 33 #endif 34 }; 35 36 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { 37 #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) 38 UNIPHIER_LD11_SYS_CLK_NAND(2), 39 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ 40 UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ 41 UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ 42 UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ 43 UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */ 44 { /* sentinel */ } 45 #endif 46 }; 47 48 const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { 49 #if defined(CONFIG_ARCH_UNIPHIER_PXS3) 50 UNIPHIER_LD11_SYS_CLK_NAND(2), 51 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ 52 UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ 53 UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ 54 UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */ 55 UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */ 56 UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 16), /* usb30-phy0 */ 57 UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 18), /* usb30-phy1 */ 58 UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20), /* usb30-phy2 */ 59 UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17), /* usb31-phy0 */ 60 UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19), /* usb31-phy1 */ 61 { /* sentinel */ } 62 #endif 63 }; 64