/external/llvm/test/MC/AArch64/ |
D | arm64-advsimd.s | 1394 ushr d0, d0, #1 define
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
D | arm64-advsimd.s | 1394 ushr d0, d0, #1 define
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/external/vixl/test/aarch64/ |
D | test-trace-aarch64.cc | 2430 __ ushr(d28, d27, 53); in GenerateTestSequenceNEON() local 2431 __ ushr(v1.V16B(), v9.V16B(), 7); in GenerateTestSequenceNEON() local 2432 __ ushr(v2.V2D(), v24.V2D(), 43); in GenerateTestSequenceNEON() local 2433 __ ushr(v30.V2S(), v25.V2S(), 11); in GenerateTestSequenceNEON() local 2434 __ ushr(v10.V4H(), v26.V4H(), 12); in GenerateTestSequenceNEON() local 2435 __ ushr(v4.V4S(), v5.V4S(), 30); in GenerateTestSequenceNEON() local 2436 __ ushr(v30.V8B(), v2.V8B(), 1); in GenerateTestSequenceNEON() local 2437 __ ushr(v6.V8H(), v12.V8H(), 2); in GenerateTestSequenceNEON() local
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/external/swiftshader/src/Pipeline/ |
D | ShaderCore.cpp | 910 void ShaderCore::ushr(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) in ushr() function in sw::ShaderCore
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/external/swiftshader/src/Shader/ |
D | ShaderCore.cpp | 910 void ShaderCore::ushr(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) in ushr() function in sw::ShaderCore
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/external/v8/src/arm64/ |
D | assembler-arm64.cc | 2091 void Assembler::ushr(const VRegister& vd, const VRegister& vn, int shift) { in ushr() function in v8::internal::Assembler
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D | simulator-logic-arm64.cc | 1457 LogicVRegister Simulator::ushr(VectorFormat vform, LogicVRegister dst, in ushr() function in v8::internal::Simulator
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/external/vixl/src/aarch64/ |
D | assembler-aarch64.cc | 4808 void Assembler::ushr(const VRegister& vd, const VRegister& vn, int shift) { in ushr() function in vixl::aarch64::Assembler
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D | logic-aarch64.cc | 1601 LogicVRegister Simulator::ushr(VectorFormat vform, in ushr() function in vixl::aarch64::Simulator
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