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1 /*
2  * Copyright © 2014 Broadcom
3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22  * IN THE SOFTWARE.
23  */
24 
25 #ifndef VC4_CONTEXT_H
26 #define VC4_CONTEXT_H
27 
28 #include <stdio.h>
29 
30 #include "pipe/p_context.h"
31 #include "pipe/p_state.h"
32 #include "util/slab.h"
33 #include "xf86drm.h"
34 
35 #define __user
36 #include "vc4_drm.h"
37 #include "vc4_bufmgr.h"
38 #include "vc4_resource.h"
39 #include "vc4_cl.h"
40 #include "vc4_qir.h"
41 
42 #ifndef DRM_VC4_PARAM_SUPPORTS_ETC1
43 #define DRM_VC4_PARAM_SUPPORTS_ETC1		4
44 #endif
45 #ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS
46 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS	5
47 #endif
48 
49 #ifdef USE_VC4_SIMULATOR
50 #define using_vc4_simulator true
51 #else
52 #define using_vc4_simulator false
53 #endif
54 
55 #define VC4_DIRTY_BLEND         (1 <<  0)
56 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
57 #define VC4_DIRTY_ZSA           (1 <<  2)
58 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
59 #define VC4_DIRTY_VERTTEX       (1 <<  4)
60 
61 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
62 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
63 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
64 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
65 #define VC4_DIRTY_STIPPLE       (1 << 11)
66 #define VC4_DIRTY_VIEWPORT      (1 << 12)
67 #define VC4_DIRTY_CONSTBUF      (1 << 13)
68 #define VC4_DIRTY_VTXSTATE      (1 << 14)
69 #define VC4_DIRTY_VTXBUF        (1 << 15)
70 
71 #define VC4_DIRTY_SCISSOR       (1 << 17)
72 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
73 #define VC4_DIRTY_PRIM_MODE     (1 << 19)
74 #define VC4_DIRTY_CLIP          (1 << 20)
75 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
76 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
77 #define VC4_DIRTY_COMPILED_CS   (1 << 23)
78 #define VC4_DIRTY_COMPILED_VS   (1 << 24)
79 #define VC4_DIRTY_COMPILED_FS   (1 << 25)
80 #define VC4_DIRTY_FS_INPUTS     (1 << 26)
81 
82 struct vc4_sampler_view {
83         struct pipe_sampler_view base;
84         uint32_t texture_p0;
85         uint32_t texture_p1;
86         bool force_first_level;
87         /**
88          * Resource containing the actual texture that will be sampled.
89          *
90          * We may need to rebase the .base.texture resource to work around the
91          * lack of GL_TEXTURE_BASE_LEVEL, or to upload the texture as tiled.
92          */
93         struct pipe_resource *texture;
94 };
95 
96 struct vc4_sampler_state {
97         struct pipe_sampler_state base;
98         uint32_t texture_p1;
99 };
100 
101 struct vc4_texture_stateobj {
102         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
103         unsigned num_textures;
104         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
105         unsigned num_samplers;
106 };
107 
108 struct vc4_shader_uniform_info {
109         enum quniform_contents *contents;
110         uint32_t *data;
111         uint32_t count;
112         uint32_t num_texture_samples;
113 };
114 
115 struct vc4_uncompiled_shader {
116         /** A name for this program, so you can track it in shader-db output. */
117         uint32_t program_id;
118         /** How many variants of this program were compiled, for shader-db. */
119         uint32_t compiled_variant_count;
120         struct pipe_shader_state base;
121 };
122 
123 struct vc4_ubo_range {
124         /**
125          * offset in bytes from the start of the ubo where this range is
126          * uploaded.
127          *
128          * Only set once used is set.
129          */
130         uint32_t dst_offset;
131 
132         /**
133          * offset in bytes from the start of the gallium uniforms where the
134          * data comes from.
135          */
136         uint32_t src_offset;
137 
138         /** size in bytes of this ubo range */
139         uint32_t size;
140 };
141 
142 struct vc4_fs_inputs {
143         /**
144          * Array of the meanings of the VPM inputs this shader needs.
145          *
146          * It doesn't include those that aren't part of the VPM, like
147          * point/line coordinates.
148          */
149         struct vc4_varying_slot *input_slots;
150         uint32_t num_inputs;
151 };
152 
153 struct vc4_compiled_shader {
154         uint64_t program_id;
155         struct vc4_bo *bo;
156 
157         struct vc4_shader_uniform_info uniforms;
158 
159         struct vc4_ubo_range *ubo_ranges;
160         uint32_t num_ubo_ranges;
161         uint32_t ubo_size;
162         /**
163          * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
164          * uniforms have to be rewritten (and therefore the shader state
165          * reemitted).
166          */
167         uint32_t uniform_dirty_bits;
168 
169         /** bitmask of which inputs are color inputs, for flat shade handling. */
170         uint32_t color_inputs;
171 
172         bool disable_early_z;
173 
174         /* Set if the compile failed, likely due to register allocation
175          * failure.  In this case, we have no shader to run and should not try
176          * to do any draws.
177          */
178         bool failed;
179 
180         bool fs_threaded;
181 
182         uint8_t num_inputs;
183 
184         /* Byte offsets for the start of the vertex attributes 0-7, and the
185          * total size as "attribute" 8.
186          */
187         uint8_t vattr_offsets[9];
188         uint8_t vattrs_live;
189 
190         const struct vc4_fs_inputs *fs_inputs;
191 };
192 
193 struct vc4_program_stateobj {
194         struct vc4_uncompiled_shader *bind_vs, *bind_fs;
195         struct vc4_compiled_shader *cs, *vs, *fs;
196 };
197 
198 struct vc4_constbuf_stateobj {
199         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
200         uint32_t enabled_mask;
201         uint32_t dirty_mask;
202 };
203 
204 struct vc4_vertexbuf_stateobj {
205         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
206         unsigned count;
207         uint32_t enabled_mask;
208         uint32_t dirty_mask;
209 };
210 
211 struct vc4_vertex_stateobj {
212         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
213         unsigned num_elements;
214 };
215 
216 /* Hash table key for vc4->jobs */
217 struct vc4_job_key {
218         struct pipe_surface *cbuf;
219         struct pipe_surface *zsbuf;
220 };
221 
222 /**
223  * A complete bin/render job.
224  *
225  * This is all of the state necessary to submit a bin/render to the kernel.
226  * We want to be able to have multiple in progress at a time, so that we don't
227  * need to flush an existing CL just to switch to rendering to a new render
228  * target (which would mean reading back from the old render target when
229  * starting to render to it again).
230  */
231 struct vc4_job {
232         struct vc4_cl bcl;
233         struct vc4_cl shader_rec;
234         struct vc4_cl uniforms;
235         struct vc4_cl bo_handles;
236         struct vc4_cl bo_pointers;
237         uint32_t shader_rec_count;
238         /**
239          * Amount of memory used by the BOs in bo_pointers.
240          *
241          * Used for checking when we should flush the job early so we don't
242          * OOM.
243          */
244         uint32_t bo_space;
245 
246         /* Last BO hindex referenced from VC4_PACKET_GEM_HANDLES. */
247         uint32_t last_gem_handle_hindex;
248 
249         /** @{ Surfaces to submit rendering for. */
250         struct pipe_surface *color_read;
251         struct pipe_surface *color_write;
252         struct pipe_surface *zs_read;
253         struct pipe_surface *zs_write;
254         struct pipe_surface *msaa_color_write;
255         struct pipe_surface *msaa_zs_write;
256         /** @} */
257         /** @{
258          * Bounding box of the scissor across all queued drawing.
259          *
260          * Note that the max values are exclusive.
261          */
262         uint32_t draw_min_x;
263         uint32_t draw_min_y;
264         uint32_t draw_max_x;
265         uint32_t draw_max_y;
266         /** @} */
267         /** @{
268          * Width/height of the color framebuffer being rendered to,
269          * for VC4_TILE_RENDERING_MODE_CONFIG.
270         */
271         uint32_t draw_width;
272         uint32_t draw_height;
273         /** @} */
274         /** @{ Tile information, depending on MSAA and float color buffer. */
275         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
276         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
277 
278         uint32_t tile_width; /** @< Width of a tile. */
279         uint32_t tile_height; /** @< Height of a tile. */
280         /** Whether the current rendering is in a 4X MSAA tile buffer. */
281         bool msaa;
282 	/** @} */
283 
284         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
285          * first rendering.
286          */
287         uint32_t cleared;
288         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
289          * (either clears or draws).
290          */
291         uint32_t resolve;
292         uint32_t clear_color[2];
293         uint32_t clear_depth; /**< 24-bit unorm depth */
294         uint8_t clear_stencil;
295 
296         /**
297          * Set if some drawing (triangles, blits, or just a glClear()) has
298          * been done to the FBO, meaning that we need to
299          * DRM_IOCTL_VC4_SUBMIT_CL.
300          */
301         bool needs_flush;
302 
303         /**
304          * Number of draw calls (not counting full buffer clears) queued in
305          * the current job.
306          */
307         uint32_t draw_calls_queued;
308 
309         /** Any flags to be passed in drm_vc4_submit_cl.flags. */
310         uint32_t flags;
311 
312         struct vc4_job_key key;
313 };
314 
315 struct vc4_context {
316         struct pipe_context base;
317 
318         int fd;
319         struct vc4_screen *screen;
320 
321         /** The 3D rendering job for the currently bound FBO. */
322         struct vc4_job *job;
323 
324         /* Map from struct vc4_job_key to the job for that FBO.
325          */
326         struct hash_table *jobs;
327 
328         /**
329          * Map from vc4_resource to a job writing to that resource.
330          *
331          * Primarily for flushing jobs rendering to textures that are now
332          * being read from.
333          */
334         struct hash_table *write_jobs;
335 
336         struct slab_child_pool transfer_pool;
337         struct blitter_context *blitter;
338 
339         /** bitfield of VC4_DIRTY_* */
340         uint32_t dirty;
341 
342         struct primconvert_context *primconvert;
343 
344         struct hash_table *fs_cache, *vs_cache;
345         struct set *fs_inputs_set;
346         uint32_t next_uncompiled_program_id;
347         uint64_t next_compiled_program_id;
348 
349         struct ra_regs *regs;
350         unsigned int reg_class_any[2];
351         unsigned int reg_class_a_or_b[2];
352         unsigned int reg_class_a_or_b_or_acc[2];
353         unsigned int reg_class_r0_r3;
354         unsigned int reg_class_r4_or_a[2];
355         unsigned int reg_class_a[2];
356 
357         uint8_t prim_mode;
358 
359         /** Maximum index buffer valid for the current shader_rec. */
360         uint32_t max_index;
361         /** Last index bias baked into the current shader_rec. */
362         uint32_t last_index_bias;
363 
364         /** Seqno of the last CL flush's job. */
365         uint64_t last_emit_seqno;
366 
367         struct u_upload_mgr *uploader;
368 
369         /** @{ Current pipeline state objects */
370         struct pipe_scissor_state scissor;
371         struct pipe_blend_state *blend;
372         struct vc4_rasterizer_state *rasterizer;
373         struct vc4_depth_stencil_alpha_state *zsa;
374 
375         struct vc4_texture_stateobj verttex, fragtex;
376 
377         struct vc4_program_stateobj prog;
378 
379         struct vc4_vertex_stateobj *vtx;
380 
381         struct {
382                 struct pipe_blend_color f;
383                 uint8_t ub[4];
384         } blend_color;
385         struct pipe_stencil_ref stencil_ref;
386         unsigned sample_mask;
387         struct pipe_framebuffer_state framebuffer;
388         struct pipe_poly_stipple stipple;
389         struct pipe_clip_state clip;
390         struct pipe_viewport_state viewport;
391         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
392         struct vc4_vertexbuf_stateobj vertexbuf;
393         /** @} */
394 };
395 
396 struct vc4_rasterizer_state {
397         struct pipe_rasterizer_state base;
398 
399         /* VC4_CONFIGURATION_BITS */
400         uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
401 
402         struct PACKED {
403                 uint8_t depth_offset[V3D21_DEPTH_OFFSET_length];
404                 uint8_t point_size[V3D21_POINT_SIZE_length];
405                 uint8_t line_width[V3D21_LINE_WIDTH_length];
406         } packed;
407 
408         /** Raster order flags to be passed in struct drm_vc4_submit_cl.flags. */
409         uint32_t tile_raster_order_flags;
410 };
411 
412 struct vc4_depth_stencil_alpha_state {
413         struct pipe_depth_stencil_alpha_state base;
414 
415         /* VC4_CONFIGURATION_BITS */
416         uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
417 
418         /** Uniforms for stencil state.
419          *
420          * Index 0 is either the front config, or the front-and-back config.
421          * Index 1 is the back config if doing separate back stencil.
422          * Index 2 is the writemask config if it's not a common mask value.
423          */
424         uint32_t stencil_uniforms[3];
425 };
426 
427 #define perf_debug(...) do {                            \
428         if (unlikely(vc4_debug & VC4_DEBUG_PERF))       \
429                 fprintf(stderr, __VA_ARGS__);           \
430 } while (0)
431 
432 static inline struct vc4_context *
vc4_context(struct pipe_context * pcontext)433 vc4_context(struct pipe_context *pcontext)
434 {
435         return (struct vc4_context *)pcontext;
436 }
437 
438 static inline struct vc4_sampler_view *
vc4_sampler_view(struct pipe_sampler_view * psview)439 vc4_sampler_view(struct pipe_sampler_view *psview)
440 {
441         return (struct vc4_sampler_view *)psview;
442 }
443 
444 static inline struct vc4_sampler_state *
vc4_sampler_state(struct pipe_sampler_state * psampler)445 vc4_sampler_state(struct pipe_sampler_state *psampler)
446 {
447         return (struct vc4_sampler_state *)psampler;
448 }
449 
450 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
451                                         void *priv, unsigned flags);
452 void vc4_draw_init(struct pipe_context *pctx);
453 void vc4_state_init(struct pipe_context *pctx);
454 void vc4_program_init(struct pipe_context *pctx);
455 void vc4_program_fini(struct pipe_context *pctx);
456 void vc4_query_init(struct pipe_context *pctx);
457 void vc4_simulator_init(struct vc4_screen *screen);
458 void vc4_simulator_destroy(struct vc4_screen *screen);
459 int vc4_simulator_flush(struct vc4_context *vc4,
460                         struct drm_vc4_submit_cl *args,
461                         struct vc4_job *job);
462 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
463 void vc4_simulator_open_from_handle(int fd, uint32_t winsys_stride,
464                                     int handle, uint32_t size);
465 
466 static inline int
vc4_ioctl(int fd,unsigned long request,void * arg)467 vc4_ioctl(int fd, unsigned long request, void *arg)
468 {
469         if (using_vc4_simulator)
470                 return vc4_simulator_ioctl(fd, request, arg);
471         else
472                 return drmIoctl(fd, request, arg);
473 }
474 
475 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
476 void vc4_write_uniforms(struct vc4_context *vc4,
477                         struct vc4_compiled_shader *shader,
478                         struct vc4_constbuf_stateobj *cb,
479                         struct vc4_texture_stateobj *texstate);
480 
481 void vc4_flush(struct pipe_context *pctx);
482 void vc4_job_init(struct vc4_context *vc4);
483 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
484                             struct pipe_surface *cbuf,
485                             struct pipe_surface *zsbuf);
486 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
487 
488 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
489 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
490                                      struct pipe_resource *prsc);
491 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
492                                      struct pipe_resource *prsc);
493 void vc4_emit_state(struct pipe_context *pctx);
494 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
495 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
496 bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
497 
498 bool vc4_rt_format_supported(enum pipe_format f);
499 bool vc4_rt_format_is_565(enum pipe_format f);
500 bool vc4_tex_format_supported(enum pipe_format f);
501 uint8_t vc4_get_tex_format(enum pipe_format f);
502 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
503 void vc4_init_query_functions(struct vc4_context *vc4);
504 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
505 void vc4_blitter_save(struct vc4_context *vc4);
506 #endif /* VC4_CONTEXT_H */
507