1 /*
2 * Copyright © 2015 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "vc4_qir.h"
25 #include "kernel/vc4_packet.h"
26 #include "compiler/nir/nir_builder.h"
27
28 /** @file vc4_nir_lower_txf_ms.c
29 * Walks the NIR generated by TGSI-to-NIR to lower its nir_texop_txf_ms
30 * coordinates to do the math necessary and use a plain nir_texop_txf instead.
31 *
32 * MSAA textures are laid out as 32x32-aligned blocks of RGBA8888 or Z24S8.
33 * We can't load them through the normal sampler path because of the lack of
34 * linear support in the hardware. So, we treat MSAA textures as a giant UBO
35 * and do the math in the shader.
36 */
37
38 static void
vc4_nir_lower_txf_ms_instr(struct vc4_compile * c,nir_builder * b,nir_tex_instr * txf_ms)39 vc4_nir_lower_txf_ms_instr(struct vc4_compile *c, nir_builder *b,
40 nir_tex_instr *txf_ms)
41 {
42 if (txf_ms->op != nir_texop_txf_ms)
43 return;
44
45 b->cursor = nir_before_instr(&txf_ms->instr);
46
47 nir_tex_instr *txf = nir_tex_instr_create(c->s, 1);
48 txf->op = nir_texop_txf;
49 txf->texture = txf_ms->texture;
50 txf->texture_index = txf_ms->texture_index;
51 txf->coord_components = txf_ms->coord_components;
52 txf->is_shadow = txf_ms->is_shadow;
53 txf->is_new_style_shadow = txf_ms->is_new_style_shadow;
54
55 nir_ssa_def *coord = NULL, *sample_index = NULL;
56 for (int i = 0; i < txf_ms->num_srcs; i++) {
57 assert(txf_ms->src[i].src.is_ssa);
58
59 switch (txf_ms->src[i].src_type) {
60 case nir_tex_src_coord:
61 coord = txf_ms->src[i].src.ssa;
62 break;
63 case nir_tex_src_ms_index:
64 sample_index = txf_ms->src[i].src.ssa;
65 break;
66 default:
67 unreachable("Unknown txf_ms src\n");
68 }
69 }
70 assert(coord);
71 assert(sample_index);
72
73 nir_ssa_def *x = nir_channel(b, coord, 0);
74 nir_ssa_def *y = nir_channel(b, coord, 1);
75
76 uint32_t tile_w = 32;
77 uint32_t tile_h = 32;
78 uint32_t tile_w_shift = 5;
79 uint32_t tile_h_shift = 5;
80 uint32_t tile_size = (tile_h * tile_w *
81 VC4_MAX_SAMPLES * sizeof(uint32_t));
82 unsigned unit = txf_ms->texture_index;
83 uint32_t w = align(c->key->tex[unit].msaa_width, tile_w);
84 uint32_t w_tiles = w / tile_w;
85
86 nir_ssa_def *x_tile = nir_ushr(b, x, nir_imm_int(b, tile_w_shift));
87 nir_ssa_def *y_tile = nir_ushr(b, y, nir_imm_int(b, tile_h_shift));
88 nir_ssa_def *tile_addr = nir_iadd(b,
89 nir_imul(b, x_tile,
90 nir_imm_int(b, tile_size)),
91 nir_imul(b, y_tile,
92 nir_imm_int(b, (w_tiles *
93 tile_size))));
94 nir_ssa_def *x_subspan = nir_iand(b, x,
95 nir_imm_int(b, (tile_w - 1) & ~1));
96 nir_ssa_def *y_subspan = nir_iand(b, y,
97 nir_imm_int(b, (tile_h - 1) & ~1));
98 nir_ssa_def *subspan_addr = nir_iadd(b,
99 nir_imul(b, x_subspan,
100 nir_imm_int(b, 2 * VC4_MAX_SAMPLES * sizeof(uint32_t))),
101 nir_imul(b, y_subspan,
102 nir_imm_int(b,
103 tile_w *
104 VC4_MAX_SAMPLES *
105 sizeof(uint32_t))));
106
107 nir_ssa_def *pixel_addr = nir_ior(b,
108 nir_iand(b,
109 nir_ishl(b, x,
110 nir_imm_int(b, 2)),
111 nir_imm_int(b, (1 << 2))),
112 nir_iand(b,
113 nir_ishl(b, y,
114 nir_imm_int(b, 3)),
115 nir_imm_int(b, (1 << 3))));
116
117 nir_ssa_def *sample_addr = nir_ishl(b, sample_index, nir_imm_int(b, 4));
118
119 nir_ssa_def *addr = nir_iadd(b,
120 nir_ior(b, sample_addr, pixel_addr),
121 nir_iadd(b, subspan_addr, tile_addr));
122
123 txf->src[0].src_type = nir_tex_src_coord;
124 txf->src[0].src = nir_src_for_ssa(nir_vec2(b, addr, nir_imm_int(b, 0)));
125 nir_ssa_dest_init(&txf->instr, &txf->dest, 4, 32, NULL);
126 nir_builder_instr_insert(b, &txf->instr);
127 nir_ssa_def_rewrite_uses(&txf_ms->dest.ssa,
128 nir_src_for_ssa(&txf->dest.ssa));
129 nir_instr_remove(&txf_ms->instr);
130 }
131
132 static bool
vc4_nir_lower_txf_ms_impl(struct vc4_compile * c,nir_function_impl * impl)133 vc4_nir_lower_txf_ms_impl(struct vc4_compile *c, nir_function_impl *impl)
134 {
135 nir_builder b;
136 nir_builder_init(&b, impl);
137
138 nir_foreach_block(block, impl) {
139 nir_foreach_instr_safe(instr, block) {
140 if (instr->type == nir_instr_type_tex) {
141 vc4_nir_lower_txf_ms_instr(c, &b,
142 nir_instr_as_tex(instr));
143 }
144 }
145 }
146
147 nir_metadata_preserve(impl,
148 nir_metadata_block_index |
149 nir_metadata_dominance);
150
151 return true;
152 }
153
154 void
vc4_nir_lower_txf_ms(nir_shader * s,struct vc4_compile * c)155 vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c)
156 {
157 nir_foreach_function(function, s) {
158 if (function->impl)
159 vc4_nir_lower_txf_ms_impl(c, function->impl);
160 }
161 }
162