1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
5 */
6
7 /*
8 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
9 * PCI and video mode code was derived from smiLynxEM driver.
10 */
11
12 #include <common.h>
13
14 #include <asm/io.h>
15 #include <pci.h>
16 #include <video_fb.h>
17 #include "videomodes.h"
18 #include <mb862xx.h>
19
20 #if defined(CONFIG_POST)
21 #include <post.h>
22 #endif
23
24 /*
25 * Graphic Device
26 */
27 GraphicDevice mb862xx;
28
29 /*
30 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
31 */
32 #define VIDEO_MEM_SIZE 0x01FC0000
33
34 #if defined(CONFIG_PCI)
35 #if defined(CONFIG_VIDEO_CORALP)
36
37 static struct pci_device_id supported[] = {
38 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
39 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
40 { }
41 };
42
43 /* Internal clock frequency divider table, index is mode number */
44 unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
45 #endif
46 #endif
47
48 #if defined(CONFIG_VIDEO_CORALP)
49 #define rd_io in32r
50 #define wr_io out32r
51 #else
52 #define rd_io(addr) in_be32((volatile unsigned *)(addr))
53 #define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
54 #endif
55
56 #define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
57 #define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
58 (val))
59 #define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
60 #define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
61 (val))
62 #define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
63 #define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
64
65 #if defined(CONFIG_VIDEO_CORALP)
66 #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
67 #else
68 #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
69 #endif
70
71 #define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
72 (GC_DISP_BASE | GC_L0PAL0) + \
73 ((idx) << 2)), (val))
74
75 #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
gdc_sw_reset(void)76 static void gdc_sw_reset (void)
77 {
78 GraphicDevice *dev = &mb862xx;
79
80 HOST_WR_REG (GC_SRST, 0x1);
81 udelay (500);
82 video_hw_init ();
83 }
84
85
de_wait(void)86 static void de_wait (void)
87 {
88 GraphicDevice *dev = &mb862xx;
89 int lc = 0x10000;
90
91 /*
92 * Sync with software writes to framebuffer,
93 * try to reset if engine locked
94 */
95 while (DE_RD_REG (GC_CTR) & 0x00000131)
96 if (lc-- < 0) {
97 gdc_sw_reset ();
98 puts ("gdc reset done after drawing engine lock.\n");
99 break;
100 }
101 }
102
de_wait_slots(int slots)103 static void de_wait_slots (int slots)
104 {
105 GraphicDevice *dev = &mb862xx;
106 int lc = 0x10000;
107
108 /* Wait for free fifo slots */
109 while (DE_RD_REG (GC_IFCNT) < slots)
110 if (lc-- < 0) {
111 gdc_sw_reset ();
112 puts ("gdc reset done after drawing engine lock.\n");
113 break;
114 }
115 }
116 #endif
117
118 #if !defined(CONFIG_VIDEO_CORALP)
board_disp_init(void)119 static void board_disp_init (void)
120 {
121 GraphicDevice *dev = &mb862xx;
122 const gdc_regs *regs = board_get_regs ();
123
124 while (regs->index) {
125 DISP_WR_REG (regs->index, regs->value);
126 regs++;
127 }
128 }
129 #endif
130
131 /*
132 * Init drawing engine if accel enabled.
133 * Also clears visible framebuffer.
134 */
de_init(void)135 static void de_init (void)
136 {
137 GraphicDevice *dev = &mb862xx;
138 #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
139 int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
140
141 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
142
143 /* Setup mode and fbbase, xres, fg, bg */
144 de_wait_slots (2);
145 DE_WR_FIFO (0xf1010108);
146 DE_WR_FIFO (cf | 0x0300);
147 DE_WR_REG (GC_FBR, 0x0);
148 DE_WR_REG (GC_XRES, dev->winSizeX);
149 DE_WR_REG (GC_FC, 0x0);
150 DE_WR_REG (GC_BC, 0x0);
151 /* Reset clipping */
152 DE_WR_REG (GC_CXMIN, 0x0);
153 DE_WR_REG (GC_CXMAX, dev->winSizeX);
154 DE_WR_REG (GC_CYMIN, 0x0);
155 DE_WR_REG (GC_CYMAX, dev->winSizeY);
156
157 /* Clear framebuffer using drawing engine */
158 de_wait_slots (3);
159 DE_WR_FIFO (0x09410000);
160 DE_WR_FIFO (0x00000000);
161 DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
162 /* sync with SW access to framebuffer */
163 de_wait ();
164 #else
165 unsigned int i, *p;
166
167 i = dev->winSizeX * dev->winSizeY;
168 p = (unsigned int *)dev->frameAdrs;
169 while (i--)
170 *p++ = 0;
171 #endif
172 }
173
174 #if defined(CONFIG_VIDEO_CORALP)
175 /* use CCF and MMR parameters for Coral-P Eval. Board as default */
176 #ifndef CONFIG_SYS_MB862xx_CCF
177 #define CONFIG_SYS_MB862xx_CCF 0x00090000
178 #endif
179 #ifndef CONFIG_SYS_MB862xx_MMR
180 #define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
181 #endif
182
pci_video_init(void)183 unsigned int pci_video_init (void)
184 {
185 GraphicDevice *dev = &mb862xx;
186 pci_dev_t devbusfn;
187 u16 device;
188
189 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
190 puts("controller not present\n");
191 return 0;
192 }
193
194 /* PCI setup */
195 pci_write_config_dword (devbusfn, PCI_COMMAND,
196 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
197 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
198 dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
199
200 if (dev->frameAdrs == 0) {
201 puts ("PCI config: failed to get base address\n");
202 return 0;
203 }
204
205 dev->pciBase = dev->frameAdrs;
206
207 puts("Coral-");
208
209 pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
210 switch (device) {
211 case PCI_DEVICE_ID_CORAL_P:
212 puts("P\n");
213 break;
214 case PCI_DEVICE_ID_CORAL_PA:
215 puts("PA\n");
216 break;
217 default:
218 puts("Unknown\n");
219 return 0;
220 }
221
222 /* Setup clocks and memory mode for Coral-P(A) */
223 HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
224 udelay (200);
225 HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
226 udelay (100);
227 return dev->frameAdrs;
228 }
229
card_init(void)230 unsigned int card_init (void)
231 {
232 GraphicDevice *dev = &mb862xx;
233 unsigned int cf, videomode, div = 0;
234 unsigned long t1, hsync, vsync;
235 char *penv;
236 int tmp, i, bpp;
237 struct ctfb_res_modes *res_mode;
238 struct ctfb_res_modes var_mode;
239
240 memset (dev, 0, sizeof (GraphicDevice));
241
242 if (!pci_video_init ())
243 return 0;
244
245 tmp = 0;
246 videomode = 0x310;
247 /* get video mode via environment */
248 penv = env_get("videomode");
249 if (penv) {
250 /* decide if it is a string */
251 if (penv[0] <= '9') {
252 videomode = (int) simple_strtoul (penv, NULL, 16);
253 tmp = 1;
254 }
255 } else {
256 tmp = 1;
257 }
258
259 if (tmp) {
260 /* parameter are vesa modes, search params */
261 for (i = 0; i < VESA_MODES_COUNT; i++) {
262 if (vesa_modes[i].vesanr == videomode)
263 break;
264 }
265 if (i == VESA_MODES_COUNT) {
266 printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
267 videomode);
268 i = 0;
269 }
270 res_mode = (struct ctfb_res_modes *)
271 &res_mode_init[vesa_modes[i].resindex];
272 if (vesa_modes[i].resindex > 2) {
273 puts ("\tUnsupported resolution, using default\n");
274 bpp = vesa_modes[1].bits_per_pixel;
275 div = fr_div[1];
276 }
277 bpp = vesa_modes[i].bits_per_pixel;
278 div = fr_div[vesa_modes[i].resindex];
279 } else {
280 res_mode = (struct ctfb_res_modes *) &var_mode;
281 bpp = video_get_params (res_mode, penv);
282 }
283
284 /* calculate hsync and vsync freq (info only) */
285 t1 = (res_mode->left_margin + res_mode->xres +
286 res_mode->right_margin + res_mode->hsync_len) / 8;
287 t1 *= 8;
288 t1 *= res_mode->pixclock;
289 t1 /= 1000;
290 hsync = 1000000000L / t1;
291 t1 *= (res_mode->upper_margin + res_mode->yres +
292 res_mode->lower_margin + res_mode->vsync_len);
293 t1 /= 1000;
294 vsync = 1000000000L / t1;
295
296 /* fill in Graphic device struct */
297 sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
298 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
299 printf ("\t%s\n", dev->modeIdent);
300 dev->winSizeX = res_mode->xres;
301 dev->winSizeY = res_mode->yres;
302 dev->memSize = VIDEO_MEM_SIZE;
303
304 switch (bpp) {
305 case 8:
306 dev->gdfIndex = GDF__8BIT_INDEX;
307 dev->gdfBytesPP = 1;
308 break;
309 case 15:
310 case 16:
311 dev->gdfIndex = GDF_15BIT_555RGB;
312 dev->gdfBytesPP = 2;
313 break;
314 default:
315 printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
316 bpp);
317 puts ("\tfallback to 15bpp\n");
318 dev->gdfIndex = GDF_15BIT_555RGB;
319 dev->gdfBytesPP = 2;
320 }
321
322 /* Setup dot clock (internal pll, division rate) */
323 DISP_WR_REG (GC_DCM1, div);
324 /* L0 init */
325 cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
326 DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
327 (dev->winSizeY - 1) | cf);
328 DISP_WR_REG (GC_L0OA0, 0x0);
329 DISP_WR_REG (GC_L0DA0, 0x0);
330 DISP_WR_REG (GC_L0DY_L0DX, 0x0);
331 DISP_WR_REG (GC_L0EM, 0x0);
332 DISP_WR_REG (GC_L0WY_L0WX, 0x0);
333 DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
334
335 /* Display timing init */
336 DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
337 res_mode->left_margin +
338 res_mode->right_margin +
339 res_mode->hsync_len - 1) << 16);
340 DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
341 (dev->winSizeX - 1));
342 DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
343 (res_mode->hsync_len - 1) << 16 |
344 (dev->winSizeX +
345 res_mode->right_margin - 1));
346 DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
347 res_mode->upper_margin +
348 res_mode->vsync_len - 1) << 16);
349 DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
350 (dev->winSizeY +
351 res_mode->lower_margin - 1));
352 DISP_WR_REG (GC_WY_WX, 0x0);
353 DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
354 /* Display enable, L0 layer */
355 DISP_WR_REG (GC_DCM1, 0x80010000 | div);
356
357 return dev->frameAdrs;
358 }
359 #endif
360
361
362 #if !defined(CONFIG_VIDEO_CORALP)
mb862xx_probe(unsigned int addr)363 int mb862xx_probe(unsigned int addr)
364 {
365 GraphicDevice *dev = &mb862xx;
366 unsigned int reg;
367
368 dev->frameAdrs = addr;
369 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
370
371 /* Try to access GDC ID/Revision registers */
372 reg = HOST_RD_REG (GC_CID);
373 reg = HOST_RD_REG (GC_CID);
374 if (reg == 0x303) {
375 reg = DE_RD_REG(GC_REV);
376 reg = DE_RD_REG(GC_REV);
377 if ((reg & ~0xff) == 0x20050100)
378 return MB862XX_TYPE_LIME;
379 }
380
381 return 0;
382 }
383 #endif
384
video_hw_init(void)385 void *video_hw_init (void)
386 {
387 GraphicDevice *dev = &mb862xx;
388
389 puts ("Video: Fujitsu ");
390
391 memset (dev, 0, sizeof (GraphicDevice));
392
393 #if defined(CONFIG_VIDEO_CORALP)
394 if (card_init () == 0)
395 return NULL;
396 #else
397 /*
398 * Preliminary init of the onboard graphic controller,
399 * retrieve base address
400 */
401 if ((dev->frameAdrs = board_video_init ()) == 0) {
402 puts ("Controller not found!\n");
403 return NULL;
404 } else {
405 puts ("Lime\n");
406
407 /* Set Change of Clock Frequency Register */
408 HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
409 /* Delay required */
410 udelay(300);
411 /* Set Memory I/F Mode Register) */
412 HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
413 }
414 #endif
415
416 de_init ();
417
418 #if !defined(CONFIG_VIDEO_CORALP)
419 board_disp_init ();
420 #endif
421
422 #if (defined(CONFIG_LWMON5) || \
423 defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
424 /* Lamp on */
425 board_backlight_switch (1);
426 #endif
427
428 return dev;
429 }
430
431 /*
432 * Set a RGB color in the LUT
433 */
video_set_lut(unsigned int index,unsigned char r,unsigned char g,unsigned char b)434 void video_set_lut (unsigned int index, unsigned char r,
435 unsigned char g, unsigned char b)
436 {
437 GraphicDevice *dev = &mb862xx;
438
439 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
440 }
441
442 #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
443 /*
444 * Drawing engine Fill and BitBlt screen region
445 */
video_hw_rectfill(unsigned int bpp,unsigned int dst_x,unsigned int dst_y,unsigned int dim_x,unsigned int dim_y,unsigned int color)446 void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
447 unsigned int dst_y, unsigned int dim_x,
448 unsigned int dim_y, unsigned int color)
449 {
450 GraphicDevice *dev = &mb862xx;
451
452 de_wait_slots (3);
453 DE_WR_REG (GC_FC, color);
454 DE_WR_FIFO (0x09410000);
455 DE_WR_FIFO ((dst_y << 16) | dst_x);
456 DE_WR_FIFO ((dim_y << 16) | dim_x);
457 de_wait ();
458 }
459
video_hw_bitblt(unsigned int bpp,unsigned int src_x,unsigned int src_y,unsigned int dst_x,unsigned int dst_y,unsigned int width,unsigned int height)460 void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
461 unsigned int src_y, unsigned int dst_x,
462 unsigned int dst_y, unsigned int width,
463 unsigned int height)
464 {
465 GraphicDevice *dev = &mb862xx;
466 unsigned int ctrl = 0x0d000000L;
467
468 if (src_x >= dst_x && src_y >= dst_y)
469 ctrl |= 0x00440000L;
470 else if (src_x >= dst_x && src_y <= dst_y)
471 ctrl |= 0x00460000L;
472 else if (src_x <= dst_x && src_y >= dst_y)
473 ctrl |= 0x00450000L;
474 else
475 ctrl |= 0x00470000L;
476
477 de_wait_slots (4);
478 DE_WR_FIFO (ctrl);
479 DE_WR_FIFO ((src_y << 16) | src_x);
480 DE_WR_FIFO ((dst_y << 16) | dst_x);
481 DE_WR_FIFO ((height << 16) | width);
482 de_wait (); /* sync */
483 }
484 #endif
485