| /external/v8/src/compiler/arm/ |
| D | code-generator-arm.cc | 2417 __ vzip(Neon16, dst.low(), dst.high()); // dst = [0, 8, 1, 9, ... 11] in AssembleArchInstruction() local
2426 __ vzip(Neon16, dst.low(), dst.high()); // dst = [4, 12, 5, 13, ... 15] in AssembleArchInstruction() local
2479 __ vzip(Neon8, dst.low(), dst.high()); // dst = [0, 16, 1, 17, ... 23] in AssembleArchInstruction() local
2488 __ vzip(Neon8, dst.low(), dst.high()); // dst = [8, 24, 9, 25, ... 31] in AssembleArchInstruction() local
|
| /external/v8/src/arm/ |
| D | assembler-arm.cc | 4825 void Assembler::vzip(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) { in vzip() function in v8::internal::Assembler
4836 void Assembler::vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) { in vzip() function in v8::internal::Assembler
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 3465 void AssemblerARM32::vzip(Type ElmtTy, const Operand *OpQd, const Operand *OpQn, in vzip() function in Ice::ARM32::AssemblerARM32
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 6134 void vzip(DataType dt, DRegister rd, DRegister rm) { vzip(al, dt, rd, rm); } in vzip() function
6137 void vzip(DataType dt, QRegister rd, QRegister rm) { vzip(al, dt, rd, rm); } in vzip() function
|
| D | assembler-aarch32.cc | 27826 void Assembler::vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) { in vzip() function in vixl::aarch32::Assembler
27868 void Assembler::vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) { in vzip() function in vixl::aarch32::Assembler
|
| D | disasm-aarch32.cc | 6951 void Disassembler::vzip(Condition cond, in vzip() function in vixl::aarch32::Disassembler
6960 void Disassembler::vzip(Condition cond, in vzip() function in vixl::aarch32::Disassembler
|