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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2010 - 2011
4  * NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <linux/errno.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/emc.h>
12 #include <asm/arch/gp_padctrl.h>
13 #include <asm/arch/pinmux.h>
14 #include <asm/arch/sdram_param.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/ap.h>
17 #include <asm/arch-tegra/apb_misc.h>
18 #include <asm/arch-tegra/clk_rst.h>
19 #include <asm/arch-tegra/pmc.h>
20 #include <asm/arch-tegra/fuse.h>
21 #include <asm/arch-tegra/warmboot.h>
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 #ifndef CONFIG_TEGRA_CLOCK_SCALING
26 #error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
27 #endif
28 
29 /*
30  * This is the place in SRAM where the SDRAM parameters are stored. There
31  * are 4 blocks, one for each RAM code
32  */
33 #define SDRAM_PARAMS_BASE	(NV_PA_BASE_SRAM + 0x188)
34 
35 /* TODO: If we later add support for the Misc GP controller, refactor this */
36 union xm2cfga_reg {
37 	struct {
38 		u32 reserved0:2;
39 		u32 hsm_en:1;
40 		u32 reserved1:2;
41 		u32 preemp_en:1;
42 		u32 vref_en:1;
43 		u32 reserved2:5;
44 		u32 cal_drvdn:5;
45 		u32 reserved3:3;
46 		u32 cal_drvup:5;
47 		u32 reserved4:3;
48 		u32 cal_drvdn_slwr:2;
49 		u32 cal_drvup_slwf:2;
50 	};
51 	u32 word;
52 };
53 
54 union xm2cfgd_reg {
55 	struct {
56 		u32 reserved0:2;
57 		u32 hsm_en:1;
58 		u32 schmt_en:1;
59 		u32 lpmd:2;
60 		u32 vref_en:1;
61 		u32 reserved1:5;
62 		u32 cal_drvdn:5;
63 		u32 reserved2:3;
64 		u32 cal_drvup:5;
65 		u32 reserved3:3;
66 		u32 cal_drvdn_slwr:2;
67 		u32 cal_drvup_slwf:2;
68 	};
69 	u32 word;
70 };
71 
72 /*
73  * TODO: This register is not documented in the TRM yet. We could move this
74  * into the EMC and give it a proper interface, but not while it is
75  * undocumented.
76  */
77 union fbio_spare_reg {
78 	struct {
79 		u32 reserved:24;
80 		u32 cfg_wb0:8;
81 	};
82 	u32 word;
83 };
84 
85 /* We pack the resume information into these unions for later */
86 union scratch2_reg {
87 	struct {
88 		u32 pllm_base_divm:5;
89 		u32 pllm_base_divn:10;
90 		u32 pllm_base_divp:3;
91 		u32 pllm_misc_lfcon:4;
92 		u32 pllm_misc_cpcon:4;
93 		u32 gp_xm2cfga_padctrl_preemp:1;
94 		u32 gp_xm2cfgd_padctrl_schmt:1;
95 		u32 osc_ctrl_xobp:1;
96 		u32 memory_type:3;
97 	};
98 	u32 word;
99 };
100 
101 union scratch4_reg {
102 	struct {
103 		u32 emc_clock_divider:8;
104 		u32 pllm_stable_time:8;
105 		u32 pllx_stable_time:8;
106 		u32 emc_fbio_spare_cfg_wb0:8;
107 	};
108 	u32 word;
109 };
110 
111 union scratch24_reg {
112 	struct {
113 		u32 emc_auto_cal_wait:8;
114 		u32 emc_pin_program_wait:8;
115 		u32 warmboot_wait:8;
116 		u32 reserved:8;
117 	};
118 	u32 word;
119 };
120 
warmboot_save_sdram_params(void)121 int warmboot_save_sdram_params(void)
122 {
123 	u32 ram_code;
124 	struct sdram_params sdram;
125 	struct apb_misc_pp_ctlr *apb_misc =
126 				(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
127 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
128 	struct apb_misc_gp_ctlr *gp =
129 			(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
130 	struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
131 	union scratch2_reg scratch2;
132 	union scratch4_reg scratch4;
133 	union scratch24_reg scratch24;
134 	union xm2cfga_reg xm2cfga;
135 	union xm2cfgd_reg xm2cfgd;
136 	union fbio_spare_reg fbio_spare;
137 
138 	/* get ram code that is used as index to array sdram_params in BCT */
139 	ram_code = (readl(&apb_misc->strapping_opt_a) >>
140 			  STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
141 	memcpy(&sdram,
142 	       (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
143 	       sizeof(sdram));
144 
145 	xm2cfga.word = readl(&gp->xm2cfga);
146 	xm2cfgd.word = readl(&gp->xm2cfgd);
147 
148 	scratch2.word = 0;
149 	scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
150 
151 	/* Get the memory PLL settings */
152 	{
153 		u32 divm, divn, divp, cpcon, lfcon;
154 
155 		if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
156 					&cpcon, &lfcon))
157 			return -1;
158 		scratch2.pllm_base_divm = divm;
159 		scratch2.pllm_base_divn = divn;
160 		scratch2.pllm_base_divp = divp;
161 		scratch2.pllm_misc_cpcon = cpcon;
162 		scratch2.pllm_misc_lfcon = lfcon;
163 	}
164 
165 	scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
166 	scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
167 	scratch2.memory_type = sdram.memory_type;
168 	writel(scratch2.word, &pmc->pmc_scratch2);
169 
170 	/* collect data from various sources for pmc_scratch4 */
171 	fbio_spare.word = readl(&emc->fbio_spare);
172 	scratch4.word = 0;
173 	scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
174 	scratch4.emc_clock_divider = sdram.emc_clock_divider;
175 	scratch4.pllm_stable_time = -1;
176 	scratch4.pllx_stable_time = -1;
177 	writel(scratch4.word, &pmc->pmc_scratch4);
178 
179 	/* collect various data from sdram for pmc_scratch24 */
180 	scratch24.word = 0;
181 	scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
182 	scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
183 	scratch24.warmboot_wait = sdram.warm_boot_wait;
184 	writel(scratch24.word, &pmc->pmc_scratch24);
185 
186 	return 0;
187 }
188 
get_major_version(void)189 static u32 get_major_version(void)
190 {
191 	u32 major_id;
192 	struct apb_misc_gp_ctlr *gp =
193 		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
194 
195 	major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
196 			HIDREV_MAJORPREV_SHIFT;
197 	return major_id;
198 }
199 
is_production_mode_fuse_set(struct fuse_regs * fuse)200 static int is_production_mode_fuse_set(struct fuse_regs *fuse)
201 {
202 	return readl(&fuse->production_mode);
203 }
204 
is_odm_production_mode_fuse_set(struct fuse_regs * fuse)205 static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
206 {
207 	return readl(&fuse->security_mode);
208 }
209 
is_failure_analysis_mode(struct fuse_regs * fuse)210 static int is_failure_analysis_mode(struct fuse_regs *fuse)
211 {
212 	return readl(&fuse->fa);
213 }
214 
ap20_is_odm_production_mode(void)215 static int ap20_is_odm_production_mode(void)
216 {
217 	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
218 
219 	if (!is_failure_analysis_mode(fuse) &&
220 	    is_odm_production_mode_fuse_set(fuse))
221 		return 1;
222 	else
223 		return 0;
224 }
225 
ap20_is_production_mode(void)226 static int ap20_is_production_mode(void)
227 {
228 	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
229 
230 	if (get_major_version() == 0)
231 		return 1;
232 
233 	if (!is_failure_analysis_mode(fuse) &&
234 	    is_production_mode_fuse_set(fuse) &&
235 	    !is_odm_production_mode_fuse_set(fuse))
236 		return 1;
237 	else
238 		return 0;
239 }
240 
fuse_get_operation_mode(void)241 static enum fuse_operating_mode fuse_get_operation_mode(void)
242 {
243 	u32 chip_id;
244 	struct apb_misc_gp_ctlr *gp =
245 		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
246 
247 	chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
248 			HIDREV_CHIPID_SHIFT;
249 	if (chip_id == CHIPID_TEGRA20) {
250 		if (ap20_is_odm_production_mode()) {
251 			printf("!! odm_production_mode is not supported !!\n");
252 			return MODE_UNDEFINED;
253 		} else
254 			if (ap20_is_production_mode())
255 				return MODE_PRODUCTION;
256 			else
257 				return MODE_UNDEFINED;
258 	}
259 	return MODE_UNDEFINED;
260 }
261 
determine_crypto_options(int * is_encrypted,int * is_signed,int * use_zero_key)262 static void determine_crypto_options(int *is_encrypted, int *is_signed,
263 				     int *use_zero_key)
264 {
265 	switch (fuse_get_operation_mode()) {
266 	case MODE_PRODUCTION:
267 		*is_encrypted = 0;
268 		*is_signed = 1;
269 		*use_zero_key = 1;
270 		break;
271 	case MODE_UNDEFINED:
272 	default:
273 		*is_encrypted = 0;
274 		*is_signed = 0;
275 		*use_zero_key  = 0;
276 		break;
277 	}
278 }
279 
sign_wb_code(u32 start,u32 length,int use_zero_key)280 static int sign_wb_code(u32 start, u32 length, int use_zero_key)
281 {
282 	int err;
283 	u8 *source;		/* Pointer to source */
284 	u8 *hash;
285 
286 	/* Calculate AES block parameters. */
287 	source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
288 	length -= offsetof(struct wb_header, random_aes_block);
289 	hash = (u8 *)(start + offsetof(struct wb_header, hash));
290 	err = sign_data_block(source, length, hash);
291 
292 	return err;
293 }
294 
warmboot_prepare_code(u32 seg_address,u32 seg_length)295 int warmboot_prepare_code(u32 seg_address, u32 seg_length)
296 {
297 	int err = 0;
298 	u32 length;			/* length of the signed/encrypt code */
299 	struct wb_header *dst_header;	/* Pointer to dest WB header */
300 	int is_encrypted;		/* Segment is encrypted */
301 	int is_signed;			/* Segment is signed */
302 	int use_zero_key;		/* Use key of all zeros */
303 
304 	/* Determine crypto options. */
305 	determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
306 
307 	/* Get the actual code limits. */
308 	length = roundup(((u32)wb_end - (u32)wb_start), 16);
309 
310 	/*
311 	 * The region specified by seg_address must be in SDRAM and must be
312 	 * nonzero in length.
313 	 */
314 	if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
315 		seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
316 		err = -EFAULT;
317 		goto fail;
318 	}
319 
320 	/* Things must be 16-byte aligned. */
321 	if ((seg_length & 0xF) || (seg_address & 0xF)) {
322 		err = -EINVAL;
323 		goto fail;
324 	}
325 
326 	/* Will the code fit? (destination includes wb_header + wb code) */
327 	if (seg_length < (length + sizeof(struct wb_header))) {
328 		err = -EINVAL;
329 		goto fail;
330 	}
331 
332 	dst_header = (struct wb_header *)seg_address;
333 	memset((char *)dst_header, 0, sizeof(struct wb_header));
334 
335 	/* Populate the random_aes_block as requested. */
336 	{
337 		u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
338 		u32 *end = (u32 *)(((u32)aes_block) +
339 				   sizeof(dst_header->random_aes_block));
340 
341 		do {
342 			*aes_block++ = 0;
343 		} while (aes_block < end);
344 	}
345 
346 	/* Populate the header. */
347 	dst_header->length_insecure = length + sizeof(struct wb_header);
348 	dst_header->length_secure = length + sizeof(struct wb_header);
349 	dst_header->destination = NV_WB_RUN_ADDRESS;
350 	dst_header->entry_point = NV_WB_RUN_ADDRESS;
351 	dst_header->code_length = length;
352 
353 	if (is_encrypted) {
354 		printf("!!!! Encryption is not supported !!!!\n");
355 		dst_header->length_insecure = 0;
356 		err = -EACCES;
357 		goto fail;
358 	} else
359 		/* copy the wb code directly following dst_header. */
360 		memcpy((char *)(dst_header+1), (char *)wb_start, length);
361 
362 	if (is_signed)
363 		err = sign_wb_code(seg_address, dst_header->length_insecure,
364 				   use_zero_key);
365 
366 fail:
367 	if (err)
368 		printf("Warning: warmboot code copy failed (error=%d)\n", err);
369 
370 	return err;
371 }
372