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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2009
4  * Marek Vasut <marek.vasut@gmail.com>
5  *
6  * Heavily based on pxa255_idp platform
7  */
8 
9 #include <common.h>
10 #include <command.h>
11 #include <serial.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/pxa.h>
14 #include <asm/arch/regs-mmc.h>
15 #include <spi.h>
16 #include <asm/io.h>
17 #include <usb.h>
18 #include <asm/mach-types.h>
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 
22 #ifdef	CONFIG_CMD_SPI
23 void lcd_start(void);
24 #else
lcd_start(void)25 inline void lcd_start(void) {};
26 #endif
27 
28 /*
29  * Miscelaneous platform dependent initialisations
30  */
board_init(void)31 int board_init(void)
32 {
33 	/* arch number of Z2 */
34 	gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
35 
36 	/* adress of boot parameters */
37 	gd->bd->bi_boot_params = 0xa0000100;
38 
39 	/* Enable LCD */
40 	lcd_start();
41 
42 	return 0;
43 }
44 
dram_init(void)45 int dram_init(void)
46 {
47 	pxa2xx_dram_init();
48 	gd->ram_size = PHYS_SDRAM_1_SIZE;
49 	return 0;
50 }
51 
52 #ifdef	CONFIG_CMD_USB
board_usb_init(int index,enum usb_init_type init)53 int board_usb_init(int index, enum usb_init_type init)
54 {
55 	/* enable port 2 */
56 	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
57 		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
58 
59 	return 0;
60 }
61 
board_usb_cleanup(int index,enum usb_init_type init)62 int board_usb_cleanup(int index, enum usb_init_type init)
63 {
64 	return 0;
65 }
66 
usb_board_stop(void)67 void usb_board_stop(void)
68 {
69 }
70 #endif
71 
dram_init_banksize(void)72 int dram_init_banksize(void)
73 {
74 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
75 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
76 
77 	return 0;
78 }
79 
80 #ifdef	CONFIG_CMD_MMC
board_mmc_init(bd_t * bis)81 int board_mmc_init(bd_t *bis)
82 {
83 	pxa_mmc_register(0);
84 	return 0;
85 }
86 #endif
87 
88 #ifdef	CONFIG_CMD_SPI
89 
90 struct {
91 	unsigned char	reg;
92 	unsigned short	data;
93 	unsigned char	mdelay;
94 } lcd_data[] = {
95 	{ 0x07,	0x0000,	0 },
96 	{ 0x13,	0x0000,	10 },
97 	{ 0x11,	0x3004,	0 },
98 	{ 0x14,	0x200F,	0 },
99 	{ 0x10,	0x1a20,	0 },
100 	{ 0x13,	0x0040,	50 },
101 	{ 0x13,	0x0060,	0 },
102 	{ 0x13,	0x0070,	200 },
103 	{ 0x01,	0x0127,	0 },
104 	{ 0x02,	0x0700,	0 },
105 	{ 0x03,	0x1030,	0 },
106 	{ 0x08,	0x0208,	0 },
107 	{ 0x0B,	0x0620,	0 },
108 	{ 0x0C,	0x0110,	0 },
109 	{ 0x30,	0x0120,	0 },
110 	{ 0x31,	0x0127,	0 },
111 	{ 0x32,	0x0000,	0 },
112 	{ 0x33,	0x0503,	0 },
113 	{ 0x34,	0x0727,	0 },
114 	{ 0x35,	0x0124,	0 },
115 	{ 0x36,	0x0706,	0 },
116 	{ 0x37,	0x0701,	0 },
117 	{ 0x38,	0x0F00,	0 },
118 	{ 0x39,	0x0F00,	0 },
119 	{ 0x40,	0x0000,	0 },
120 	{ 0x41,	0x0000,	0 },
121 	{ 0x42,	0x013f,	0 },
122 	{ 0x43,	0x0000,	0 },
123 	{ 0x44,	0x013f,	0 },
124 	{ 0x45,	0x0000,	0 },
125 	{ 0x46,	0xef00,	0 },
126 	{ 0x47,	0x013f,	0 },
127 	{ 0x48,	0x0000,	0 },
128 	{ 0x07,	0x0015,	30 },
129 	{ 0x07,	0x0017,	0 },
130 	{ 0x20,	0x0000,	0 },
131 	{ 0x21,	0x0000,	0 },
132 	{ 0x22,	0x0000,	0 },
133 };
134 
zipitz2_spi_sda(int set)135 void zipitz2_spi_sda(int set)
136 {
137 	/* GPIO 13 */
138 	if (set)
139 		writel((1 << 13), GPSR0);
140 	else
141 		writel((1 << 13), GPCR0);
142 }
143 
zipitz2_spi_scl(int set)144 void zipitz2_spi_scl(int set)
145 {
146 	/* GPIO 22 */
147 	if (set)
148 		writel((1 << 22), GPCR0);
149 	else
150 		writel((1 << 22), GPSR0);
151 }
152 
zipitz2_spi_read(void)153 unsigned char zipitz2_spi_read(void)
154 {
155 	/* GPIO 40 */
156 	return !!(readl(GPLR1) & (1 << 8));
157 }
158 
spi_cs_is_valid(unsigned int bus,unsigned int cs)159 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
160 {
161 	/* Always valid */
162 	return 1;
163 }
164 
spi_cs_activate(struct spi_slave * slave)165 void spi_cs_activate(struct spi_slave *slave)
166 {
167 	/* GPIO 88 low */
168 	writel((1 << 24), GPCR2);
169 }
170 
spi_cs_deactivate(struct spi_slave * slave)171 void spi_cs_deactivate(struct spi_slave *slave)
172 {
173 	/* GPIO 88 high */
174 	writel((1 << 24), GPSR2);
175 }
176 
lcd_start(void)177 void lcd_start(void)
178 {
179 	int i;
180 	unsigned char reg[3] = { 0x74, 0x00, 0 };
181 	unsigned char data[3] = { 0x76, 0, 0 };
182 	unsigned char dummy[3] = { 0, 0, 0 };
183 
184 	/* PWM2 AF */
185 	writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
186 	/* Enable clock to all PWM */
187 	writel(readl(CKEN) | 0x3, CKEN);
188 	/* Configure PWM2 */
189 	writel(0x4f, PWM_CTRL2);
190 	writel(0x2ff, PWM_PWDUTY2);
191 	writel(792, PWM_PERVAL2);
192 
193 	/* Toggle the reset pin to reset the LCD */
194 	writel((1 << 19), GPSR0);
195 	udelay(100000);
196 	writel((1 << 19), GPCR0);
197 	udelay(20000);
198 	writel((1 << 19), GPSR0);
199 	udelay(20000);
200 
201 	/* Program the LCD init sequence */
202 	for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
203 		reg[0] = 0x74;
204 		reg[1] = 0x0;
205 		reg[2] = lcd_data[i].reg;
206 		spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
207 
208 		data[0] = 0x76;
209 		data[1] = lcd_data[i].data >> 8;
210 		data[2] = lcd_data[i].data & 0xff;
211 		spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
212 
213 		if (lcd_data[i].mdelay)
214 			udelay(lcd_data[i].mdelay * 1000);
215 	}
216 
217 	writel((1 << 11), GPSR0);
218 }
219 #endif
220