1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2015 - 2016, Xilinx, Inc,
4 * Michal Simek <michal.simek@xilinx.com>
5 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
6 */
7
8 #include <console.h>
9 #include <common.h>
10 #include <zynqmppl.h>
11 #include <linux/sizes.h>
12 #include <asm/arch/sys_proto.h>
13 #include <memalign.h>
14
15 #define DUMMY_WORD 0xffffffff
16
17 /* Xilinx binary format header */
18 static const u32 bin_format[] = {
19 DUMMY_WORD, /* Dummy words */
20 DUMMY_WORD,
21 DUMMY_WORD,
22 DUMMY_WORD,
23 DUMMY_WORD,
24 DUMMY_WORD,
25 DUMMY_WORD,
26 DUMMY_WORD,
27 DUMMY_WORD,
28 DUMMY_WORD,
29 DUMMY_WORD,
30 DUMMY_WORD,
31 DUMMY_WORD,
32 DUMMY_WORD,
33 DUMMY_WORD,
34 DUMMY_WORD,
35 0x000000bb, /* Sync word */
36 0x11220044, /* Sync word */
37 DUMMY_WORD,
38 DUMMY_WORD,
39 0xaa995566, /* Sync word */
40 };
41
42 #define SWAP_NO 1
43 #define SWAP_DONE 2
44
45 /*
46 * Load the whole word from unaligned buffer
47 * Keep in your mind that it is byte loading on little-endian system
48 */
load_word(const void * buf,u32 swap)49 static u32 load_word(const void *buf, u32 swap)
50 {
51 u32 word = 0;
52 u8 *bitc = (u8 *)buf;
53 int p;
54
55 if (swap == SWAP_NO) {
56 for (p = 0; p < 4; p++) {
57 word <<= 8;
58 word |= bitc[p];
59 }
60 } else {
61 for (p = 3; p >= 0; p--) {
62 word <<= 8;
63 word |= bitc[p];
64 }
65 }
66
67 return word;
68 }
69
check_header(const void * buf)70 static u32 check_header(const void *buf)
71 {
72 u32 i, pattern;
73 int swap = SWAP_NO;
74 u32 *test = (u32 *)buf;
75
76 debug("%s: Let's check bitstream header\n", __func__);
77
78 /* Checking that passing bin is not a bitstream */
79 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
80 pattern = load_word(&test[i], swap);
81
82 /*
83 * Bitstreams in binary format are swapped
84 * compare to regular bistream.
85 * Do not swap dummy word but if swap is done assume
86 * that parsing buffer is binary format
87 */
88 if ((__swab32(pattern) != DUMMY_WORD) &&
89 (__swab32(pattern) == bin_format[i])) {
90 swap = SWAP_DONE;
91 debug("%s: data swapped - let's swap\n", __func__);
92 }
93
94 debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
95 &test[i], pattern, bin_format[i]);
96 }
97 debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
98 buf, swap == SWAP_NO ? "without" : "with");
99
100 return swap;
101 }
102
check_data(u8 * buf,size_t bsize,u32 * swap)103 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
104 {
105 u32 word, p = 0; /* possition */
106
107 /* Because buf doesn't need to be aligned let's read it by chars */
108 for (p = 0; p < bsize; p++) {
109 word = load_word(&buf[p], SWAP_NO);
110 debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
111
112 /* Find the first bitstream dummy word */
113 if (word == DUMMY_WORD) {
114 debug("%s: Found dummy word at position %x/%px\n",
115 __func__, p, &buf[p]);
116 *swap = check_header(&buf[p]);
117 if (*swap) {
118 /* FIXME add full bitstream checking here */
119 return &buf[p];
120 }
121 }
122 /* Loop can be huge - support CTRL + C */
123 if (ctrlc())
124 return NULL;
125 }
126 return NULL;
127 }
128
zynqmp_align_dma_buffer(u32 * buf,u32 len,u32 swap)129 static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
130 {
131 u32 *new_buf;
132 u32 i;
133
134 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
135 new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
136
137 /*
138 * This might be dangerous but permits to flash if
139 * ARCH_DMA_MINALIGN is greater than header size
140 */
141 if (new_buf > (u32 *)buf) {
142 debug("%s: Aligned buffer is after buffer start\n",
143 __func__);
144 new_buf -= ARCH_DMA_MINALIGN;
145 }
146 printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
147 buf, new_buf, swap);
148
149 for (i = 0; i < (len/4); i++)
150 new_buf[i] = load_word(&buf[i], swap);
151
152 buf = new_buf;
153 } else if (swap != SWAP_DONE) {
154 /* For bitstream which are aligned */
155 u32 *new_buf = (u32 *)buf;
156
157 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
158 swap);
159
160 for (i = 0; i < (len/4); i++)
161 new_buf[i] = load_word(&buf[i], swap);
162 }
163
164 return (ulong)buf;
165 }
166
zynqmp_validate_bitstream(xilinx_desc * desc,const void * buf,size_t bsize,u32 blocksize,u32 * swap)167 static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
168 size_t bsize, u32 blocksize, u32 *swap)
169 {
170 ulong *buf_start;
171 ulong diff;
172
173 buf_start = check_data((u8 *)buf, blocksize, swap);
174
175 if (!buf_start)
176 return FPGA_FAIL;
177
178 /* Check if data is postpone from start */
179 diff = (ulong)buf_start - (ulong)buf;
180 if (diff) {
181 printf("%s: Bitstream is not validated yet (diff %lx)\n",
182 __func__, diff);
183 return FPGA_FAIL;
184 }
185
186 if ((ulong)buf < SZ_1M) {
187 printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
188 __func__, buf);
189 return FPGA_FAIL;
190 }
191
192 return 0;
193 }
194
zynqmp_load(xilinx_desc * desc,const void * buf,size_t bsize,bitstream_type bstype)195 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
196 bitstream_type bstype)
197 {
198 ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
199 u32 swap;
200 ulong bin_buf;
201 int ret;
202 u32 buf_lo, buf_hi;
203 u32 ret_payload[PAYLOAD_ARG_CNT];
204
205 if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
206 return FPGA_FAIL;
207
208 bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
209 bsizeptr = (u32 *)&bsize;
210
211 debug("%s called!\n", __func__);
212 flush_dcache_range(bin_buf, bin_buf + bsize);
213 flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
214
215 buf_lo = (u32)bin_buf;
216 buf_hi = upper_32_bits(bin_buf);
217 bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
218 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
219 (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
220 if (ret)
221 debug("PL FPGA LOAD fail\n");
222
223 return ret;
224 }
225
226 #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
zynqmp_loads(xilinx_desc * desc,const void * buf,size_t bsize,struct fpga_secure_info * fpga_sec_info)227 static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
228 struct fpga_secure_info *fpga_sec_info)
229 {
230 int ret;
231 u32 buf_lo, buf_hi;
232 u32 ret_payload[PAYLOAD_ARG_CNT];
233 u8 flag = 0;
234
235 flush_dcache_range((ulong)buf, (ulong)buf +
236 ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
237
238 if (!fpga_sec_info->encflag)
239 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
240
241 if (fpga_sec_info->userkey_addr &&
242 fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
243 flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
244 (ulong)fpga_sec_info->userkey_addr +
245 ALIGN(KEY_PTR_LEN,
246 CONFIG_SYS_CACHELINE_SIZE));
247 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
248 }
249
250 if (!fpga_sec_info->authflag)
251 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
252
253 if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
254 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
255
256 buf_lo = lower_32_bits((ulong)buf);
257 buf_hi = upper_32_bits((ulong)buf);
258
259 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
260 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
261 flag, ret_payload);
262 if (ret)
263 puts("PL FPGA LOAD fail\n");
264 else
265 puts("Bitstream successfully loaded\n");
266
267 return ret;
268 }
269 #endif
270
zynqmp_pcap_info(xilinx_desc * desc)271 static int zynqmp_pcap_info(xilinx_desc *desc)
272 {
273 int ret;
274 u32 ret_payload[PAYLOAD_ARG_CNT];
275
276 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
277 0, ret_payload);
278 if (!ret)
279 printf("PCAP status\t0x%x\n", ret_payload[1]);
280
281 return ret;
282 }
283
284 struct xilinx_fpga_op zynqmp_op = {
285 .load = zynqmp_load,
286 #if defined CONFIG_CMD_FPGA_LOAD_SECURE
287 .loads = zynqmp_loads,
288 #endif
289 .info = zynqmp_pcap_info,
290 };
291