| /external/llvm/test/ObjectYAML/MachO/ |
| D | lazy_bind_opcode.yaml | 66 Imm: 2
70 Imm: 1
72 Imm: 0
75 Imm: 0
77 Imm: 0
79 Imm: 2
83 Imm: 1
85 Imm: 0
88 Imm: 0
90 Imm: 0
[all …]
|
| D | bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | weak_bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | out_of_order_linkedit.yaml | 144 Imm: 1
146 Imm: 2
150 Imm: 0
154 Imm: 0
157 Imm: 1
160 Imm: 0
163 Imm: 1
166 Imm: 2
171 Imm: 0
174 Imm: 0
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/ObjectYAML/MachO/ |
| D | lazy_bind_opcode.yaml | 66 Imm: 2
70 Imm: 1
72 Imm: 0
75 Imm: 0
77 Imm: 0
79 Imm: 2
83 Imm: 1
85 Imm: 0
88 Imm: 0
90 Imm: 0
[all …]
|
| D | weak_bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | out_of_order_linkedit.yaml | 144 Imm: 1
146 Imm: 2
150 Imm: 0
154 Imm: 0
157 Imm: 1
160 Imm: 0
163 Imm: 1
166 Imm: 2
171 Imm: 0
174 Imm: 0
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoC.td | 24 return isUInt<6>(Imm) && (Imm != 0);
25 return isUInt<5>(Imm) && (Imm != 0);
31 int64_t Imm;
32 if (!MCOp.evaluateAsConstantImm(Imm))
35 return isUInt<6>(Imm) && (Imm != 0);
36 return isUInt<5>(Imm) && (Imm != 0);
40 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
45 int64_t Imm;
46 if (MCOp.evaluateAsConstantImm(Imm))
47 return isInt<6>(Imm);
[all …]
|
| /external/mesa3d/src/intel/compiler/ |
| D | brw_fs_combine_constants.cpp | 101 struct imm { struct
142 struct imm *imm; argument
147 static struct imm *
151 if (table->imm[i].val == val) { in find_imm()
152 return &table->imm[i]; in find_imm()
158 static struct imm *
163 table->imm = reralloc(mem_ctx, table->imm, struct imm, table->size); in new_imm()
165 return &table->imm[table->len++]; in new_imm()
169 * Comparator used for sorting an array of imm structures.
179 const struct imm *a = (const struct imm *)_a, in compare()
[all …]
|
| /external/clang/lib/Headers/ |
| D | avx512bwintrin.h | 1632 #define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \ argument
1636 4 + (((imm) >> 0) & 0x3), \
1637 4 + (((imm) >> 2) & 0x3), \
1638 4 + (((imm) >> 4) & 0x3), \
1639 4 + (((imm) >> 6) & 0x3), \
1641 12 + (((imm) >> 0) & 0x3), \
1642 12 + (((imm) >> 2) & 0x3), \
1643 12 + (((imm) >> 4) & 0x3), \
1644 12 + (((imm) >> 6) & 0x3), \
1646 20 + (((imm) >> 0) & 0x3), \
[all …]
|
| D | avx2intrin.h | 498 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \ argument
501 0 + (((imm) >> 0) & 0x3), \
502 0 + (((imm) >> 2) & 0x3), \
503 0 + (((imm) >> 4) & 0x3), \
504 0 + (((imm) >> 6) & 0x3), \
505 4 + (((imm) >> 0) & 0x3), \
506 4 + (((imm) >> 2) & 0x3), \
507 4 + (((imm) >> 4) & 0x3), \
508 4 + (((imm) >> 6) & 0x3)); })
510 #define _mm256_shufflehi_epi16(a, imm) __extension__ ({ \ argument
[all …]
|
| /external/virglrenderer/tests/ |
| D | large_shader.h | 14 IMM[0] FLT32 {0x40000000, 0xbf800000, 0x00000000, 0x3f7fffff}
15 IMM[1] FLT32 {0xbf3504f4, 0x3f3504f4, 0x00000000, 0x3fb504f3}
16 IMM[2] FLT32 {0xbf87c3b7, 0x80000000, 0xbf733333, 0x41000000}
17 IMM[3] UINT32 {0, 4294967295, 0, 0}
18 IMM[4] INT32 {0, 32, 1, 0}
19 IMM[5] FLT32 {0x3f6e147b, 0x00000000, 0x40400000, 0x42e20000}
20 IMM[6] FLT32 {0x42640000, 0x3f000000, 0x472aee8c, 0x3f800000}
21 IMM[7] FLT32 {0x42680000, 0x42e40000, 0x432a0000, 0x432b0000}
22 IMM[8] FLT32 {0xbf19999a, 0xbef5c28f, 0x3f23d70a, 0x400147ae}
23 IMM[9] FLT32 {0xbf4ccccd, 0x3eb851ec, 0xbef5c28f, 0x3e800000}
[all …]
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrMemory.td | 83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
84 (LOAD_I32 imm:$off, $addr, 0)>;
85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
86 (LOAD_I64 imm:$off, $addr, 0)>;
87 def : Pat<(f32 (load (regPlusImm I32:$addr, imm:$off))),
88 (LOAD_F32 imm:$off, $addr, 0)>;
89 def : Pat<(f64 (load (regPlusImm I32:$addr, imm:$off))),
90 (LOAD_F64 imm:$off, $addr, 0)>;
91 def : Pat<(i32 (load (or_is_add I32:$addr, imm:$off))),
92 (LOAD_I32 imm:$off, $addr, 0)>;
[all …]
|
| /external/iproute2/include/ |
| D | bpf_util.h | 76 .imm = 0 })
84 .imm = 0 })
88 #define BPF_ALU64_IMM(OP, DST, IMM) \ argument
94 .imm = IMM })
96 #define BPF_ALU32_IMM(OP, DST, IMM) \ argument
102 .imm = IMM })
112 .imm = 0 })
120 .imm = 0 })
124 #define BPF_MOV64_IMM(DST, IMM) \ argument
130 .imm = IMM })
[all …]
|
| /external/mesa3d/src/gallium/auxiliary/postprocess/ |
| D | pp_mlaa.h | 55 "IMM FLT32 { 0.0030, 0.0000, 1.0000, 0.0000}\n"
67 " 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx\n"
68 " 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz\n"
69 " 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy\n"
86 "IMM FLT32 { 0.2126, 0.7152, 0.0722, 0.1000}\n"
87 "IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000}\n"
89 " 1: DP3 TEMP[0].x, TEMP[1].xyzz, IMM[0]\n"
91 " 3: DP3 TEMP[0].y, TEMP[1].xyzz, IMM[0].xyzz\n"
93 " 5: DP3 TEMP[0].z, TEMP[1].xyzz, IMM[0].xyzz\n"
95 " 7: DP3 TEMP[0].w, TEMP[1].xyzz, IMM[0].xyzz\n"
[all …]
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_64.c | 44 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in load_immediate() argument
51 if (imm <= SIMM_MAX && imm >= SIMM_MIN) in load_immediate()
52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
54 if (!(imm & ~0xffff)) in load_immediate()
55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
57 if (imm <= 0x7fffffffl && imm >= -0x80000000l) { in load_immediate()
58 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
63 tmp = (imm >= 0) ? imm : ~imm; in load_immediate()
67 tmp = (imm << shift); in load_immediate()
[all …]
|
| D | sljitNativePPC_32.c | 29 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in load_immediate() argument
31 if (imm <= SIMM_MAX && imm >= SIMM_MIN) in load_immediate()
32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
34 if (!(imm & ~0xffff)) in load_immediate()
35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
37 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
109 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); in emit_single_op()
112 …h_inst(compiler, ADDIS | D(dst) | A(src1) | (((compiler->imm >> 16) & 0xffff) + ((compiler->imm >>… in emit_single_op()
116 return push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)); in emit_single_op()
[all …]
|
| /external/v8/src/wasm/ |
| D | function-body-decoder-impl.h | 380 const BranchTableImmediate<validate>& imm) in BranchTableIterator() argument
382 start_(imm.start), in BranchTableIterator()
383 pc_(imm.table), in BranchTableIterator()
384 table_count_(imm.table_count) {} in BranchTableIterator()
628 F(GetLocal, Value* result, const LocalIndexImmediate<validate>& imm) \
629 F(SetLocal, const Value& value, const LocalIndexImmediate<validate>& imm) \
631 const LocalIndexImmediate<validate>& imm) \
632 F(GetGlobal, Value* result, const GlobalIndexImmediate<validate>& imm) \
633 F(SetGlobal, const Value& value, const GlobalIndexImmediate<validate>& imm) \
639 F(BrTable, const BranchTableImmediate<validate>& imm, const Value& key) \
[all …]
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 66 // b<cond> $imm
67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68 (BCOND brtarget:$imm, condVal)>;
70 // b<cond>,a $imm
71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72 (BCONDA brtarget:$imm, condVal)>;
74 // b<cond> %icc, $imm
75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 // b<cond>,pt %icc, $imm
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 66 // b<cond> $imm
67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68 (BCOND brtarget:$imm, condVal)>;
70 // b<cond>,a $imm
71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72 (BCONDA brtarget:$imm, condVal)>;
74 // b<cond> %icc, $imm
75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 // b<cond>,pt %icc, $imm
[all …]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIIntrinsics.td | 26 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
29 llvm_i32_ty, // inst_offset(imm)
30 llvm_i32_ty, // dfmt(imm)
31 llvm_i32_ty, // nfmt(imm)
32 llvm_i32_ty, // offen(imm)
33 llvm_i32_ty, // idxen(imm)
34 llvm_i32_ty, // glc(imm)
35 llvm_i32_ty, // slc(imm)
36 llvm_i32_ty], // tfe(imm)
45 llvm_i32_ty, // inst_offset(imm)
[all …]
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| /external/llvm/test/MC/Lanai/ |
| D | memory.s | 12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
28 ! CHECK-NEXT: <MCOperand Imm:0>
29 ! CHECK-NEXT: <MCOperand Imm:0>
36 ! CHECK-NEXT: <MCOperand Imm:291>
37 ! CHECK-NEXT: <MCOperand Imm:128>
44 ! CHECK-NEXT: <MCOperand Imm:-4>
45 ! CHECK-NEXT: <MCOperand Imm:128>
[all …]
|