| /external/swiftshader/third_party/subzero/tests_lit/reader_tests/ |
| D | select.ll | 9 %vc = trunc i32 %p to i1
12 %r = select i1 %vc, i1 %vt, i1 %ve
18 ; CHECK-NEXT: %vc = trunc i32 %p to i1
21 ; CHECK-NEXT: %r = select i1 %vc, i1 %vt, i1 %ve
27 %vc = trunc i32 %p to i1
30 %r = select i1 %vc, i8 %vt, i8 %ve
36 ; CHECK-NEXT: %vc = trunc i32 %p to i1
39 ; CHECK-NEXT: %r = select i1 %vc, i8 %vt, i8 %ve
45 %vc = trunc i32 %p to i1
48 %r = select i1 %vc, i16 %vt, i16 %ve
[all …]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-operand-rn-in-it-block-t32.cc | 1671 {{vc, r0, r0}, true, vc, "vc r0 r0", "vc_r0_r0"},
1672 {{vc, r0, r1}, true, vc, "vc r0 r1", "vc_r0_r1"},
1673 {{vc, r0, r2}, true, vc, "vc r0 r2", "vc_r0_r2"},
1674 {{vc, r0, r3}, true, vc, "vc r0 r3", "vc_r0_r3"},
1675 {{vc, r0, r4}, true, vc, "vc r0 r4", "vc_r0_r4"},
1676 {{vc, r0, r5}, true, vc, "vc r0 r5", "vc_r0_r5"},
1677 {{vc, r0, r6}, true, vc, "vc r0 r6", "vc_r0_r6"},
1678 {{vc, r0, r7}, true, vc, "vc r0 r7", "vc_r0_r7"},
1679 {{vc, r0, r8}, true, vc, "vc r0 r8", "vc_r0_r8"},
1680 {{vc, r0, r9}, true, vc, "vc r0 r9", "vc_r0_r9"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc | 543 {{vc, r0, r0}, true, vc, "vc r0 r0", "vc_r0_r0"},
544 {{vc, r0, r1}, true, vc, "vc r0 r1", "vc_r0_r1"},
545 {{vc, r0, r2}, true, vc, "vc r0 r2", "vc_r0_r2"},
546 {{vc, r0, r3}, true, vc, "vc r0 r3", "vc_r0_r3"},
547 {{vc, r0, r4}, true, vc, "vc r0 r4", "vc_r0_r4"},
548 {{vc, r0, r5}, true, vc, "vc r0 r5", "vc_r0_r5"},
549 {{vc, r0, r6}, true, vc, "vc r0 r6", "vc_r0_r6"},
550 {{vc, r0, r7}, true, vc, "vc r0 r7", "vc_r0_r7"},
551 {{vc, r1, r0}, true, vc, "vc r1 r0", "vc_r1_r0"},
552 {{vc, r1, r1}, true, vc, "vc r1 r1", "vc_r1_r1"},
[all …]
|
| D | test-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc | 95 const TestData kTests[] = {{{vc, r1, 111}, true, vc, "vc r1 111", "vc_r1_111"},
109 {{vc, r7, 207}, true, vc, "vc r7 207", "vc_r7_207"},
119 {{vc, r0, 217}, true, vc, "vc r0 217", "vc_r0_217"},
139 {{vc, r6, 221}, true, vc, "vc r6 221", "vc_r6_221"},
144 {{vc, r3, 28}, true, vc, "vc r3 28", "vc_r3_28"},
161 {{vc, r5, 205}, true, vc, "vc r5 205", "vc_r5_205"},
174 {{vc, r1, 31}, true, vc, "vc r1 31", "vc_r1_31"},
206 {{vc, r1, 24}, true, vc, "vc r1 24", "vc_r1_24"},
222 {{vc, r3, 8}, true, vc, "vc r3 8", "vc_r3_8"},
226 {{vc, r6, 4}, true, vc, "vc r6 4", "vc_r6_4"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc | 98 {{vc, r6, r6, 138}, true, vc, "vc r6 r6 138", "vc_r6_r6_138"},
102 {{vc, r5, r5, 114}, true, vc, "vc r5 r5 114", "vc_r5_r5_114"},
112 {{vc, r0, r0, 83}, true, vc, "vc r0 r0 83", "vc_r0_r0_83"},
134 {{vc, r0, r0, 2}, true, vc, "vc r0 r0 2", "vc_r0_r0_2"},
144 {{vc, r3, r3, 203}, true, vc, "vc r3 r3 203", "vc_r3_r3_203"},
152 {{vc, r7, r7, 11}, true, vc, "vc r7 r7 11", "vc_r7_r7_11"},
177 {{vc, r0, r0, 200}, true, vc, "vc r0 r0 200", "vc_r0_r0_200"},
184 {{vc, r3, r3, 107}, true, vc, "vc r3 r3 107", "vc_r3_r3_107"},
195 {{vc, r2, r2, 69}, true, vc, "vc r2 r2 69", "vc_r2_r2_69"},
196 {{vc, r7, r7, 167}, true, vc, "vc r7 r7 167", "vc_r7_r7_167"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc | 543 {{vc, r0, r0, r0}, true, vc, "vc r0 r0 r0", "vc_r0_r0_r0"},
544 {{vc, r0, r1, r0}, true, vc, "vc r0 r1 r0", "vc_r0_r1_r0"},
545 {{vc, r0, r2, r0}, true, vc, "vc r0 r2 r0", "vc_r0_r2_r0"},
546 {{vc, r0, r3, r0}, true, vc, "vc r0 r3 r0", "vc_r0_r3_r0"},
547 {{vc, r0, r4, r0}, true, vc, "vc r0 r4 r0", "vc_r0_r4_r0"},
548 {{vc, r0, r5, r0}, true, vc, "vc r0 r5 r0", "vc_r0_r5_r0"},
549 {{vc, r0, r6, r0}, true, vc, "vc r0 r6 r0", "vc_r0_r6_r0"},
550 {{vc, r0, r7, r0}, true, vc, "vc r0 r7 r0", "vc_r0_r7_r0"},
551 {{vc, r1, r0, r1}, true, vc, "vc r1 r0 r1", "vc_r1_r0_r1"},
552 {{vc, r1, r1, r1}, true, vc, "vc r1 r1 r1", "vc_r1_r1_r1"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc | 543 {{vc, r0, r0, 0}, true, vc, "vc r0 r0 0", "vc_r0_r0_0"},
544 {{vc, r0, r1, 0}, true, vc, "vc r0 r1 0", "vc_r0_r1_0"},
545 {{vc, r0, r2, 0}, true, vc, "vc r0 r2 0", "vc_r0_r2_0"},
546 {{vc, r0, r3, 0}, true, vc, "vc r0 r3 0", "vc_r0_r3_0"},
547 {{vc, r0, r4, 0}, true, vc, "vc r0 r4 0", "vc_r0_r4_0"},
548 {{vc, r0, r5, 0}, true, vc, "vc r0 r5 0", "vc_r0_r5_0"},
549 {{vc, r0, r6, 0}, true, vc, "vc r0 r6 0", "vc_r0_r6_0"},
550 {{vc, r0, r7, 0}, true, vc, "vc r0 r7 0", "vc_r0_r7_0"},
551 {{vc, r1, r0, 0}, true, vc, "vc r1 r0 0", "vc_r1_r0_0"},
552 {{vc, r1, r1, 0}, true, vc, "vc r1 r1 0", "vc_r1_r1_0"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc | 109 {{vc, r5, r2, 5}, true, vc, "vc r5 r2 5", "vc_r5_r2_5"},
115 {{vc, r1, r2, 0}, true, vc, "vc r1 r2 0", "vc_r1_r2_0"},
144 {{vc, r4, r2, 7}, true, vc, "vc r4 r2 7", "vc_r4_r2_7"},
184 {{vc, r1, r7, 1}, true, vc, "vc r1 r7 1", "vc_r1_r7_1"},
196 {{vc, r3, r4, 3}, true, vc, "vc r3 r4 3", "vc_r3_r4_3"},
201 {{vc, r3, r0, 3}, true, vc, "vc r3 r0 3", "vc_r3_r0_3"},
219 {{vc, r0, r2, 3}, true, vc, "vc r0 r2 3", "vc_r0_r2_3"},
247 {{vc, r5, r5, 4}, true, vc, "vc r5 r5 4", "vc_r5_r5_4"},
248 {{vc, r7, r2, 5}, true, vc, "vc r7 r2 5", "vc_r7_r2_5"},
262 {{vc, r5, r1, 6}, true, vc, "vc r5 r1 6", "vc_r5_r1_6"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc | 100 {{vc, r4, r4, ROR, r1}, true, vc, "vc r4 r4 ROR r1", "vc_r4_r4_ROR_r1"},
102 {{vc, r4, r4, LSR, r4}, true, vc, "vc r4 r4 LSR r4", "vc_r4_r4_LSR_r4"},
134 {{vc, r5, r5, ROR, r3}, true, vc, "vc r5 r5 ROR r3", "vc_r5_r5_ROR_r3"},
138 {{vc, r6, r6, ASR, r7}, true, vc, "vc r6 r6 ASR r7", "vc_r6_r6_ASR_r7"},
155 {{vc, r3, r3, LSR, r7}, true, vc, "vc r3 r3 LSR r7", "vc_r3_r3_LSR_r7"},
157 {{vc, r1, r1, LSL, r7}, true, vc, "vc r1 r1 LSL r7", "vc_r1_r1_LSL_r7"},
169 {{vc, r2, r2, LSR, r7}, true, vc, "vc r2 r2 LSR r7", "vc_r2_r2_LSR_r7"},
187 {{vc, r6, r6, LSL, r0}, true, vc, "vc r6 r6 LSL r0", "vc_r6_r6_LSL_r0"},
198 {{vc, r5, r5, LSR, r3}, true, vc, "vc r5 r5 LSR r3", "vc_r5_r5_LSR_r3"},
199 {{vc, r4, r4, LSL, r4}, true, vc, "vc r4 r4 LSL r4", "vc_r4_r4_LSL_r4"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc | 104 {{vc, r2, r2, LSL, 22}, true, vc, "vc r2 r2 LSL 22", "vc_r2_r2_LSL_22"},
127 {{vc, r0, r5, LSL, 20}, true, vc, "vc r0 r5 LSL 20", "vc_r0_r5_LSL_20"},
129 {{vc, r6, r0, LSL, 13}, true, vc, "vc r6 r0 LSL 13", "vc_r6_r0_LSL_13"},
134 {{vc, r5, r6, LSL, 5}, true, vc, "vc r5 r6 LSL 5", "vc_r5_r6_LSL_5"},
145 {{vc, r6, r3, LSL, 17}, true, vc, "vc r6 r3 LSL 17", "vc_r6_r3_LSL_17"},
157 {{vc, r6, r6, LSL, 31}, true, vc, "vc r6 r6 LSL 31", "vc_r6_r6_LSL_31"},
160 {{vc, r6, r4, LSL, 20}, true, vc, "vc r6 r4 LSL 20", "vc_r6_r4_LSL_20"},
180 {{vc, r3, r7, LSL, 25}, true, vc, "vc r3 r7 LSL 25", "vc_r3_r7_LSL_25"},
188 {{vc, r3, r2, LSL, 24}, true, vc, "vc r3 r2 LSL 24", "vc_r3_r2_LSL_24"},
206 {{vc, r4, r2, LSL, 24}, true, vc, "vc r4 r2 LSL 24", "vc_r4_r2_LSL_24"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc | 103 {{vc, r4, r3, r4}, true, vc, "vc r4 r3 r4", "vc_r4_r3_r4"},
142 {{vc, r6, r2, r3}, true, vc, "vc r6 r2 r3", "vc_r6_r2_r3"},
148 {{vc, r4, r6, r3}, true, vc, "vc r4 r6 r3", "vc_r4_r6_r3"},
159 {{vc, r4, r1, r6}, true, vc, "vc r4 r1 r6", "vc_r4_r1_r6"},
160 {{vc, r5, r0, r1}, true, vc, "vc r5 r0 r1", "vc_r5_r0_r1"},
169 {{vc, r2, r0, r3}, true, vc, "vc r2 r0 r3", "vc_r2_r0_r3"},
176 {{vc, r0, r3, r7}, true, vc, "vc r0 r3 r7", "vc_r0_r3_r7"},
178 {{vc, r3, r0, r3}, true, vc, "vc r3 r0 r3", "vc_r3_r0_r3"},
198 {{vc, r7, r2, r6}, true, vc, "vc r7 r2 r6", "vc_r7_r2_r6"},
240 {{vc, r2, r1, r0}, true, vc, "vc r2 r1 r0", "vc_r2_r1_r0"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc | 100 {{vc, r11, r11, r0}, true, vc, "vc r11 r11 r0", "vc_r11_r11_r0"},
133 {{vc, r8, r8, r6}, true, vc, "vc r8 r8 r6", "vc_r8_r8_r6"},
143 {{vc, r6, r6, r14}, true, vc, "vc r6 r6 r14", "vc_r6_r6_r14"},
148 {{vc, r10, r10, r8}, true, vc, "vc r10 r10 r8", "vc_r10_r10_r8"},
151 {{vc, r1, r1, r7}, true, vc, "vc r1 r1 r7", "vc_r1_r1_r7"},
160 {{vc, r9, r9, r12}, true, vc, "vc r9 r9 r12", "vc_r9_r9_r12"},
177 {{vc, r9, r9, r11}, true, vc, "vc r9 r9 r11", "vc_r9_r9_r11"},
199 {{vc, r12, r12, r10}, true, vc, "vc r12 r12 r10", "vc_r12_r12_r10"},
207 {{vc, r13, r13, r2}, true, vc, "vc r13 r13 r2", "vc_r13_r13_r2"},
254 {{vc, r14, r14, r2}, true, vc, "vc r14 r14 r2", "vc_r14_r14_r2"},
[all …]
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| D | test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc | 137 {{vc, r0, r0, r3}, true, vc, "vc r0 r0 r3", "vc_r0_r0_r3"},
140 {{vc, r0, r0, r1}, true, vc, "vc r0 r0 r1", "vc_r0_r0_r1"},
181 {{vc, r4, r4, r2}, true, vc, "vc r4 r4 r2", "vc_r4_r4_r2"},
182 {{vc, r4, r4, r7}, true, vc, "vc r4 r4 r7", "vc_r4_r4_r7"},
198 {{vc, r4, r4, r1}, true, vc, "vc r4 r4 r1", "vc_r4_r4_r1"},
238 {{vc, r2, r2, r3}, true, vc, "vc r2 r2 r3", "vc_r2_r2_r3"},
295 {{vc, r0, r0, r5}, true, vc, "vc r0 r0 r5", "vc_r0_r0_r5"},
311 {{vc, r0, r0, r4}, true, vc, "vc r0 r0 r4", "vc_r0_r0_r4"},
312 {{vc, r4, r4, r5}, true, vc, "vc r4 r4 r5", "vc_r4_r4_r5"},
321 {{vc, r1, r1, r1}, true, vc, "vc r1 r1 r1", "vc_r1_r1_r1"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc | 112 {{vc, r2, r1, ASR, 29}, true, vc, "vc r2 r1 ASR 29", "vc_r2_r1_ASR_29"},
132 {{vc, r2, r5, ASR, 30}, true, vc, "vc r2 r5 ASR 30", "vc_r2_r5_ASR_30"},
143 {{vc, r0, r0, ASR, 18}, true, vc, "vc r0 r0 ASR 18", "vc_r0_r0_ASR_18"},
150 {{vc, r5, r3, LSR, 17}, true, vc, "vc r5 r3 LSR 17", "vc_r5_r3_LSR_17"},
160 {{vc, r0, r4, LSR, 6}, true, vc, "vc r0 r4 LSR 6", "vc_r0_r4_LSR_6"},
169 {{vc, r3, r4, ASR, 12}, true, vc, "vc r3 r4 ASR 12", "vc_r3_r4_ASR_12"},
189 {{vc, r3, r4, ASR, 3}, true, vc, "vc r3 r4 ASR 3", "vc_r3_r4_ASR_3"},
237 {{vc, r7, r2, LSR, 21}, true, vc, "vc r7 r2 LSR 21", "vc_r7_r2_LSR_21"},
247 {{vc, r4, r5, LSR, 3}, true, vc, "vc r4 r5 LSR 3", "vc_r4_r5_LSR_3"},
252 {{vc, r4, r6, LSR, 24}, true, vc, "vc r4 r6 LSR 24", "vc_r4_r6_LSR_24"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-a32.cc | 123 {{vc, r5, r14}, false, al, "vc r5 r14", "vc_r5_r14"},
143 {{vc, r10, r10}, false, al, "vc r10 r10", "vc_r10_r10"},
157 {{vc, r14, r2}, false, al, "vc r14 r2", "vc_r14_r2"},
192 {{vc, r6, r10}, false, al, "vc r6 r10", "vc_r6_r10"},
205 {{vc, r6, r9}, false, al, "vc r6 r9", "vc_r6_r9"},
208 {{vc, r4, r1}, false, al, "vc r4 r1", "vc_r4_r1"},
236 {{vc, r2, r8}, false, al, "vc r2 r8", "vc_r2_r8"},
240 {{vc, r5, r1}, false, al, "vc r5 r1", "vc_r5_r1"},
279 {{vc, r11, r8}, false, al, "vc r11 r8", "vc_r11_r8"},
287 {{vc, r1, r6}, false, al, "vc r1 r6", "vc_r1_r6"},
[all …]
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| D | test-macro-assembler-cond-rd-rn-pc-a32.cc | 304 {{vc, r0, r15}, "vc, r0, r15", "vc_r0_r15"},
305 {{vc, r1, r15}, "vc, r1, r15", "vc_r1_r15"},
306 {{vc, r2, r15}, "vc, r2, r15", "vc_r2_r15"},
307 {{vc, r3, r15}, "vc, r3, r15", "vc_r3_r15"},
308 {{vc, r4, r15}, "vc, r4, r15", "vc_r4_r15"},
309 {{vc, r5, r15}, "vc, r5, r15", "vc_r5_r15"},
310 {{vc, r6, r15}, "vc, r6, r15", "vc_r6_r15"},
311 {{vc, r7, r15}, "vc, r7, r15", "vc_r7_r15"},
312 {{vc, r8, r15}, "vc, r8, r15", "vc_r8_r15"},
313 {{vc, r9, r15}, "vc, r9, r15", "vc_r9_r15"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 115 {{vc, r8, r11, ASR, 13}, false, al, "vc r8 r11 ASR 13", "vc_r8_r11_ASR_13"},
125 {{vc, r6, r2, ASR, 9}, false, al, "vc r6 r2 ASR 9", "vc_r6_r2_ASR_9"},
129 {{vc, r5, r8, LSR, 5}, false, al, "vc r5 r8 LSR 5", "vc_r5_r8_LSR_5"},
133 {{vc, r9, r13, LSR, 16}, false, al, "vc r9 r13 LSR 16", "vc_r9_r13_LSR_16"},
152 {{vc, r6, r0, LSR, 13}, false, al, "vc r6 r0 LSR 13", "vc_r6_r0_LSR_13"},
177 {{vc, r7, r1, ASR, 12}, false, al, "vc r7 r1 ASR 12", "vc_r7_r1_ASR_12"},
190 {{vc, r2, r4, LSR, 23}, false, al, "vc r2 r4 LSR 23", "vc_r2_r4_LSR_23"},
240 {{vc, r0, r9, ASR, 23}, false, al, "vc r0 r9 ASR 23", "vc_r0_r9_ASR_23"},
251 {{vc, r9, r14, ASR, 28}, false, al, "vc r9 r14 ASR 28", "vc_r9_r14_ASR_28"},
271 {{vc, r7, r14, LSR, 11}, false, al, "vc r7 r14 LSR 11", "vc_r7_r14_LSR_11"},
[all …]
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| D | test-assembler-cond-rd-rn-operand-rm-rd-is-rn-is-sp-in-it-block-t32.cc | 200 {{vc, r13, r13, r0}, true, vc, "vc r13 r13 r0", "vc_r13_r13_r0"},
201 {{vc, r13, r13, r1}, true, vc, "vc r13 r13 r1", "vc_r13_r13_r1"},
202 {{vc, r13, r13, r2}, true, vc, "vc r13 r13 r2", "vc_r13_r13_r2"},
203 {{vc, r13, r13, r3}, true, vc, "vc r13 r13 r3", "vc_r13_r13_r3"},
204 {{vc, r13, r13, r4}, true, vc, "vc r13 r13 r4", "vc_r13_r13_r4"},
205 {{vc, r13, r13, r5}, true, vc, "vc r13 r13 r5", "vc_r13_r13_r5"},
206 {{vc, r13, r13, r6}, true, vc, "vc r13 r13 r6", "vc_r13_r13_r6"},
207 {{vc, r13, r13, r7}, true, vc, "vc r13 r13 r7", "vc_r13_r13_r7"},
208 {{vc, r13, r13, r8}, true, vc, "vc r13 r13 r8", "vc_r13_r13_r8"},
209 {{vc, r13, r13, r9}, true, vc, "vc r13 r13 r9", "vc_r13_r13_r9"},
[all …]
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| D | test-macro-assembler-cond-rd-rn-a32.cc | 101 {{vc, r7, r11}, "vc, r7, r11", "vc_r7_r11"},
156 {{vc, r14, r4}, "vc, r14, r4", "vc_r14_r4"},
157 {{vc, r1, r10}, "vc, r1, r10", "vc_r1_r10"},
160 {{vc, r14, r5}, "vc, r14, r5", "vc_r14_r5"},
163 {{vc, r7, r8}, "vc, r7, r8", "vc_r7_r8"},
186 {{vc, r14, r9}, "vc, r14, r9", "vc_r14_r9"},
216 {{vc, r13, r3}, "vc, r13, r3", "vc_r13_r3"},
217 {{vc, r8, r8}, "vc, r8, r8", "vc_r8_r8"},
235 {{vc, r0, r6}, "vc, r0, r6", "vc_r0_r6"},
249 {{vc, r4, r10}, "vc, r4, r10", "vc_r4_r10"},
[all …]
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| D | test-macro-assembler-cond-rd-rn-t32.cc | 101 {{vc, r7, r11}, "vc, r7, r11", "vc_r7_r11"},
156 {{vc, r14, r4}, "vc, r14, r4", "vc_r14_r4"},
157 {{vc, r1, r10}, "vc, r1, r10", "vc_r1_r10"},
160 {{vc, r14, r5}, "vc, r14, r5", "vc_r14_r5"},
163 {{vc, r7, r8}, "vc, r7, r8", "vc_r7_r8"},
186 {{vc, r14, r9}, "vc, r14, r9", "vc_r14_r9"},
216 {{vc, r13, r3}, "vc, r13, r3", "vc_r13_r3"},
217 {{vc, r8, r8}, "vc, r8, r8", "vc_r8_r8"},
235 {{vc, r0, r6}, "vc, r0, r6", "vc_r0_r6"},
249 {{vc, r4, r10}, "vc, r4, r10", "vc_r4_r10"},
[all …]
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| D | test-assembler-cond-rd-operand-const-cannot-use-pc-a32.cc | 124 {{vc, r10, 0xff000000},
127 "vc r10 0xff000000",
151 {{vc, r13, 0x0000ab00},
154 "vc r13 0x0000ab00",
174 {{vc, r13, 0x000000ab},
177 "vc r13 0x000000ab",
251 {{vc, r12, 0xf000000f},
254 "vc r12 0xf000000f",
282 {{vc, r12, 0xb000000a},
285 "vc r12 0xb000000a",
[all …]
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| /external/tremolo/Tremolo/ |
| D | treminfo.c | 58 void vorbis_comment_init(vorbis_comment *vc){ in vorbis_comment_init() argument
59 memset(vc,0,sizeof(*vc)); in vorbis_comment_init()
74 char *vorbis_comment_query(vorbis_comment *vc, char *tag, int count){ in vorbis_comment_query() argument
83 for(i=0;i<vc->comments;i++){ in vorbis_comment_query()
84 if(!tagcompare(vc->user_comments[i], fulltag, taglen)){ in vorbis_comment_query()
87 return vc->user_comments[i] + taglen; in vorbis_comment_query()
95 int vorbis_comment_query_count(vorbis_comment *vc, char *tag){ in vorbis_comment_query_count() argument
102 for(i=0;i<vc->comments;i++){ in vorbis_comment_query_count()
103 if(!tagcompare(vc->user_comments[i], fulltag, taglen)) in vorbis_comment_query_count()
110 void vorbis_comment_clear(vorbis_comment *vc){ in vorbis_comment_clear() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | swaps-le-2.ll | 14 ; vector char vc = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
23 ; vcr = (vector char){vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5],
24 ; vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5]};
38 @vc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i…
48 %0 = load <16 x i8>, <16 x i8>* @vc, align 8
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | swaps-le-2.ll | 7 ; vector char vc = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
16 ; vcr = (vector char){vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5],
17 ; vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5]};
31 @vc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i…
41 %0 = load <16 x i8>, <16 x i8>* @vc, align 16
|
| /external/mesa3d/src/gallium/drivers/nouveau/ |
| D | nouveau_vp3_video_bsp.c | 164 struct vc1_picparm_bsp *vc = (struct vc1_picparm_bsp *)map; in nouveau_vp3_fill_picparm_vc1_bsp() local
166 vc->width = dec->base.width; in nouveau_vp3_fill_picparm_vc1_bsp()
167 vc->height = dec->base.height; in nouveau_vp3_fill_picparm_vc1_bsp()
168 vc->profile = dec->base.profile - PIPE_VIDEO_PROFILE_VC1_SIMPLE; // 04 in nouveau_vp3_fill_picparm_vc1_bsp()
169 vc->postprocflag = d->postprocflag; in nouveau_vp3_fill_picparm_vc1_bsp()
170 vc->pulldown = d->pulldown; in nouveau_vp3_fill_picparm_vc1_bsp()
171 vc->interlaced = d->interlace; in nouveau_vp3_fill_picparm_vc1_bsp()
172 vc->tfcntrflag = d->tfcntrflag; // 08 in nouveau_vp3_fill_picparm_vc1_bsp()
173 vc->finterpflag = d->finterpflag; in nouveau_vp3_fill_picparm_vc1_bsp()
174 vc->psf = d->psf; in nouveau_vp3_fill_picparm_vc1_bsp()
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