| /external/curl/tests/data/ |
| D | test1060 | 23 And you should ignore this data. aaaaaaaaaaaaaaaa
24 And you should ignore this data. aaaaaaaaaaaaaaaa
25 And you should ignore this data. aaaaaaaaaaaaaaaa
26 And you should ignore this data. aaaaaaaaaaaaaaaa
27 And you should ignore this data. aaaaaaaaaaaaaaaa
28 And you should ignore this data. aaaaaaaaaaaaaaaa
29 And you should ignore this data. aaaaaaaaaaaaaaaa
30 And you should ignore this data. aaaaaaaaaaaaaaaa
31 And you should ignore this data. aaaaaaaaaaaaaaaa
32 And you should ignore this data. aaaaaaaaaaaaaaaa
[all …]
|
| D | test1061 | 25 And you should ignore this data. aaaaaaaaaaaaaaaa
26 And you should ignore this data. aaaaaaaaaaaaaaaa
27 And you should ignore this data. aaaaaaaaaaaaaaaa
28 And you should ignore this data. aaaaaaaaaaaaaaaa
29 And you should ignore this data. aaaaaaaaaaaaaaaa
30 And you should ignore this data. aaaaaaaaaaaaaaaa
31 And you should ignore this data. aaaaaaaaaaaaaaaa
32 And you should ignore this data. aaaaaaaaaaaaaaaa
33 And you should ignore this data. aaaaaaaaaaaaaaaa
34 And you should ignore this data. aaaaaaaaaaaaaaaa
[all …]
|
| /external/python/cpython3/Lib/test/decimaltestdata/ |
| D | dqAnd.decTest | 2 -- dqAnd.decTest -- digitwise logical AND for decQuads --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 dqand001 and 0 0 -> 0
31 dqand002 and 0 1 -> 0
32 dqand003 and 1 0 -> 0
33 dqand004 and 1 1 -> 1
34 dqand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 dqand006 and 0000000000000000000000000000000000 0000000000000000000000000000000000 -> …
[all …]
|
| D | and.decTest | 2 -- and.decTest -- digitwise logical AND --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
29 andx001 and 0 0 -> 0
30 andx002 and 0 1 -> 0
31 andx003 and 1 0 -> 0
32 andx004 and 1 1 -> 1
33 andx005 and 1100 1010 -> 1000
34 andx006 and 1111 10 -> 10
35 andx007 and 1111 1010 -> 1010
[all …]
|
| D | ddAnd.decTest | 2 -- ddAnd.decTest -- digitwise logical AND for decDoubles --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 ddand001 and 0 0 -> 0
31 ddand002 and 0 1 -> 0
32 ddand003 and 1 0 -> 0
33 ddand004 and 1 1 -> 1
34 ddand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 ddand006 and 0000000000000000 0000000000000000 -> 0
[all …]
|
| /external/python/cpython2/Lib/test/decimaltestdata/ |
| D | dqAnd.decTest | 2 -- dqAnd.decTest -- digitwise logical AND for decQuads --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 dqand001 and 0 0 -> 0
31 dqand002 and 0 1 -> 0
32 dqand003 and 1 0 -> 0
33 dqand004 and 1 1 -> 1
34 dqand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 dqand006 and 0000000000000000000000000000000000 0000000000000000000000000000000000 -> …
[all …]
|
| D | and.decTest | 2 -- and.decTest -- digitwise logical AND --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
29 andx001 and 0 0 -> 0
30 andx002 and 0 1 -> 0
31 andx003 and 1 0 -> 0
32 andx004 and 1 1 -> 1
33 andx005 and 1100 1010 -> 1000
34 andx006 and 1111 10 -> 10
35 andx007 and 1111 1010 -> 1010
[all …]
|
| D | ddAnd.decTest | 2 -- ddAnd.decTest -- digitwise logical AND for decDoubles --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 ddand001 and 0 0 -> 0
31 ddand002 and 0 1 -> 0
32 ddand003 and 1 0 -> 0
33 ddand004 and 1 1 -> 1
34 ddand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 ddand006 and 0000000000000000 0000000000000000 -> 0
[all …]
|
| /external/v8/ |
| D | ChangeLog | 3 Performance and stability improvements on all platforms.
8 Performance and stability improvements on all platforms.
13 Performance and stability improvements on all platforms.
18 Performance and stability improvements on all platforms.
23 Performance and stability improvements on all platforms.
28 Performance and stability improvements on all platforms.
33 Performance and stability improvements on all platforms.
38 Performance and stability improvements on all platforms.
43 Performance and stability improvements on all platforms.
48 Performance and stability improvements on all platforms.
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/CorrelatedValuePropagation/ |
| D | crash.ll | 15 %and.us.us = and i16 %conv6.us.us, %and.us.us
66 %a1 = and i1 %a0, %a0
67 %a2 = and i1 %a1, %a1
68 %a3 = and i1 %a2, %a2
69 %a4 = and i1 %a3, %a3
70 %a5 = and i1 %a4, %a4
71 %a6 = and i1 %a5, %a5
72 %a7 = and i1 %a6, %a6
73 %a8 = and i1 %a7, %a7
74 %a9 = and i1 %a8, %a8
[all …]
|
| /external/brotli/tests/testdata/ |
| D | plrabn12.txt | 16 a specific location, and then it took months to convince people
18 the copying and get it to us. Then another month to convert to
21 will see below. The original was, of course, in CAPS only, and
22 so were all the other etexts of the 60's and early 70's. Don't
23 let anyone fool you into thinking any etext with both upper and
25 etexts were also in upper case and were translated or rewritten
29 In the course of our searches for Professor Raben and his etext
32 little information here and there, but even after we received a
34 determining that it was in fact Public Domain and finding Raben
35 to verify this and get his permission. Interested enough, in a
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/ |
| D | and-icmps-same-ops.ll | 4 ; There are 10 * 10 combinations of icmp predicates that can be AND'd together.
14 %and = and i1 %cmp1, %cmp2
15 ret i1 %and
24 %and = and i1 %cmp1, %cmp2
25 ret i1 %and
35 %and = and i1 %cmp1, %cmp2
36 ret i1 %and
45 %and = and i1 %cmp1, %cmp2
46 ret i1 %and
56 %and = and i1 %cmp1, %cmp2
[all …]
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoderCommon.h | 11 // It contains common definitions used by both the disassembler and the table
85 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
96 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
115 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
116 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
117 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
118 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
119 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
120 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
121 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
| D | X86DisassemblerDecoderCommon.h | 11 // It contains common definitions used by both the disassembler and the table
87 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
102 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
123 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
124 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
125 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
126 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
127 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
128 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
129 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
[all …]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | risbg-01.ll | 12 %and = and i32 %shr, 1
13 ret i32 %and
16 ; ...and again with i64.
22 %and = and i64 %shr, 1
23 ret i64 %and
32 %and = and i32 %shr, 12
33 ret i32 %and
36 ; ...and again with i64.
42 %and = and i64 %shr, 12
43 ret i64 %and
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | risbg-04.ll | 12 %and = and i32 %shr, 1
13 ret i32 %and
16 ; ...and again with i64.
22 %and = and i64 %shr, 1
23 ret i64 %and
32 %and = and i32 %shr, 12
33 ret i32 %and
36 ; ...and again with i64.
42 %and = and i64 %shr, 12
43 ret i64 %and
[all …]
|
| D | risbg-01.ll | 12 %and = and i32 %shr, 1
13 ret i32 %and
16 ; ...and again with i64.
22 %and = and i64 %shr, 1
23 ret i64 %and
32 %and = and i32 %shr, 12
33 ret i32 %and
36 ; ...and again with i64.
42 %and = and i64 %shr, 12
43 ret i64 %and
[all …]
|
| D | rnsbg-01.ll | 11 %and = and i32 %a, %orb
12 ret i32 %and
15 ; ...and again with i64.
21 %and = and i64 %a, %orb
22 ret i64 %and
31 %and = and i32 %a, %orb
32 ret i32 %and
35 ; ...and again with i64.
41 %and = and i64 %a, %orb
42 ret i64 %and
[all …]
|
| /external/capstone/arch/X86/ |
| D | X86DisassemblerDecoderCommon.h | 11 * It contains common definitions used by both the disassembler and the table
22 * the decoder and the table generator in a C-friendly manner.
114 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
115 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
116 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
117 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
118 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
119 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
120 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
121 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/SystemZ/ |
| D | scalar-cmp-cmp-log-sel.ll | 9 %and = and i1 %cmp0, %cmp1
10 %sel = select i1 %and, i8 %val5, i8 %val6
16 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
17 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i8 %val5, i8 %val6
24 %and = and i1 %cmp0, %cmp1
25 %sel = select i1 %and, i16 %val5, i16 %val6
31 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
32 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i16 %val5, i16 %val6
39 %and = and i1 %cmp0, %cmp1
40 %sel = select i1 %and, i32 %val5, i32 %val6
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | masked-merge-add.ll | 12 ; And then into:
21 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
23 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
24 ; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
27 %and = and i32 %x, %m
29 %and1 = and i32 %neg, %y
30 %ret = add i32 %and, %and1
36 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]]
38 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[NEG]], [[Y:%.*]]
39 ; CHECK-NEXT: [[RET:%.*]] = or <2 x i32> [[AND]], [[AND1]]
[all …]
|
| D | masked-merge-xor.ll | 12 ; And then into:
21 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
23 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
24 ; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
27 %and = and i32 %x, %m
29 %and1 = and i32 %neg, %y
30 %ret = xor i32 %and, %and1
36 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]]
38 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[NEG]], [[Y:%.*]]
39 ; CHECK-NEXT: [[RET:%.*]] = or <2 x i32> [[AND]], [[AND1]]
[all …]
|
| D | masked-merge-or.ll | 12 ; And then into:
21 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
23 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
24 ; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
27 %and = and i32 %x, %m
29 %and1 = and i32 %neg, %y
30 %ret = or i32 %and, %and1
36 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]]
38 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[NEG]], [[Y:%.*]]
39 ; CHECK-NEXT: [[RET:%.*]] = or <2 x i32> [[AND]], [[AND1]]
[all …]
|
| /external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/duration/testdata/ |
| D | testdata_en.txt | 167 1 hour and 5 minutes
169 1 hour and 10 minutes
171 1 hour and 15 minutes
173 1 hour and 20 minutes
175 1 hour and 25 minutes
177 1 hour and 30 minutes
179 1 hour and 35 minutes
181 1 hour and 40 minutes
183 1 hour and 45 minutes
185 1 hour and 50 minutes
[all …]
|
| /external/icu/android_icu4j/src/main/tests/android/icu/dev/test/duration/testdata/ |
| D | testdata_en.txt | 167 1 hour and 5 minutes
169 1 hour and 10 minutes
171 1 hour and 15 minutes
173 1 hour and 20 minutes
175 1 hour and 25 minutes
177 1 hour and 30 minutes
179 1 hour and 35 minutes
181 1 hour and 40 minutes
183 1 hour and 45 minutes
185 1 hour and 50 minutes
[all …]
|