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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D3dnow-schedule.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+3dnowa | FileC…
5 ; CHECK-LABEL: test_femms:
7 ; CHECK-NEXT: femms # sched: [31:10.33]
8 ; CHECK-NEXT: retq # sched: [1:1.00]
9 call void @llvm.x86.mmx.femms()
12 declare void @llvm.x86.mmx.femms() nounwind readnone
15 ; CHECK-LABEL: test_pavgusb:
17 ; CHECK-NEXT: pavgusb %mm1, %mm0 # sched: [3:1.00]
18 ; CHECK-NEXT: pavgusb (%rdi), %mm0 # sched: [8:1.00]
19 ; CHECK-NEXT: movq %mm0, %rax # sched: [2:1.00]
[all …]
Dstack-folding-3dnow.ll1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+3dnow | FileCheck %s
4 ;CHECK-LABEL: stack_fold_pavgusb
5 ;CHECK: pavgusb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
7 %2 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %a, x86_mmx %b) nounwind readnone
10 declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone
13 ;CHECK-LABEL: stack_fold_pf2id
14 ;CHECK: pf2id {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
16 %2 = call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %a) nounwind readnone
19 declare x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx) nounwind readnone
22 ;CHECK-LABEL: stack_fold_pf2iw
[all …]
Dmmx-intrinsics.ll1 ; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-p…
2 ; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix=X…
3 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check…
4 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix…
6 declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone
9 ; ALL-LABEL: @test1
15 %3 = bitcast <4 x i16> %0 to x86_mmx
16 %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %2, x86_mmx %3) nounwind readnone
23 declare x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx, x86_mmx) nounwind readnone
26 ; ALL-LABEL: @test88
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dfunnel-shift-rot.ll2 ; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
4 declare i8 @llvm.fshl.i8(i8, i8, i8)
5 declare i16 @llvm.fshl.i16(i16, i16, i16)
6 declare i32 @llvm.fshl.i32(i32, i32, i32)
7 declare i64 @llvm.fshl.i64(i64, i64, i64)
8 declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
10 declare i8 @llvm.fshr.i8(i8, i8, i8)
11 declare i16 @llvm.fshr.i16(i16, i16, i16)
12 declare i32 @llvm.fshr.i32(i32, i32, i32)
13 declare i64 @llvm.fshr.i64(i64, i64, i64)
[all …]
Dfunnel-shift.ll2 ; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
4 declare i8 @llvm.fshl.i8(i8, i8, i8)
5 declare i16 @llvm.fshl.i16(i16, i16, i16)
6 declare i32 @llvm.fshl.i32(i32, i32, i32)
7 declare i64 @llvm.fshl.i64(i64, i64, i64)
8 declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
10 declare i8 @llvm.fshr.i8(i8, i8, i8)
11 declare i16 @llvm.fshr.i16(i16, i16, i16)
12 declare i32 @llvm.fshr.i32(i32, i32, i32)
13 declare i64 @llvm.fshr.i64(i64, i64, i64)
[all …]
/external/clang/test/CodeGen/
D3dnow-builtins.c1 …N: %clang_cc1 %s -triple=x86_64-unknown-unknown -target-feature +3dnowa -emit-llvm -o - -Werror | …
2 … RUN: %clang_cc1 %s -triple=x86_64-scei-ps4 -target-feature +3dnowa -emit-llvm -o - -Werror | File…
10 // PS4-LABEL: define i64 @test_m_pavgusb in test_m_pavgusb()
11 // GCC-LABEL: define double @test_m_pavgusb in test_m_pavgusb()
12 // CHECK: @llvm.x86.3dnow.pavgusb in test_m_pavgusb()
17 // PS4-LABEL: define i64 @test_m_pf2id in test_m_pf2id()
18 // GCC-LABEL: define double @test_m_pf2id in test_m_pf2id()
19 // CHECK: @llvm.x86.3dnow.pf2id in test_m_pf2id()
24 // PS4-LABEL: define i64 @test_m_pfacc in test_m_pfacc()
25 // GCC-LABEL: define double @test_m_pfacc in test_m_pfacc()
[all …]
Darm-v8.1a-neon-intrinsics.c1 // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \
2 // RUN: -S -emit-llvm -o - %s \
3 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
5 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
6 // RUN: -target-feature +v8.1a -S -emit-llvm -o - %s \
7 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
9 // REQUIRES: arm-registered-target,aarch64-registered-target
13 // CHECK-LABEL: test_vqrdmlah_s16
15 // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}}) in test_vqrdmlah_s16()
16 // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}}) in test_vqrdmlah_s16()
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dlds-alignment.ll1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA -check-p…
3 @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
4 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
6 @lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8
7 @lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32
9 @lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef
10 @lds.missing.align.1 = internal unnamed_addr addrspace(3) global [7 x i64] undef
12 declare void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(1)* nocapture read…
13 declare void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* nocapture, i8 addrspace(3)* nocapture read…
16 ; HSA-LABEL: {{^}}test_no_round_size_1:
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dlds-alignment.ll1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA -check-p…
3 @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
4 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
6 @lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8
7 @lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32
9 @lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef
10 @lds.missing.align.1 = internal unnamed_addr addrspace(3) global [7 x i64] undef
12 declare void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(1)* nocapture read…
13 declare void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* nocapture, i8 addrspace(3)* nocapture read…
16 ; HSA-LABEL: {{^}}test_no_round_size_1:
[all …]
Dmad-mix-lo.ll1 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -che…
2 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check…
3 ; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -che…
5 ; GCN-LABEL: mixlo_simple:
7 ; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2{{$}}
8 ; GFX9-NEXT: s_setpc_b64
13 %result = call float @llvm.fmuladd.f32(float %src0, float %src1, float %src2)
18 ; GCN-LABEL: {{^}}v_mad_mixlo_f16_f16lo_f16lo_f16lo:
26 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
31 ; GCN-LABEL: {{^}}v_mad_mixlo_f16_f16lo_f16lo_f32:
[all …]
Dllvm.amdgcn.buffer.store.ll1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=VERDE %s
2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
4 ;CHECK-LABEL: {{^}}buffer_store:
5 ;CHECK-NOT: s_waitcnt
6 ;CHECK: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
7 ;CHECK: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 glc
8 ;CHECK: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 slc
11 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
12 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
13 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InferAddressSpaces/AMDGPU/
Dmem-intrinsics.ll1 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
3 ; CHECK-LABEL: @memset_group_to_flat(
4 ; CHECK: call void @llvm.memset.p3i8.i64(i8 addrspace(3)* align 4 %group.ptr, i8 4, i64 32, i1 fals…
5 define amdgpu_kernel void @memset_group_to_flat(i8 addrspace(3)* %group.ptr, i32 %y) #0 {
6 %cast = addrspacecast i8 addrspace(3)* %group.ptr to i8*
7 …call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope…
11 ; CHECK-LABEL: @memset_global_to_flat(
12 ; CHECK: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* align 4 %global.ptr, i8 4, i64 32, i1 fal…
15 …call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope…
19 ; CHECK-LABEL: @memset_group_to_flat_no_md(
[all …]
Dintrinsics.ll1 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
3 ; CHECK-LABEL: @objectsize_group_to_flat_i32(
4 ; CHECK: %val = call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* %group.ptr, i1 true, i1 false)
5 define i32 @objectsize_group_to_flat_i32(i8 addrspace(3)* %group.ptr) #0 {
6 %cast = addrspacecast i8 addrspace(3)* %group.ptr to i8*
7 %val = call i32 @llvm.objectsize.i32.p0i8(i8* %cast, i1 true, i1 false)
11 ; CHECK-LABEL: @objectsize_global_to_flat_i64(
12 ; CHECK: %val = call i64 @llvm.objectsize.i64.p3i8(i8 addrspace(3)* %global.ptr, i1 true, i1 false)
13 define i64 @objectsize_global_to_flat_i64(i8 addrspace(3)* %global.ptr) #0 {
14 %cast = addrspacecast i8 addrspace(3)* %global.ptr to i8*
[all …]
/external/llvm/test/CodeGen/X86/
Dstack-folding-3dnow.ll1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+3dnow | FileCheck %s
4 ;CHECK-LABEL: stack_fold_pavgusb
5 ;CHECK: pavgusb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
7 %2 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %a, x86_mmx %b) nounwind readnone
10 declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone
13 ;CHECK-LABEL: stack_fold_pf2id
14 ;CHECK: pf2id {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
16 %2 = call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %a) nounwind readnone
19 declare x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx) nounwind readnone
22 ;CHECK-LABEL: stack_fold_pf2iw
[all …]
Dmmx-intrinsics.ll1 ; RUN: llc < %s -march=x86 -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-prefix…
2 ; RUN: llc < %s -march=x86 -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix=X86
3 ; RUN: llc < %s -march=x86-64 -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-pre…
4 ; RUN: llc < %s -march=x86-64 -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix=X64
6 declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone
9 ; ALL-LABEL: @test1
15 %3 = bitcast <4 x i16> %0 to x86_mmx
16 %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %2, x86_mmx %3) nounwind readnone
23 declare x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx, x86_mmx) nounwind readnone
26 ; ALL-LABEL: @test88
[all …]
Dvector-shuffle-combining-avx.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefi…
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-pref…
4 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-p…
8 declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8)
9 declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8)
10 declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8)
11 declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8)
13 declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>)
14 declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>)
15 declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll1 ; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
5 ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
6 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
7 ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
8 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
9 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
10 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
11 ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
12 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
13 ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/AMDGPU/
Dfabs.ll1 ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
4 ; CHECK: estimated cost of 0 for {{.*}} call float @llvm.fabs.f32
7 %fabs = call float @llvm.fabs.f32(float %vec) #1
13 ; CHECK: estimated cost of 0 for {{.*}} call <2 x float> @llvm.fabs.v2f32
16 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %vec) #1
22 ; CHECK: estimated cost of 0 for {{.*}} call <3 x float> @llvm.fabs.v3f32
23 define amdgpu_kernel void @fabs_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %va…
24 %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
25 %fabs = call <3 x float> @llvm.fabs.v3f32(<3 x float> %vec) #1
26 store <3 x float> %fabs, <3 x float> addrspace(1)* %out
[all …]
/external/llvm/test/Analysis/CostModel/AMDGPU/
Dfabs.ll1 ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
4 ; CHECK: estimated cost of 0 for {{.*}} call float @llvm.fabs.f32
7 %fabs = call float @llvm.fabs.f32(float %vec) #1
13 ; CHECK: estimated cost of 0 for {{.*}} call <2 x float> @llvm.fabs.v2f32
16 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %vec) #1
22 ; CHECK: estimated cost of 0 for {{.*}} call <3 x float> @llvm.fabs.v3f32
23 define void @fabs_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr) #0 {
24 %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
25 %fabs = call <3 x float> @llvm.fabs.v3f32(<3 x float> %vec) #1
26 store <3 x float> %fabs, <3 x float> addrspace(1)* %out
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dlog-exp-intrinsic.ll2 ; RUN: opt < %s -instsimplify -S | FileCheck %s
4 declare double @llvm.log.f64(double)
5 declare double @llvm.exp.f64(double)
6 declare double @llvm.log2.f64(double)
7 declare double @llvm.exp2.f64(double)
10 ; CHECK-LABEL: @log_reassoc_exp_strict(
11 ; CHECK-NEXT: ret double [[A:%.*]]
13 %1 = call double @llvm.exp.f64(double %a)
14 %2 = call reassoc double @llvm.log.f64(double %1)
19 ; CHECK-LABEL: @log_strict_exp_reassoc(
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dreg-scav-imp-use-dbl-vec.ll1 ; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
7 target triple = "hexagon-unknown--elf"
18 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
21 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
24 declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #1
27 declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1
30 declare <32 x i32> @llvm.hexagon.V6.vlsrw.128B(<32 x i32>, i32) #1
33 declare <32 x i32> @llvm.hexagon.V6.vshufeh.128B(<32 x i32>, <32 x i32>) #1
36 declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #1
39 declare <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32>, i32) #1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dintrinsics-coprocessor.ll1 ; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -show-mc-encoding | FileCheck %s
4 ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
5 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
6 ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
7 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
8 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
9 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
10 ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
11 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
12 ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
[all …]
/external/spirv-llvm/test/SPIRV/transcoding/
DOpMemoryBarrier_cl20.ll1 ; RUN: llvm-as %s -o %t.bc
2 ; RUN: llvm-spirv %t.bc -spirv-text -o %t.txt
3 ; RUN: FileCheck < %t.txt %s --check-prefix=CHECK-SPIRV
4 ; RUN: llvm-spirv %t.bc -o %t.spv
5 ; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
6 ; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
8 ; CHECK-LLVM: call spir_func void @_Z22atomic_work_item_fencejii(i32 2, i32 3, i32 0)
9 ; CHECK-LLVM-NEXT: call spir_func void @_Z22atomic_work_item_fencejii(i32 2, i32 3, i32 1)
10 ; CHECK-LLVM-NEXT: call spir_func void @_Z22atomic_work_item_fencejii(i32 2, i32 3, i32 2)
11 ; CHECK-LLVM-NEXT: call spir_func void @_Z22atomic_work_item_fencejii(i32 2, i32 3, i32 3)
[all …]
/external/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll1 ; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
2 ; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s
6 ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
7 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
8 ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
9 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
10 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
12 ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
13 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
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/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-profdata/
Dmultiple-inputs.test3 RUN: llvm-profdata merge %p/Inputs/foo3-1.proftext %p/Inputs/foo3-2.proftext -o %t
4 RUN: llvm-profdata show %t -all-functions -counts | FileCheck %s --check-prefix=FOO3
5 RUN: llvm-profdata merge %p/Inputs/foo3-2.proftext %p/Inputs/foo3-1.proftext -o %t
6 RUN: llvm-profdata show %t -all-functions -counts | FileCheck %s --check-prefix=FOO3
8 FOO3: Counters: 3
15 RUN: llvm-profdata merge %p/Inputs/empty.proftext %p/Inputs/foo3-1.proftext -o %t
16 RUN: llvm-profdata show %t -all-functions -counts | FileCheck %s --check-prefix=FOO3EMPTY
18 FOO3EMPTY: Counters: 3
20 FOO3EMPTY: Block counts: [2, 3]
23 FOO3EMPTY: Maximum internal block count: 3
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