| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 32 const MipsRegisterBankInfo &RBI);
44 const MipsRegisterBankInfo &RBI; member in __anonca8e812d0111::MipsInstructionSelector
63 const MipsRegisterBankInfo &RBI) in MipsInstructionSelector() argument
65 TRI(*STI.getRegisterInfo()), RBI(RBI), in MipsInstructionSelector()
78 const RegisterBankInfo &RBI) { in selectCopy() argument
85 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
102 return selectCopy(I, TII, MRI, TRI, RBI); in select()
132 const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID(); in select()
161 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in select()
163 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in select()
[all …]
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| D | MipsSubtarget.cpp | 203 auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo()); in MipsSubtarget() local
204 RegBankInfo.reset(RBI); in MipsSubtarget()
206 *static_cast<const MipsTargetMachine *>(&TM), *this, *RBI)); in MipsSubtarget()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anon30372f3b0111::ARMInstructionSelector
95 const ARMRegisterBankInfo &RBI) { in createARMInstructionSelector() argument
96 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
108 const ARMRegisterBankInfo &RBI) in ARMInstructionSelector() argument
110 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), in ARMInstructionSelector()
123 const RegisterBankInfo &RBI) { in guessRegClass() argument
124 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
148 const RegisterBankInfo &RBI) { in selectCopy() argument
153 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
[all …]
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| D | ARMSubtarget.cpp | 112 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo()); in ARMSubtarget() local
114 // FIXME: At this point, we can't rely on Subtarget having RBI. in ARMSubtarget()
115 // It's awkward to mix passing RBI and the Subtarget; should we pass in ARMSubtarget()
118 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI)); in ARMSubtarget()
120 RegBankInfo.reset(RBI); in ARMSubtarget()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 50 const AArch64RegisterBankInfo &RBI);
106 const AArch64RegisterBankInfo &RBI; member in __anon0efbf18d0111::AArch64InstructionSelector
127 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
129 TRI(*STI.getRegisterInfo()), RBI(RBI), in AArch64InstructionSelector()
143 const RegisterBankInfo &RBI, in getRegClassForTypeOnBank() argument
177 const AArch64RegisterBankInfo &RBI, in unsupportedBinOp() argument
203 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
344 const RegisterBankInfo &RBI) { in selectCopy() argument
352 const RegisterBank &RegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
354 MRI.getType(SrcReg), RegBank, RBI, /* GetAllRegSet */ true); in selectCopy()
[all …]
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| D | AArch64Subtarget.cpp | 162 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo()); in AArch64Subtarget() local
164 // FIXME: At this point, we can't rely on Subtarget having RBI. in AArch64Subtarget()
165 // It's awkward to mix passing RBI and the Subtarget; should we pass in AArch64Subtarget()
168 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI)); in AArch64Subtarget()
170 RegBankInfo.reset(RBI); in AArch64Subtarget()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 62 const X86RegisterBankInfo &RBI);
135 const X86RegisterBankInfo &RBI; member in __anonacd089870111::X86InstructionSelector
154 const X86RegisterBankInfo &RBI) in X86InstructionSelector() argument
156 TRI(*STI.getRegisterInfo()), RBI(RBI), in X86InstructionSelector()
199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
234 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
238 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
239 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
274 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) && in selectCopy()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 46 const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, in AMDGPUInstructionSelector() argument
49 TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
77 RBI.constrainGenericRegister(MO.getReg(), *RC, MRI); in selectCOPY()
126 unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI); in selectG_ADD()
158 RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI); in selectG_ADD()
177 RBI.constrainGenericRegister(MO.getReg(), *RC, MRI); in selectG_IMPLICIT_DEF()
257 return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI); in selectG_INTRINSIC_W_SIDE_EFFECTS()
274 return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI); in selectG_INTRINSIC_W_SIDE_EFFECTS()
285 unsigned StoreSize = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI); in selectG_STORE()
316 bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI); in selectG_STORE()
[all …]
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| D | AMDGPUInstructionSelector.h | 46 const AMDGPURegisterBankInfo &RBI,
95 const AMDGPURegisterBankInfo &RBI; variable
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 33 const RegisterBankInfo &RBI, in constrainRegToClass() argument
36 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) { in constrainRegToClass()
50 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, in constrainOperandRegClass() argument
85 return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass); in constrainOperandRegClass()
91 const RegisterBankInfo &RBI) { in constrainSelectedInstRegOperands() argument
121 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
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| D | InstructionSelector.cpp | 40 const RegisterBankInfo &RBI) const { in constrainOperandRegToRegClass()
46 constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC); in constrainOperandRegToRegClass()
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| D | RegBankSelect.cpp | 84 RBI = MF.getSubtarget().getRegBankInfo(); in init()
85 assert(RBI && "Cannot work without RegisterBankInfo"); in init()
122 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
195 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
226 unsigned Cost = RBI->copyCost(*DesiredRegBrank, *CurRegBank, in getRepairCost()
227 RBI->getSizeInBits(MO.getReg(), *MRI, *TRI)); in getRepairCost()
565 RBI->applyMapping(OpdMapper); in applyMapping()
577 BestMapping = &RBI->getInstrMapping(MI); in assignInstr()
584 RBI->getInstrPossibleMappings(MI); in assignInstr()
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| /external/snakeyaml/src/test/resources/specification/ |
| D | example2_9.yaml | 5 rbi:
6 # 1998 rbi ranking
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| D | example2_2.yaml | 3 rbi: 147 # Runs Batted In
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| D | example2_10.yaml | 6 rbi:
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| /external/snakeyaml/src/test/resources/pyyaml/ |
| D | spec-02-09.data | 5 rbi:
6 # 1998 rbi ranking
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| D | spec-02-02.data | 3 rbi: 147 # Runs Batted In
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| D | spec-02-10.data | 6 rbi:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/YAMLParser/ |
| D | spec-02-09.test | 7 rbi:
8 # 1998 rbi ranking
|
| /external/llvm/test/YAMLParser/ |
| D | spec-02-09.test | 7 rbi:
8 # 1998 rbi ranking
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 46 const RegisterBankInfo &RBI,
61 const RegisterBankInfo &RBI,
77 const RegisterBankInfo &RBI);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| D | MergedLoadStoreMotion.cpp | 292 for (BasicBlock::reverse_iterator RBI = Pred0->rbegin(), RBE = Pred0->rend(); in mergeStores() local
293 RBI != RBE;) { in mergeStores()
295 Instruction *I = &*RBI; in mergeStores()
296 ++RBI; in mergeStores()
315 RBI = Pred0->rbegin(); in mergeStores()
317 LLVM_DEBUG(dbgs() << "Search again\n"; Instruction *I = &*RBI; I->dump()); in mergeStores()
|
| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegBankSelect.cpp | 48 : MachineFunctionPass(ID), RBI(nullptr), MRI(nullptr), TRI(nullptr), in RegBankSelect()
59 RBI = MF.getSubtarget().getRegBankInfo(); in init()
60 assert(RBI && "Cannot work without RegisterBankInfo"); in init()
93 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
161 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
193 RBI->copyCost(*DesiredRegBrank, *CurRegBank, in getRepairCost()
506 RBI->applyMapping(OpdMapper); in applyMapping()
516 BestMapping = RBI->getInstrMapping(MI); in assignInstr()
523 RBI->getInstrPossibleMappings(MI); in assignInstr()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | MergedLoadStoreMotion.cpp | 490 for (BasicBlock::reverse_iterator RBI = Pred0->rbegin(), RBE = Pred0->rend(); in mergeStores() local
491 RBI != RBE;) { in mergeStores()
493 Instruction *I = &*RBI; in mergeStores()
494 ++RBI; in mergeStores()
513 RBI = Pred0->rbegin(); in mergeStores()
515 DEBUG(dbgs() << "Search again\n"; Instruction *I = &*RBI; I->dump()); in mergeStores()
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| /external/snakeyaml/src/test/java/org/yaml/snakeyaml/ |
| D | Chapter2_1Test.java | 51 assertEquals("Expect 147 to be an Integer", Integer.class, map.get("rbi").getClass()); in testExample_2_2()
52 assertEquals(new Integer(147), map.get("rbi")); in testExample_2_2()
|