1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29 /* 30 * Authors: 31 * Kevin E. Martin <martin@xfree86.org> 32 * Rickard E. Faith <faith@valinux.com> 33 * Alan Hourihane <alanh@fairlite.demon.co.uk> 34 * 35 * References: 36 * 37 * !!!! FIXME !!!! 38 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 39 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 40 * 1999. 41 * 42 * !!!! FIXME !!!! 43 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 44 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 45 * 46 */ 47 48 /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h 49 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT 50 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ 51 52 #ifndef _RADEON_REG_H_ 53 #define _RADEON_REG_H_ 54 55 /* Registers for 2D/Video/Overlay */ 56 #define RADEON_ADAPTER_ID 0x0f2c /* PCI */ 57 #define RADEON_AGP_BASE 0x0170 58 #define RADEON_AGP_CNTL 0x0174 59 # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) 60 # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) 61 # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) 62 # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) 63 # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) 64 # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) 65 # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) 66 # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) 67 #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ 68 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ 69 # define RADEON_AGP_ENABLE (1<<8) 70 #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ 71 #define RADEON_AGP_STATUS 0x0f5c /* PCI */ 72 # define RADEON_AGP_1X_MODE 0x01 73 # define RADEON_AGP_2X_MODE 0x02 74 # define RADEON_AGP_4X_MODE 0x04 75 # define RADEON_AGP_FW_MODE 0x10 76 # define RADEON_AGP_MODE_MASK 0x17 77 #define RADEON_ATTRDR 0x03c1 /* VGA */ 78 #define RADEON_ATTRDW 0x03c0 /* VGA */ 79 #define RADEON_ATTRX 0x03c0 /* VGA */ 80 #define RADEON_AUX_SC_CNTL 0x1660 81 # define RADEON_AUX1_SC_EN (1 << 0) 82 # define RADEON_AUX1_SC_MODE_OR (0 << 1) 83 # define RADEON_AUX1_SC_MODE_NAND (1 << 1) 84 # define RADEON_AUX2_SC_EN (1 << 2) 85 # define RADEON_AUX2_SC_MODE_OR (0 << 3) 86 # define RADEON_AUX2_SC_MODE_NAND (1 << 3) 87 # define RADEON_AUX3_SC_EN (1 << 4) 88 # define RADEON_AUX3_SC_MODE_OR (0 << 5) 89 # define RADEON_AUX3_SC_MODE_NAND (1 << 5) 90 #define RADEON_AUX1_SC_BOTTOM 0x1670 91 #define RADEON_AUX1_SC_LEFT 0x1664 92 #define RADEON_AUX1_SC_RIGHT 0x1668 93 #define RADEON_AUX1_SC_TOP 0x166c 94 #define RADEON_AUX2_SC_BOTTOM 0x1680 95 #define RADEON_AUX2_SC_LEFT 0x1674 96 #define RADEON_AUX2_SC_RIGHT 0x1678 97 #define RADEON_AUX2_SC_TOP 0x167c 98 #define RADEON_AUX3_SC_BOTTOM 0x1690 99 #define RADEON_AUX3_SC_LEFT 0x1684 100 #define RADEON_AUX3_SC_RIGHT 0x1688 101 #define RADEON_AUX3_SC_TOP 0x168c 102 #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 103 #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc 104 105 #define RADEON_BASE_CODE 0x0f0b 106 #define RADEON_BIOS_0_SCRATCH 0x0010 107 #define RADEON_BIOS_1_SCRATCH 0x0014 108 #define RADEON_BIOS_2_SCRATCH 0x0018 109 #define RADEON_BIOS_3_SCRATCH 0x001c 110 #define RADEON_BIOS_4_SCRATCH 0x0020 111 #define RADEON_BIOS_5_SCRATCH 0x0024 112 #define RADEON_BIOS_6_SCRATCH 0x0028 113 #define RADEON_BIOS_7_SCRATCH 0x002c 114 #define RADEON_BIOS_ROM 0x0f30 /* PCI */ 115 #define RADEON_BIST 0x0f0f /* PCI */ 116 #define RADEON_BRUSH_DATA0 0x1480 117 #define RADEON_BRUSH_DATA1 0x1484 118 #define RADEON_BRUSH_DATA10 0x14a8 119 #define RADEON_BRUSH_DATA11 0x14ac 120 #define RADEON_BRUSH_DATA12 0x14b0 121 #define RADEON_BRUSH_DATA13 0x14b4 122 #define RADEON_BRUSH_DATA14 0x14b8 123 #define RADEON_BRUSH_DATA15 0x14bc 124 #define RADEON_BRUSH_DATA16 0x14c0 125 #define RADEON_BRUSH_DATA17 0x14c4 126 #define RADEON_BRUSH_DATA18 0x14c8 127 #define RADEON_BRUSH_DATA19 0x14cc 128 #define RADEON_BRUSH_DATA2 0x1488 129 #define RADEON_BRUSH_DATA20 0x14d0 130 #define RADEON_BRUSH_DATA21 0x14d4 131 #define RADEON_BRUSH_DATA22 0x14d8 132 #define RADEON_BRUSH_DATA23 0x14dc 133 #define RADEON_BRUSH_DATA24 0x14e0 134 #define RADEON_BRUSH_DATA25 0x14e4 135 #define RADEON_BRUSH_DATA26 0x14e8 136 #define RADEON_BRUSH_DATA27 0x14ec 137 #define RADEON_BRUSH_DATA28 0x14f0 138 #define RADEON_BRUSH_DATA29 0x14f4 139 #define RADEON_BRUSH_DATA3 0x148c 140 #define RADEON_BRUSH_DATA30 0x14f8 141 #define RADEON_BRUSH_DATA31 0x14fc 142 #define RADEON_BRUSH_DATA32 0x1500 143 #define RADEON_BRUSH_DATA33 0x1504 144 #define RADEON_BRUSH_DATA34 0x1508 145 #define RADEON_BRUSH_DATA35 0x150c 146 #define RADEON_BRUSH_DATA36 0x1510 147 #define RADEON_BRUSH_DATA37 0x1514 148 #define RADEON_BRUSH_DATA38 0x1518 149 #define RADEON_BRUSH_DATA39 0x151c 150 #define RADEON_BRUSH_DATA4 0x1490 151 #define RADEON_BRUSH_DATA40 0x1520 152 #define RADEON_BRUSH_DATA41 0x1524 153 #define RADEON_BRUSH_DATA42 0x1528 154 #define RADEON_BRUSH_DATA43 0x152c 155 #define RADEON_BRUSH_DATA44 0x1530 156 #define RADEON_BRUSH_DATA45 0x1534 157 #define RADEON_BRUSH_DATA46 0x1538 158 #define RADEON_BRUSH_DATA47 0x153c 159 #define RADEON_BRUSH_DATA48 0x1540 160 #define RADEON_BRUSH_DATA49 0x1544 161 #define RADEON_BRUSH_DATA5 0x1494 162 #define RADEON_BRUSH_DATA50 0x1548 163 #define RADEON_BRUSH_DATA51 0x154c 164 #define RADEON_BRUSH_DATA52 0x1550 165 #define RADEON_BRUSH_DATA53 0x1554 166 #define RADEON_BRUSH_DATA54 0x1558 167 #define RADEON_BRUSH_DATA55 0x155c 168 #define RADEON_BRUSH_DATA56 0x1560 169 #define RADEON_BRUSH_DATA57 0x1564 170 #define RADEON_BRUSH_DATA58 0x1568 171 #define RADEON_BRUSH_DATA59 0x156c 172 #define RADEON_BRUSH_DATA6 0x1498 173 #define RADEON_BRUSH_DATA60 0x1570 174 #define RADEON_BRUSH_DATA61 0x1574 175 #define RADEON_BRUSH_DATA62 0x1578 176 #define RADEON_BRUSH_DATA63 0x157c 177 #define RADEON_BRUSH_DATA7 0x149c 178 #define RADEON_BRUSH_DATA8 0x14a0 179 #define RADEON_BRUSH_DATA9 0x14a4 180 #define RADEON_BRUSH_SCALE 0x1470 181 #define RADEON_BRUSH_Y_X 0x1474 182 #define RADEON_BUS_CNTL 0x0030 183 # define RADEON_BUS_MASTER_DIS (1 << 6) 184 # define RADEON_BUS_RD_DISCARD_EN (1 << 24) 185 # define RADEON_BUS_RD_ABORT_EN (1 << 25) 186 # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) 187 # define RADEON_BUS_WRT_BURST (1 << 29) 188 # define RADEON_BUS_READ_BURST (1 << 30) 189 #define RADEON_BUS_CNTL1 0x0034 190 # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) 191 192 #define RADEON_CACHE_CNTL 0x1724 193 #define RADEON_CACHE_LINE 0x0f0c /* PCI */ 194 #define RADEON_CAP0_TRIG_CNTL 0x0950 /* ? */ 195 #define RADEON_CAP1_TRIG_CNTL 0x09c0 /* ? */ 196 #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ 197 #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ 198 #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ 199 #define RADEON_CLOCK_CNTL_DATA 0x000c 200 #define RADEON_CLOCK_CNTL_INDEX 0x0008 201 # define RADEON_PLL_WR_EN (1 << 7) 202 # define RADEON_PLL_DIV_SEL (3 << 8) 203 # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) 204 #define RADEON_CLR_CMP_CLR_3D 0x1a24 205 #define RADEON_CLR_CMP_CLR_DST 0x15c8 206 #define RADEON_CLR_CMP_CLR_SRC 0x15c4 207 #define RADEON_CLR_CMP_CNTL 0x15c0 208 # define RADEON_SRC_CMP_EQ_COLOR (4 << 0) 209 # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) 210 # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) 211 #define RADEON_CLR_CMP_MASK 0x15cc 212 # define RADEON_CLR_CMP_MSK 0xffffffff 213 #define RADEON_CLR_CMP_MASK_3D 0x1A28 214 #define RADEON_COMMAND 0x0f04 /* PCI */ 215 #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c 216 #define RADEON_CONFIG_APER_0_BASE 0x0100 217 #define RADEON_CONFIG_APER_1_BASE 0x0104 218 #define RADEON_CONFIG_APER_SIZE 0x0108 219 #define RADEON_CONFIG_BONDS 0x00e8 220 #define RADEON_CONFIG_CNTL 0x00e0 221 # define RADEON_CFG_ATI_REV_A11 (0 << 16) 222 # define RADEON_CFG_ATI_REV_A12 (1 << 16) 223 # define RADEON_CFG_ATI_REV_A13 (2 << 16) 224 # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) 225 #define RADEON_CONFIG_MEMSIZE 0x00f8 226 #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 227 #define RADEON_CONFIG_REG_1_BASE 0x010c 228 #define RADEON_CONFIG_REG_APER_SIZE 0x0110 229 #define RADEON_CONFIG_XSTRAP 0x00e4 230 #define RADEON_CONSTANT_COLOR_C 0x1d34 231 # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff 232 # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff 233 # define RADEON_CONSTANT_COLOR_ZERO 0x00000000 234 #define RADEON_CRC_CMDFIFO_ADDR 0x0740 235 #define RADEON_CRC_CMDFIFO_DOUT 0x0744 236 #define RADEON_GRPH_BUFFER_CNTL 0x02f0 237 # define RADEON_GRPH_START_REQ_MASK (0x7f) 238 # define RADEON_GRPH_START_REQ_SHIFT 0 239 # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) 240 # define RADEON_GRPH_STOP_REQ_SHIFT 8 241 # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) 242 # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 243 # define RADEON_GRPH_CRITICAL_CNTL (1<<28) 244 # define RADEON_GRPH_BUFFER_SIZE (1<<29) 245 # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) 246 # define RADEON_GRPH_STOP_CNTL (1<<31) 247 #define RADEON_GRPH2_BUFFER_CNTL 0x03f0 248 # define RADEON_GRPH2_START_REQ_MASK (0x7f) 249 # define RADEON_GRPH2_START_REQ_SHIFT 0 250 # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) 251 # define RADEON_GRPH2_STOP_REQ_SHIFT 8 252 # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) 253 # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 254 # define RADEON_GRPH2_CRITICAL_CNTL (1<<28) 255 # define RADEON_GRPH2_BUFFER_SIZE (1<<29) 256 # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) 257 # define RADEON_GRPH2_STOP_CNTL (1<<31) 258 #define RADEON_CRTC_CRNT_FRAME 0x0214 259 #define RADEON_CRTC_EXT_CNTL 0x0054 260 # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) 261 # define RADEON_VGA_ATI_LINEAR (1 << 3) 262 # define RADEON_XCRT_CNT_EN (1 << 6) 263 # define RADEON_CRTC_HSYNC_DIS (1 << 8) 264 # define RADEON_CRTC_VSYNC_DIS (1 << 9) 265 # define RADEON_CRTC_DISPLAY_DIS (1 << 10) 266 # define RADEON_CRTC_SYNC_TRISTAT (1 << 11) 267 # define RADEON_CRTC_CRT_ON (1 << 15) 268 #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 269 # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) 270 # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) 271 # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) 272 #define RADEON_CRTC_GEN_CNTL 0x0050 273 # define RADEON_CRTC_DBL_SCAN_EN (1 << 0) 274 # define RADEON_CRTC_INTERLACE_EN (1 << 1) 275 # define RADEON_CRTC_CSYNC_EN (1 << 4) 276 # define RADEON_CRTC_CUR_EN (1 << 16) 277 # define RADEON_CRTC_CUR_MODE_MASK (7 << 17) 278 # define RADEON_CRTC_ICON_EN (1 << 20) 279 # define RADEON_CRTC_EXT_DISP_EN (1 << 24) 280 # define RADEON_CRTC_EN (1 << 25) 281 # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) 282 #define RADEON_CRTC2_GEN_CNTL 0x03f8 283 # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) 284 # define RADEON_CRTC2_INTERLACE_EN (1 << 1) 285 # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) 286 # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) 287 # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) 288 # define RADEON_CRTC2_CRT2_ON (1 << 7) 289 # define RADEON_CRTC2_ICON_EN (1 << 15) 290 # define RADEON_CRTC2_CUR_EN (1 << 16) 291 # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) 292 # define RADEON_CRTC2_DISP_DIS (1 << 23) 293 # define RADEON_CRTC2_EN (1 << 25) 294 # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) 295 # define RADEON_CRTC2_CSYNC_EN (1 << 27) 296 # define RADEON_CRTC2_HSYNC_DIS (1 << 28) 297 # define RADEON_CRTC2_VSYNC_DIS (1 << 29) 298 #define RADEON_CRTC_MORE_CNTL 0x27c 299 # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) 300 # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) 301 #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 302 #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 303 # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) 304 # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) 305 # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 306 # define RADEON_CRTC_H_SYNC_WID (0x3f << 16) 307 # define RADEON_CRTC_H_SYNC_WID_SHIFT 16 308 # define RADEON_CRTC_H_SYNC_POL (1 << 23) 309 #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 310 # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) 311 # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) 312 # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 313 # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) 314 # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 315 # define RADEON_CRTC2_H_SYNC_POL (1 << 23) 316 #define RADEON_CRTC_H_TOTAL_DISP 0x0200 317 # define RADEON_CRTC_H_TOTAL (0x03ff << 0) 318 # define RADEON_CRTC_H_TOTAL_SHIFT 0 319 # define RADEON_CRTC_H_DISP (0x01ff << 16) 320 # define RADEON_CRTC_H_DISP_SHIFT 16 321 #define RADEON_CRTC2_H_TOTAL_DISP 0x0300 322 # define RADEON_CRTC2_H_TOTAL (0x03ff << 0) 323 # define RADEON_CRTC2_H_TOTAL_SHIFT 0 324 # define RADEON_CRTC2_H_DISP (0x01ff << 16) 325 # define RADEON_CRTC2_H_DISP_SHIFT 16 326 #define RADEON_CRTC_OFFSET 0x0224 327 #define RADEON_CRTC2_OFFSET 0x0324 328 #define RADEON_CRTC_OFFSET_CNTL 0x0228 329 # define RADEON_CRTC_TILE_EN (1 << 15) 330 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 331 # define RADEON_CRTC2_TILE_EN (1 << 15) 332 #define RADEON_CRTC_PITCH 0x022c 333 #define RADEON_CRTC2_PITCH 0x032c 334 #define RADEON_CRTC_STATUS 0x005c 335 # define RADEON_CRTC_VBLANK_SAVE (1 << 1) 336 # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) 337 #define RADEON_CRTC2_STATUS 0x03fc 338 # define RADEON_CRTC2_VBLANK_SAVE (1 << 1) 339 # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) 340 #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c 341 # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) 342 # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 343 # define RADEON_CRTC_V_SYNC_WID (0x1f << 16) 344 # define RADEON_CRTC_V_SYNC_WID_SHIFT 16 345 # define RADEON_CRTC_V_SYNC_POL (1 << 23) 346 #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c 347 # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) 348 # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 349 # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) 350 # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 351 # define RADEON_CRTC2_V_SYNC_POL (1 << 23) 352 #define RADEON_CRTC_V_TOTAL_DISP 0x0208 353 # define RADEON_CRTC_V_TOTAL (0x07ff << 0) 354 # define RADEON_CRTC_V_TOTAL_SHIFT 0 355 # define RADEON_CRTC_V_DISP (0x07ff << 16) 356 # define RADEON_CRTC_V_DISP_SHIFT 16 357 #define RADEON_CRTC2_V_TOTAL_DISP 0x0308 358 # define RADEON_CRTC2_V_TOTAL (0x07ff << 0) 359 # define RADEON_CRTC2_V_TOTAL_SHIFT 0 360 # define RADEON_CRTC2_V_DISP (0x07ff << 16) 361 # define RADEON_CRTC2_V_DISP_SHIFT 16 362 #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 363 # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) 364 #define RADEON_CRTC2_CRNT_FRAME 0x0314 365 #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 366 #define RADEON_CRTC2_STATUS 0x03fc 367 #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 368 #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ 369 #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ 370 #define RADEON_CUR_CLR0 0x026c 371 #define RADEON_CUR_CLR1 0x0270 372 #define RADEON_CUR_HORZ_VERT_OFF 0x0268 373 #define RADEON_CUR_HORZ_VERT_POSN 0x0264 374 #define RADEON_CUR_OFFSET 0x0260 375 # define RADEON_CUR_LOCK (1 << 31) 376 #define RADEON_CUR2_CLR0 0x036c 377 #define RADEON_CUR2_CLR1 0x0370 378 #define RADEON_CUR2_HORZ_VERT_OFF 0x0368 379 #define RADEON_CUR2_HORZ_VERT_POSN 0x0364 380 #define RADEON_CUR2_OFFSET 0x0360 381 # define RADEON_CUR2_LOCK (1 << 31) 382 383 #define RADEON_DAC_CNTL 0x0058 384 # define RADEON_DAC_RANGE_CNTL (3 << 0) 385 # define RADEON_DAC_RANGE_CNTL_MASK 0x03 386 # define RADEON_DAC_BLANKING (1 << 2) 387 # define RADEON_DAC_CMP_EN (1 << 3) 388 # define RADEON_DAC_CMP_OUTPUT (1 << 7) 389 # define RADEON_DAC_8BIT_EN (1 << 8) 390 # define RADEON_DAC_VGA_ADR_EN (1 << 13) 391 # define RADEON_DAC_PDWN (1 << 15) 392 # define RADEON_DAC_MASK_ALL (0xff << 24) 393 #define RADEON_DAC_CNTL2 0x007c 394 # define RADEON_DAC2_DAC_CLK_SEL (1 << 0) 395 # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) 396 # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) 397 #define RADEON_DAC_EXT_CNTL 0x0280 398 # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) 399 # define RADEON_DAC_FORCE_DATA_EN (1 << 5) 400 # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) 401 # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 402 # define RADEON_DAC_FORCE_DATA_SHIFT 8 403 #define RADEON_TV_DAC_CNTL 0x088c 404 # define RADEON_TV_DAC_STD_MASK 0x0300 405 # define RADEON_TV_DAC_RDACPD (1 << 24) 406 # define RADEON_TV_DAC_GDACPD (1 << 25) 407 # define RADEON_TV_DAC_BDACPD (1 << 26) 408 #define RADEON_DISP_HW_DEBUG 0x0d14 409 # define RADEON_CRT2_DISP1_SEL (1 << 5) 410 #define RADEON_DISP_OUTPUT_CNTL 0x0d64 411 # define RADEON_DISP_DAC_SOURCE_MASK 0x03 412 # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c 413 # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 414 # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 415 #define RADEON_DAC_CRC_SIG 0x02cc 416 #define RADEON_DAC_DATA 0x03c9 /* VGA */ 417 #define RADEON_DAC_MASK 0x03c6 /* VGA */ 418 #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ 419 #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ 420 #define RADEON_DDA_CONFIG 0x02e0 421 #define RADEON_DDA_ON_OFF 0x02e4 422 #define RADEON_DEFAULT_OFFSET 0x16e0 423 #define RADEON_DEFAULT_PITCH 0x16e4 424 #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 425 # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 426 # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 427 #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 428 #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 429 #define RADEON_DEVICE_ID 0x0f02 /* PCI */ 430 #define RADEON_DISP_MISC_CNTL 0x0d00 431 # define RADEON_SOFT_RESET_GRPH_PP (1 << 0) 432 #define RADEON_DISP_MERGE_CNTL 0x0d60 433 # define RADEON_DISP_ALPHA_MODE_MASK 0x03 434 # define RADEON_DISP_ALPHA_MODE_KEY 0 435 # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 436 # define RADEON_DISP_ALPHA_MODE_GLOBAL 2 437 # define RADEON_DISP_RGB_OFFSET_EN (1<<8) 438 # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) 439 # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) 440 # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) 441 #define RADEON_DISP2_MERGE_CNTL 0x0d68 442 # define RADEON_DISP2_RGB_OFFSET_EN (1<<8) 443 #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 444 #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 445 #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 446 #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c 447 #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 448 #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 449 #define RADEON_DP_BRUSH_BKGD_CLR 0x1478 450 #define RADEON_DP_BRUSH_FRGD_CLR 0x147c 451 #define RADEON_DP_CNTL 0x16c0 452 # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) 453 # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) 454 #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 455 # define RADEON_DST_Y_MAJOR (1 << 2) 456 # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) 457 # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) 458 #define RADEON_DP_DATATYPE 0x16c4 459 # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) 460 #define RADEON_DP_GUI_MASTER_CNTL 0x146c 461 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 462 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 463 # define RADEON_GMC_SRC_CLIPPING (1 << 2) 464 # define RADEON_GMC_DST_CLIPPING (1 << 3) 465 # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) 466 # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) 467 # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) 468 # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) 469 # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) 470 # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) 471 # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) 472 # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) 473 # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) 474 # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) 475 # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) 476 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 477 # define RADEON_GMC_BRUSH_NONE (15 << 4) 478 # define RADEON_GMC_DST_8BPP_CI (2 << 8) 479 # define RADEON_GMC_DST_15BPP (3 << 8) 480 # define RADEON_GMC_DST_16BPP (4 << 8) 481 # define RADEON_GMC_DST_24BPP (5 << 8) 482 # define RADEON_GMC_DST_32BPP (6 << 8) 483 # define RADEON_GMC_DST_8BPP_RGB (7 << 8) 484 # define RADEON_GMC_DST_Y8 (8 << 8) 485 # define RADEON_GMC_DST_RGB8 (9 << 8) 486 # define RADEON_GMC_DST_VYUY (11 << 8) 487 # define RADEON_GMC_DST_YVYU (12 << 8) 488 # define RADEON_GMC_DST_AYUV444 (14 << 8) 489 # define RADEON_GMC_DST_ARGB4444 (15 << 8) 490 # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) 491 # define RADEON_GMC_DST_DATATYPE_SHIFT 8 492 # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) 493 # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) 494 # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) 495 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 496 # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) 497 # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) 498 # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) 499 # define RADEON_GMC_CONVERSION_TEMP (1 << 15) 500 # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) 501 # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) 502 # define RADEON_GMC_ROP3_MASK (0xff << 16) 503 # define RADEON_DP_SRC_SOURCE_MASK (7 << 24) 504 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 505 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 506 # define RADEON_GMC_3D_FCN_EN (1 << 27) 507 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 508 # define RADEON_GMC_AUX_CLIP_DIS (1 << 29) 509 # define RADEON_GMC_WR_MSK_DIS (1 << 30) 510 # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) 511 # define RADEON_ROP3_ZERO 0x00000000 512 # define RADEON_ROP3_DSa 0x00880000 513 # define RADEON_ROP3_SDna 0x00440000 514 # define RADEON_ROP3_S 0x00cc0000 515 # define RADEON_ROP3_DSna 0x00220000 516 # define RADEON_ROP3_D 0x00aa0000 517 # define RADEON_ROP3_DSx 0x00660000 518 # define RADEON_ROP3_DSo 0x00ee0000 519 # define RADEON_ROP3_DSon 0x00110000 520 # define RADEON_ROP3_DSxn 0x00990000 521 # define RADEON_ROP3_Dn 0x00550000 522 # define RADEON_ROP3_SDno 0x00dd0000 523 # define RADEON_ROP3_Sn 0x00330000 524 # define RADEON_ROP3_DSno 0x00bb0000 525 # define RADEON_ROP3_DSan 0x00770000 526 # define RADEON_ROP3_ONE 0x00ff0000 527 # define RADEON_ROP3_DPa 0x00a00000 528 # define RADEON_ROP3_PDna 0x00500000 529 # define RADEON_ROP3_P 0x00f00000 530 # define RADEON_ROP3_DPna 0x000a0000 531 # define RADEON_ROP3_D 0x00aa0000 532 # define RADEON_ROP3_DPx 0x005a0000 533 # define RADEON_ROP3_DPo 0x00fa0000 534 # define RADEON_ROP3_DPon 0x00050000 535 # define RADEON_ROP3_PDxn 0x00a50000 536 # define RADEON_ROP3_PDno 0x00f50000 537 # define RADEON_ROP3_Pn 0x000f0000 538 # define RADEON_ROP3_DPno 0x00af0000 539 # define RADEON_ROP3_DPan 0x005f0000 540 #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 541 #define RADEON_DP_MIX 0x16c8 542 #define RADEON_DP_SRC_BKGD_CLR 0x15dc 543 #define RADEON_DP_SRC_FRGD_CLR 0x15d8 544 #define RADEON_DP_WRITE_MASK 0x16cc 545 #define RADEON_DST_BRES_DEC 0x1630 546 #define RADEON_DST_BRES_ERR 0x1628 547 #define RADEON_DST_BRES_INC 0x162c 548 #define RADEON_DST_BRES_LNTH 0x1634 549 #define RADEON_DST_BRES_LNTH_SUB 0x1638 550 #define RADEON_DST_HEIGHT 0x1410 551 #define RADEON_DST_HEIGHT_WIDTH 0x143c 552 #define RADEON_DST_HEIGHT_WIDTH_8 0x158c 553 #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 554 #define RADEON_DST_HEIGHT_Y 0x15a0 555 #define RADEON_DST_LINE_START 0x1600 556 #define RADEON_DST_LINE_END 0x1604 557 #define RADEON_DST_LINE_PATCOUNT 0x1608 558 # define RADEON_BRES_CNTL_SHIFT 8 559 #define RADEON_DST_OFFSET 0x1404 560 #define RADEON_DST_PITCH 0x1408 561 #define RADEON_DST_PITCH_OFFSET 0x142c 562 #define RADEON_DST_PITCH_OFFSET_C 0x1c80 563 # define RADEON_PITCH_SHIFT 21 564 # define RADEON_DST_TILE_LINEAR (0 << 30) 565 # define RADEON_DST_TILE_MACRO (1 << 30) 566 # define RADEON_DST_TILE_MICRO (2 << 30) 567 # define RADEON_DST_TILE_BOTH (3 << 30) 568 #define RADEON_DST_WIDTH 0x140c 569 #define RADEON_DST_WIDTH_HEIGHT 0x1598 570 #define RADEON_DST_WIDTH_X 0x1588 571 #define RADEON_DST_WIDTH_X_INCY 0x159c 572 #define RADEON_DST_X 0x141c 573 #define RADEON_DST_X_SUB 0x15a4 574 #define RADEON_DST_X_Y 0x1594 575 #define RADEON_DST_Y 0x1420 576 #define RADEON_DST_Y_SUB 0x15a8 577 #define RADEON_DST_Y_X 0x1438 578 579 #define RADEON_FCP_CNTL 0x0910 580 # define RADEON_FCP0_SRC_PCICLK 0 581 # define RADEON_FCP0_SRC_PCLK 1 582 # define RADEON_FCP0_SRC_PCLKb 2 583 # define RADEON_FCP0_SRC_HREF 3 584 # define RADEON_FCP0_SRC_GND 4 585 # define RADEON_FCP0_SRC_HREFb 5 586 #define RADEON_FLUSH_1 0x1704 587 #define RADEON_FLUSH_2 0x1708 588 #define RADEON_FLUSH_3 0x170c 589 #define RADEON_FLUSH_4 0x1710 590 #define RADEON_FLUSH_5 0x1714 591 #define RADEON_FLUSH_6 0x1718 592 #define RADEON_FLUSH_7 0x171c 593 #define RADEON_FOG_3D_TABLE_START 0x1810 594 #define RADEON_FOG_3D_TABLE_END 0x1814 595 #define RADEON_FOG_3D_TABLE_DENSITY 0x181c 596 #define RADEON_FOG_TABLE_INDEX 0x1a14 597 #define RADEON_FOG_TABLE_DATA 0x1a18 598 #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 599 #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 600 #define RADEON_FP_CRTC2_H_TOTAL_DISP 0x0350 601 #define RADEON_FP_CRTC2_V_TOTAL_DISP 0x0354 602 # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff 603 # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 604 # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff 605 # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 606 # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 607 # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 608 # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff 609 # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 610 # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 611 # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 612 # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 613 # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 614 # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 615 # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 616 # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 617 # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 618 #define RADEON_FP_GEN_CNTL 0x0284 619 # define RADEON_FP_FPON (1 << 0) 620 # define RADEON_FP_TMDS_EN (1 << 2) 621 # define RADEON_FP_PANEL_FORMAT (1 << 3) 622 # define RADEON_FP_EN_TMDS (1 << 7) 623 # define RADEON_FP_DETECT_SENSE (1 << 8) 624 # define RADEON_FP_SEL_CRTC2 (1 << 13) 625 # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) 626 # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 627 # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) 628 # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) 629 # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) 630 # define RADEON_FP_DFP_SYNC_SEL (1 << 21) 631 # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) 632 # define RADEON_FP_CRT_SYNC_SEL (1 << 23) 633 # define RADEON_FP_USE_SHADOW_EN (1 << 24) 634 # define RADEON_FP_CRT_SYNC_ALT (1 << 26) 635 #define RADEON_FP2_GEN_CNTL 0x0288 636 # define RADEON_FP2_BLANK_EN (1 << 1) 637 # define RADEON_FP2_ON (1 << 2) 638 # define RADEON_FP2_PANEL_FORMAT (1 << 3) 639 # define RADEON_FP2_SOURCE_SEL_MASK (3 << 10) 640 # define RADEON_FP2_SOURCE_SEL_CRTC2 (1 << 10) 641 # define RADEON_FP2_SRC_SEL_MASK (3 << 13) 642 # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) 643 # define RADEON_FP2_FP_POL (1 << 16) 644 # define RADEON_FP2_LP_POL (1 << 17) 645 # define RADEON_FP2_SCK_POL (1 << 18) 646 # define RADEON_FP2_LCD_CNTL_MASK (7 << 19) 647 # define RADEON_FP2_PAD_FLOP_EN (1 << 22) 648 # define RADEON_FP2_CRC_EN (1 << 23) 649 # define RADEON_FP2_CRC_READ_EN (1 << 24) 650 # define RADEON_FP2_DV0_EN (1 << 25) 651 # define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26) 652 #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 653 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 654 #define RADEON_FP_HORZ_STRETCH 0x028c 655 #define RADEON_FP_HORZ2_STRETCH 0x038c 656 # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff 657 # define RADEON_HORZ_STRETCH_RATIO_MAX 4096 658 # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) 659 # define RADEON_HORZ_PANEL_SHIFT 16 660 # define RADEON_HORZ_STRETCH_PIXREP (0 << 25) 661 # define RADEON_HORZ_STRETCH_BLEND (1 << 26) 662 # define RADEON_HORZ_STRETCH_ENABLE (1 << 25) 663 # define RADEON_HORZ_AUTO_RATIO (1 << 27) 664 # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) 665 # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) 666 #define RADEON_FP_V_SYNC_STRT_WID 0x02c8 667 #define RADEON_FP_VERT_STRETCH 0x0290 668 #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 669 #define RADEON_FP_VERT2_STRETCH 0x0390 670 # define RADEON_VERT_PANEL_SIZE (0xfff << 12) 671 # define RADEON_VERT_PANEL_SHIFT 12 672 # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff 673 # define RADEON_VERT_STRETCH_RATIO_SHIFT 0 674 # define RADEON_VERT_STRETCH_RATIO_MAX 4096 675 # define RADEON_VERT_STRETCH_ENABLE (1 << 25) 676 # define RADEON_VERT_STRETCH_LINEREP (0 << 26) 677 # define RADEON_VERT_STRETCH_BLEND (1 << 26) 678 # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) 679 # define RADEON_VERT_STRETCH_RESERVED 0xf1000000 680 681 #define RADEON_GEN_INT_CNTL 0x0040 682 #define RADEON_GEN_INT_STATUS 0x0044 683 # define RADEON_VSYNC_INT_AK (1 << 2) 684 # define RADEON_VSYNC_INT (1 << 2) 685 # define RADEON_VSYNC2_INT_AK (1 << 6) 686 # define RADEON_VSYNC2_INT (1 << 6) 687 #define RADEON_GENENB 0x03c3 /* VGA */ 688 #define RADEON_GENFC_RD 0x03ca /* VGA */ 689 #define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ 690 #define RADEON_GENMO_RD 0x03cc /* VGA */ 691 #define RADEON_GENMO_WT 0x03c2 /* VGA */ 692 #define RADEON_GENS0 0x03c2 /* VGA */ 693 #define RADEON_GENS1 0x03da /* VGA, 0x03ba */ 694 #define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ 695 #define RADEON_GPIO_MONIDB 0x006c 696 #define RADEON_GPIO_CRT2_DDC 0x006c 697 #define RADEON_GPIO_DVI_DDC 0x0064 698 #define RADEON_GPIO_VGA_DDC 0x0060 699 # define RADEON_GPIO_A_0 (1 << 0) 700 # define RADEON_GPIO_A_1 (1 << 1) 701 # define RADEON_GPIO_Y_0 (1 << 8) 702 # define RADEON_GPIO_Y_1 (1 << 9) 703 # define RADEON_GPIO_Y_SHIFT_0 8 704 # define RADEON_GPIO_Y_SHIFT_1 9 705 # define RADEON_GPIO_EN_0 (1 << 16) 706 # define RADEON_GPIO_EN_1 (1 << 17) 707 # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ 708 # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ 709 #define RADEON_GRPH8_DATA 0x03cf /* VGA */ 710 #define RADEON_GRPH8_IDX 0x03ce /* VGA */ 711 #define RADEON_GUI_SCRATCH_REG0 0x15e0 712 #define RADEON_GUI_SCRATCH_REG1 0x15e4 713 #define RADEON_GUI_SCRATCH_REG2 0x15e8 714 #define RADEON_GUI_SCRATCH_REG3 0x15ec 715 #define RADEON_GUI_SCRATCH_REG4 0x15f0 716 #define RADEON_GUI_SCRATCH_REG5 0x15f4 717 718 #define RADEON_HEADER 0x0f0e /* PCI */ 719 #define RADEON_HOST_DATA0 0x17c0 720 #define RADEON_HOST_DATA1 0x17c4 721 #define RADEON_HOST_DATA2 0x17c8 722 #define RADEON_HOST_DATA3 0x17cc 723 #define RADEON_HOST_DATA4 0x17d0 724 #define RADEON_HOST_DATA5 0x17d4 725 #define RADEON_HOST_DATA6 0x17d8 726 #define RADEON_HOST_DATA7 0x17dc 727 #define RADEON_HOST_DATA_LAST 0x17e0 728 #define RADEON_HOST_PATH_CNTL 0x0130 729 # define RADEON_HDP_SOFT_RESET (1 << 26) 730 #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ 731 #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ 732 733 #define RADEON_I2C_CNTL_1 0x0094 /* ? */ 734 #define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ 735 #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ 736 #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ 737 #define RADEON_IO_BASE 0x0f14 /* PCI */ 738 739 #define RADEON_LATENCY 0x0f0d /* PCI */ 740 #define RADEON_LEAD_BRES_DEC 0x1608 741 #define RADEON_LEAD_BRES_LNTH 0x161c 742 #define RADEON_LEAD_BRES_LNTH_SUB 0x1624 743 #define RADEON_LVDS_GEN_CNTL 0x02d0 744 # define RADEON_LVDS_ON (1 << 0) 745 # define RADEON_LVDS_DISPLAY_DIS (1 << 1) 746 # define RADEON_LVDS_PANEL_TYPE (1 << 2) 747 # define RADEON_LVDS_PANEL_FORMAT (1 << 3) 748 # define RADEON_LVDS_EN (1 << 7) 749 # define RADEON_LVDS_DIGON (1 << 18) 750 # define RADEON_LVDS_BLON (1 << 19) 751 # define RADEON_LVDS_SEL_CRTC2 (1 << 23) 752 #define RADEON_LVDS_PLL_CNTL 0x02d4 753 # define RADEON_HSYNC_DELAY_SHIFT 28 754 # define RADEON_HSYNC_DELAY_MASK (0xf << 28) 755 756 #define RADEON_MAX_LATENCY 0x0f3f /* PCI */ 757 #define RADEON_MC_AGP_LOCATION 0x014c 758 #define RADEON_MC_FB_LOCATION 0x0148 759 #define RADEON_DISPLAY_BASE_ADDR 0x23c 760 #define RADEON_DISPLAY2_BASE_ADDR 0x33c 761 #define RADEON_OV0_BASE_ADDR 0x43c 762 #define RADEON_NB_TOM 0x15c 763 #define RADEON_MCLK_CNTL 0x0012 /* PLL */ 764 # define RADEON_FORCEON_MCLKA (1 << 16) 765 # define RADEON_FORCEON_MCLKB (1 << 17) 766 # define RADEON_FORCEON_YCLKA (1 << 18) 767 # define RADEON_FORCEON_YCLKB (1 << 19) 768 # define RADEON_FORCEON_MC (1 << 20) 769 # define RADEON_FORCEON_AIC (1 << 21) 770 #define RADEON_MDGPIO_A_REG 0x01ac 771 #define RADEON_MDGPIO_EN_REG 0x01b0 772 #define RADEON_MDGPIO_MASK 0x0198 773 #define RADEON_MDGPIO_Y_REG 0x01b4 774 #define RADEON_MEM_ADDR_CONFIG 0x0148 775 #define RADEON_MEM_BASE 0x0f10 /* PCI */ 776 #define RADEON_MEM_CNTL 0x0140 777 # define RADEON_MEM_NUM_CHANNELS_MASK 0x01 778 # define RADEON_MEM_USE_B_CH_ONLY (1<<1) 779 # define RV100_HALF_MODE (1<<3) 780 #define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ 781 #define RADEON_MEM_INIT_LAT_TIMER 0x0154 782 #define RADEON_MEM_INTF_CNTL 0x014c 783 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 784 #define RADEON_MEM_STR_CNTL 0x0150 785 #define RADEON_MEM_VGA_RP_SEL 0x003c 786 #define RADEON_MEM_VGA_WP_SEL 0x0038 787 #define RADEON_MIN_GRANT 0x0f3e /* PCI */ 788 #define RADEON_MM_DATA 0x0004 789 #define RADEON_MM_INDEX 0x0000 790 #define RADEON_MPLL_CNTL 0x000e /* PLL */ 791 #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ 792 #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ 793 794 #define RADEON_N_VIF_COUNT 0x0248 795 796 #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 797 #define RADEON_OV0_COLOUR_CNTL 0x04E0 798 #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 799 #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 800 # define RADEON_EXCL_HORZ_START_MASK 0x000000ff 801 # define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 802 # define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 803 # define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 804 #define RADEON_OV0_EXCLUSIVE_VERT 0x040C 805 # define RADEON_EXCL_VERT_START_MASK 0x000003ff 806 # define RADEON_EXCL_VERT_END_MASK 0x03ff0000 807 #define RADEON_OV0_FILTER_CNTL 0x04A0 808 #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 809 #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 810 #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 811 #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC 812 #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 813 #define RADEON_OV0_GAMMA_000_00F 0x0d40 814 #define RADEON_OV0_GAMMA_010_01F 0x0d44 815 #define RADEON_OV0_GAMMA_020_03F 0x0d48 816 #define RADEON_OV0_GAMMA_040_07F 0x0d4c 817 #define RADEON_OV0_GAMMA_080_0BF 0x0e00 818 #define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 819 #define RADEON_OV0_GAMMA_100_13F 0x0e08 820 #define RADEON_OV0_GAMMA_140_17F 0x0e0c 821 #define RADEON_OV0_GAMMA_180_1BF 0x0e10 822 #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 823 #define RADEON_OV0_GAMMA_200_23F 0x0e18 824 #define RADEON_OV0_GAMMA_240_27F 0x0e1c 825 #define RADEON_OV0_GAMMA_280_2BF 0x0e20 826 #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 827 #define RADEON_OV0_GAMMA_300_33F 0x0e28 828 #define RADEON_OV0_GAMMA_340_37F 0x0e2c 829 #define RADEON_OV0_GAMMA_380_3BF 0x0d50 830 #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 831 #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC 832 #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 833 #define RADEON_OV0_H_INC 0x0480 834 #define RADEON_OV0_KEY_CNTL 0x04F4 835 # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L 836 # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L 837 # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L 838 # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L 839 # define RADEON_VIDEO_KEY_FN_NE 0x00000003L 840 # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L 841 # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L 842 # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L 843 # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L 844 # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L 845 # define RADEON_CMP_MIX_MASK 0x00000100L 846 # define RADEON_CMP_MIX_OR 0x00000000L 847 # define RADEON_CMP_MIX_AND 0x00000100L 848 #define RADEON_OV0_LIN_TRANS_A 0x0d20 849 #define RADEON_OV0_LIN_TRANS_B 0x0d24 850 #define RADEON_OV0_LIN_TRANS_C 0x0d28 851 #define RADEON_OV0_LIN_TRANS_D 0x0d2c 852 #define RADEON_OV0_LIN_TRANS_E 0x0d30 853 #define RADEON_OV0_LIN_TRANS_F 0x0d34 854 #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 855 # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL 856 # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L 857 #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 858 #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 859 # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L 860 # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L 861 #define RADEON_OV0_P1_X_START_END 0x0494 862 #define RADEON_OV0_P2_X_START_END 0x0498 863 #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 864 # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL 865 # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L 866 #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C 867 #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C 868 #define RADEON_OV0_P3_X_START_END 0x049C 869 #define RADEON_OV0_REG_LOAD_CNTL 0x0410 870 # define RADEON_REG_LD_CTL_LOCK 0x00000001L 871 # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L 872 # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L 873 # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L 874 #define RADEON_OV0_SCALE_CNTL 0x0420 875 # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L 876 # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L 877 # define RADEON_SCALER_SIGNED_UV 0x00000010L 878 # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L 879 # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L 880 # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L 881 # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L 882 # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L 883 # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L 884 # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L 885 # define RADEON_SCALER_SOURCE_15BPP 0x00000300L 886 # define RADEON_SCALER_SOURCE_16BPP 0x00000400L 887 # define RADEON_SCALER_SOURCE_32BPP 0x00000600L 888 # define RADEON_SCALER_SOURCE_YUV9 0x00000900L 889 # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L 890 # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L 891 # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L 892 # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L 893 # define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L 894 # define RADEON_SCALER_SMART_SWITCH 0x00008000L 895 # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L 896 # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L 897 # define RADEON_SCALER_DIS_LIMIT 0x08000000L 898 # define RADEON_SCALER_INT_EMU 0x20000000L 899 # define RADEON_SCALER_ENABLE 0x40000000L 900 # define RADEON_SCALER_SOFT_RESET 0x80000000L 901 # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L 902 #define RADEON_OV0_STEP_BY 0x0484 903 #define RADEON_OV0_TEST 0x04F8 904 #define RADEON_OV0_V_INC 0x0424 905 #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 906 #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 907 #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 908 # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L 909 # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L 910 # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L 911 # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L 912 #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 913 # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L 914 # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L 915 # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L 916 # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L 917 #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 918 # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L 919 # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L 920 # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L 921 # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L 922 #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C 923 #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 924 #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 925 #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 926 #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 927 #define RADEON_OV0_Y_X_START 0x0400 928 #define RADEON_OV0_Y_X_END 0x0404 929 #define RADEON_OV1_Y_X_START 0x0600 930 #define RADEON_OV1_Y_X_END 0x0604 931 #define RADEON_OVR_CLR 0x0230 932 #define RADEON_OVR_WID_LEFT_RIGHT 0x0234 933 #define RADEON_OVR_WID_TOP_BOTTOM 0x0238 934 935 #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ 936 # define RADEON_P2PLL_RESET (1 << 0) 937 # define RADEON_P2PLL_SLEEP (1 << 1) 938 # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) 939 # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 940 # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) 941 #define RADEON_P2PLL_DIV_0 0x002c 942 # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff 943 # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 944 #define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ 945 # define RADEON_P2PLL_REF_DIV_MASK 0x03ff 946 # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 947 # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 948 #define RADEON_PALETTE_DATA 0x00b4 949 #define RADEON_PALETTE_30_DATA 0x00b8 950 #define RADEON_PALETTE_INDEX 0x00b0 951 #define RADEON_PCI_GART_PAGE 0x017c 952 #define RADEON_PIXCLKS_CNTL 0x002d 953 # define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 954 # define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 955 # define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 956 # define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 957 # define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 958 # define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) 959 # define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) 960 # define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) 961 # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) 962 # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) 963 #define RADEON_PLANE_3D_MASK_C 0x1d44 964 #define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ 965 #define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ 966 #define RADEON_PMI_DATA 0x0f63 /* PCI */ 967 #define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ 968 #define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ 969 #define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ 970 #define RADEON_PMI_REGISTER 0x0f5c /* PCI */ 971 #define RADEON_PPLL_CNTL 0x0002 /* PLL */ 972 # define RADEON_PPLL_RESET (1 << 0) 973 # define RADEON_PPLL_SLEEP (1 << 1) 974 # define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) 975 # define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 976 # define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) 977 #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ 978 #define RADEON_PPLL_DIV_1 0x0005 /* PLL */ 979 #define RADEON_PPLL_DIV_2 0x0006 /* PLL */ 980 #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ 981 # define RADEON_PPLL_FB3_DIV_MASK 0x07ff 982 # define RADEON_PPLL_POST3_DIV_MASK 0x00070000 983 #define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ 984 # define RADEON_PPLL_REF_DIV_MASK 0x03ff 985 # define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 986 # define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 987 #define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ 988 989 #define RADEON_RBBM_GUICNTL 0x172c 990 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 991 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 992 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 993 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 994 #define RADEON_RBBM_SOFT_RESET 0x00f0 995 # define RADEON_SOFT_RESET_CP (1 << 0) 996 # define RADEON_SOFT_RESET_HI (1 << 1) 997 # define RADEON_SOFT_RESET_SE (1 << 2) 998 # define RADEON_SOFT_RESET_RE (1 << 3) 999 # define RADEON_SOFT_RESET_PP (1 << 4) 1000 # define RADEON_SOFT_RESET_E2 (1 << 5) 1001 # define RADEON_SOFT_RESET_RB (1 << 6) 1002 # define RADEON_SOFT_RESET_HDP (1 << 7) 1003 #define RADEON_RBBM_STATUS 0x0e40 1004 # define RADEON_RBBM_FIFOCNT_MASK 0x007f 1005 # define RADEON_RBBM_ACTIVE (1 << 31) 1006 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 1007 # define RADEON_RB2D_DC_FLUSH (3 << 0) 1008 # define RADEON_RB2D_DC_FREE (3 << 2) 1009 # define RADEON_RB2D_DC_FLUSH_ALL 0xf 1010 # define RADEON_RB2D_DC_BUSY (1 << 31) 1011 #define RADEON_RB2D_DSTCACHE_MODE 0x3428 1012 #define RADEON_REG_BASE 0x0f18 /* PCI */ 1013 #define RADEON_REGPROG_INF 0x0f09 /* PCI */ 1014 #define RADEON_REVISION_ID 0x0f08 /* PCI */ 1015 1016 #define RADEON_SC_BOTTOM 0x164c 1017 #define RADEON_SC_BOTTOM_RIGHT 0x16f0 1018 #define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c 1019 #define RADEON_SC_LEFT 0x1640 1020 #define RADEON_SC_RIGHT 0x1644 1021 #define RADEON_SC_TOP 0x1648 1022 #define RADEON_SC_TOP_LEFT 0x16ec 1023 #define RADEON_SC_TOP_LEFT_C 0x1c88 1024 # define RADEON_SC_SIGN_MASK_LO 0x8000 1025 # define RADEON_SC_SIGN_MASK_HI 0x80000000 1026 #define RADEON_SCLK_CNTL 0x000d /* PLL */ 1027 # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 1028 # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 1029 # define RADEON_SCLK_FORCEON_MASK 0xffff8000 1030 #define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ 1031 # define RADEON_SCLK_MORE_FORCEON 0x0700 1032 #define RADEON_SDRAM_MODE_REG 0x0158 1033 #define RADEON_SEQ8_DATA 0x03c5 /* VGA */ 1034 #define RADEON_SEQ8_IDX 0x03c4 /* VGA */ 1035 #define RADEON_SNAPSHOT_F_COUNT 0x0244 1036 #define RADEON_SNAPSHOT_VH_COUNTS 0x0240 1037 #define RADEON_SNAPSHOT_VIF_COUNT 0x024c 1038 #define RADEON_SRC_OFFSET 0x15ac 1039 #define RADEON_SRC_PITCH 0x15b0 1040 #define RADEON_SRC_PITCH_OFFSET 0x1428 1041 #define RADEON_SRC_SC_BOTTOM 0x165c 1042 #define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 1043 #define RADEON_SRC_SC_RIGHT 0x1654 1044 #define RADEON_SRC_X 0x1414 1045 #define RADEON_SRC_X_Y 0x1590 1046 #define RADEON_SRC_Y 0x1418 1047 #define RADEON_SRC_Y_X 0x1434 1048 #define RADEON_STATUS 0x0f06 /* PCI */ 1049 #define RADEON_SUBPIC_CNTL 0x0540 /* ? */ 1050 #define RADEON_SUB_CLASS 0x0f0a /* PCI */ 1051 #define RADEON_SURFACE_CNTL 0x0b00 1052 # define RADEON_SURF_TRANSLATION_DIS (1 << 8) 1053 # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) 1054 # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) 1055 #define RADEON_SURFACE0_INFO 0x0b0c 1056 # define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) 1057 # define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) 1058 # define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) 1059 # define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) 1060 # define R200_SURF_TILE_NONE (0 << 16) 1061 # define R200_SURF_TILE_COLOR_MACRO (1 << 16) 1062 # define R200_SURF_TILE_COLOR_MICRO (2 << 16) 1063 # define R200_SURF_TILE_COLOR_BOTH (3 << 16) 1064 # define R200_SURF_TILE_DEPTH_32BPP (4 << 16) 1065 # define R200_SURF_TILE_DEPTH_16BPP (5 << 16) 1066 # define RADEON_SURF_AP0_SWP_16BPP (1 << 20) 1067 # define RADEON_SURF_AP0_SWP_32BPP (1 << 21) 1068 # define RADEON_SURF_AP1_SWP_16BPP (1 << 22) 1069 # define RADEON_SURF_AP1_SWP_32BPP (1 << 23) 1070 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 1071 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 1072 #define RADEON_SURFACE1_INFO 0x0b1c 1073 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 1074 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 1075 #define RADEON_SURFACE2_INFO 0x0b2c 1076 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 1077 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 1078 #define RADEON_SURFACE3_INFO 0x0b3c 1079 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 1080 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1081 #define RADEON_SURFACE4_INFO 0x0b4c 1082 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1083 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1084 #define RADEON_SURFACE5_INFO 0x0b5c 1085 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1086 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1087 #define RADEON_SURFACE6_INFO 0x0b6c 1088 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1089 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1090 #define RADEON_SURFACE7_INFO 0x0b7c 1091 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1092 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1093 #define RADEON_SW_SEMAPHORE 0x013c 1094 1095 #define RADEON_TEST_DEBUG_CNTL 0x0120 1096 #define RADEON_TEST_DEBUG_MUX 0x0124 1097 #define RADEON_TEST_DEBUG_OUT 0x012c 1098 #define RADEON_TMDS_PLL_CNTL 0x02a8 1099 #define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 1100 # define RADEON_TMDS_TRANSMITTER_PLLEN 1 1101 # define RADEON_TMDS_TRANSMITTER_PLLRST 2 1102 #define RADEON_TRAIL_BRES_DEC 0x1614 1103 #define RADEON_TRAIL_BRES_ERR 0x160c 1104 #define RADEON_TRAIL_BRES_INC 0x1610 1105 #define RADEON_TRAIL_X 0x1618 1106 #define RADEON_TRAIL_X_SUB 0x1620 1107 1108 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ 1109 # define RADEON_VCLK_SRC_SEL_MASK 0x03 1110 # define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 1111 # define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 1112 # define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 1113 # define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 1114 # define RADEON_PIXCLK_ALWAYS_ONb (1<<6) 1115 # define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) 1116 1117 #define RADEON_VENDOR_ID 0x0f00 /* PCI */ 1118 #define RADEON_VGA_DDA_CONFIG 0x02e8 1119 #define RADEON_VGA_DDA_ON_OFF 0x02ec 1120 #define RADEON_VID_BUFFER_CONTROL 0x0900 1121 #define RADEON_VIDEOMUX_CNTL 0x0190 1122 #define RADEON_VIPH_CONTROL 0x0c40 /* ? */ 1123 1124 #define RADEON_WAIT_UNTIL 0x1720 1125 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1126 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1127 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1128 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1129 1130 #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ 1131 #define RADEON_XCLK_CNTL 0x000d /* PLL */ 1132 #define RADEON_XDLL_CNTL 0x000c /* PLL */ 1133 #define RADEON_XPLL_CNTL 0x000b /* PLL */ 1134 1135 1136 1137 /* Registers for 3D/TCL */ 1138 #define RADEON_PP_BORDER_COLOR_0 0x1d40 1139 #define RADEON_PP_BORDER_COLOR_1 0x1d44 1140 #define RADEON_PP_BORDER_COLOR_2 0x1d48 1141 #define RADEON_PP_CNTL 0x1c38 1142 # define RADEON_STIPPLE_ENABLE (1 << 0) 1143 # define RADEON_SCISSOR_ENABLE (1 << 1) 1144 # define RADEON_PATTERN_ENABLE (1 << 2) 1145 # define RADEON_SHADOW_ENABLE (1 << 3) 1146 # define RADEON_TEX_ENABLE_MASK (0xf << 4) 1147 # define RADEON_TEX_0_ENABLE (1 << 4) 1148 # define RADEON_TEX_1_ENABLE (1 << 5) 1149 # define RADEON_TEX_2_ENABLE (1 << 6) 1150 # define RADEON_TEX_3_ENABLE (1 << 7) 1151 # define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) 1152 # define RADEON_TEX_BLEND_0_ENABLE (1 << 12) 1153 # define RADEON_TEX_BLEND_1_ENABLE (1 << 13) 1154 # define RADEON_TEX_BLEND_2_ENABLE (1 << 14) 1155 # define RADEON_TEX_BLEND_3_ENABLE (1 << 15) 1156 # define RADEON_PLANAR_YUV_ENABLE (1 << 20) 1157 # define RADEON_SPECULAR_ENABLE (1 << 21) 1158 # define RADEON_FOG_ENABLE (1 << 22) 1159 # define RADEON_ALPHA_TEST_ENABLE (1 << 23) 1160 # define RADEON_ANTI_ALIAS_NONE (0 << 24) 1161 # define RADEON_ANTI_ALIAS_LINE (1 << 24) 1162 # define RADEON_ANTI_ALIAS_POLY (2 << 24) 1163 # define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) 1164 # define RADEON_BUMP_MAP_ENABLE (1 << 26) 1165 # define RADEON_BUMPED_MAP_T0 (0 << 27) 1166 # define RADEON_BUMPED_MAP_T1 (1 << 27) 1167 # define RADEON_BUMPED_MAP_T2 (2 << 27) 1168 # define RADEON_TEX_3D_ENABLE_0 (1 << 29) 1169 # define RADEON_TEX_3D_ENABLE_1 (1 << 30) 1170 # define RADEON_MC_ENABLE (1 << 31) 1171 #define RADEON_PP_FOG_COLOR 0x1c18 1172 # define RADEON_FOG_COLOR_MASK 0x00ffffff 1173 # define RADEON_FOG_VERTEX (0 << 24) 1174 # define RADEON_FOG_TABLE (1 << 24) 1175 # define RADEON_FOG_USE_DEPTH (0 << 25) 1176 # define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) 1177 # define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) 1178 #define RADEON_PP_LUM_MATRIX 0x1d00 1179 #define RADEON_PP_MISC 0x1c14 1180 # define RADEON_REF_ALPHA_MASK 0x000000ff 1181 # define RADEON_ALPHA_TEST_FAIL (0 << 8) 1182 # define RADEON_ALPHA_TEST_LESS (1 << 8) 1183 # define RADEON_ALPHA_TEST_LEQUAL (2 << 8) 1184 # define RADEON_ALPHA_TEST_EQUAL (3 << 8) 1185 # define RADEON_ALPHA_TEST_GEQUAL (4 << 8) 1186 # define RADEON_ALPHA_TEST_GREATER (5 << 8) 1187 # define RADEON_ALPHA_TEST_NEQUAL (6 << 8) 1188 # define RADEON_ALPHA_TEST_PASS (7 << 8) 1189 # define RADEON_ALPHA_TEST_OP_MASK (7 << 8) 1190 # define RADEON_CHROMA_FUNC_FAIL (0 << 16) 1191 # define RADEON_CHROMA_FUNC_PASS (1 << 16) 1192 # define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) 1193 # define RADEON_CHROMA_FUNC_EQUAL (3 << 16) 1194 # define RADEON_CHROMA_KEY_NEAREST (0 << 18) 1195 # define RADEON_CHROMA_KEY_ZERO (1 << 18) 1196 # define RADEON_SHADOW_ID_AUTO_INC (1 << 20) 1197 # define RADEON_SHADOW_FUNC_EQUAL (0 << 21) 1198 # define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) 1199 # define RADEON_SHADOW_PASS_1 (0 << 22) 1200 # define RADEON_SHADOW_PASS_2 (1 << 22) 1201 # define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) 1202 # define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) 1203 #define RADEON_PP_ROT_MATRIX_0 0x1d58 1204 #define RADEON_PP_ROT_MATRIX_1 0x1d5c 1205 #define RADEON_PP_TXFILTER_0 0x1c54 1206 #define RADEON_PP_TXFILTER_1 0x1c6c 1207 #define RADEON_PP_TXFILTER_2 0x1c84 1208 # define RADEON_MAG_FILTER_NEAREST (0 << 0) 1209 # define RADEON_MAG_FILTER_LINEAR (1 << 0) 1210 # define RADEON_MAG_FILTER_MASK (1 << 0) 1211 # define RADEON_MIN_FILTER_NEAREST (0 << 1) 1212 # define RADEON_MIN_FILTER_LINEAR (1 << 1) 1213 # define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) 1214 # define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) 1215 # define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) 1216 # define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) 1217 # define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) 1218 # define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) 1219 # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) 1220 # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) 1221 # define RADEON_MIN_FILTER_MASK (15 << 1) 1222 # define RADEON_MAX_ANISO_1_TO_1 (0 << 5) 1223 # define RADEON_MAX_ANISO_2_TO_1 (1 << 5) 1224 # define RADEON_MAX_ANISO_4_TO_1 (2 << 5) 1225 # define RADEON_MAX_ANISO_8_TO_1 (3 << 5) 1226 # define RADEON_MAX_ANISO_16_TO_1 (4 << 5) 1227 # define RADEON_MAX_ANISO_MASK (7 << 5) 1228 # define RADEON_LOD_BIAS_MASK (0xff << 8) 1229 # define RADEON_LOD_BIAS_SHIFT 8 1230 # define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) 1231 # define RADEON_MAX_MIP_LEVEL_SHIFT 16 1232 # define RADEON_YUV_TO_RGB (1 << 20) 1233 # define RADEON_YUV_TEMPERATURE_COOL (0 << 21) 1234 # define RADEON_YUV_TEMPERATURE_HOT (1 << 21) 1235 # define RADEON_YUV_TEMPERATURE_MASK (1 << 21) 1236 # define RADEON_WRAPEN_S (1 << 22) 1237 # define RADEON_CLAMP_S_WRAP (0 << 23) 1238 # define RADEON_CLAMP_S_MIRROR (1 << 23) 1239 # define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) 1240 # define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) 1241 # define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) 1242 # define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) 1243 # define RADEON_CLAMP_S_CLAMP_GL (6 << 23) 1244 # define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) 1245 # define RADEON_CLAMP_S_MASK (7 << 23) 1246 # define RADEON_WRAPEN_T (1 << 26) 1247 # define RADEON_CLAMP_T_WRAP (0 << 27) 1248 # define RADEON_CLAMP_T_MIRROR (1 << 27) 1249 # define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) 1250 # define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) 1251 # define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) 1252 # define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) 1253 # define RADEON_CLAMP_T_CLAMP_GL (6 << 27) 1254 # define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) 1255 # define RADEON_CLAMP_T_MASK (7 << 27) 1256 # define RADEON_BORDER_MODE_OGL (0 << 31) 1257 # define RADEON_BORDER_MODE_D3D (1 << 31) 1258 #define RADEON_PP_TXFORMAT_0 0x1c58 1259 #define RADEON_PP_TXFORMAT_1 0x1c70 1260 #define RADEON_PP_TXFORMAT_2 0x1c88 1261 # define RADEON_TXFORMAT_I8 (0 << 0) 1262 # define RADEON_TXFORMAT_AI88 (1 << 0) 1263 # define RADEON_TXFORMAT_RGB332 (2 << 0) 1264 # define RADEON_TXFORMAT_ARGB1555 (3 << 0) 1265 # define RADEON_TXFORMAT_RGB565 (4 << 0) 1266 # define RADEON_TXFORMAT_ARGB4444 (5 << 0) 1267 # define RADEON_TXFORMAT_ARGB8888 (6 << 0) 1268 # define RADEON_TXFORMAT_RGBA8888 (7 << 0) 1269 # define RADEON_TXFORMAT_Y8 (8 << 0) 1270 # define RADEON_TXFORMAT_VYUY422 (10 << 0) 1271 # define RADEON_TXFORMAT_YVYU422 (11 << 0) 1272 # define RADEON_TXFORMAT_DXT1 (12 << 0) 1273 # define RADEON_TXFORMAT_DXT23 (14 << 0) 1274 # define RADEON_TXFORMAT_DXT45 (15 << 0) 1275 # define RADEON_TXFORMAT_SHADOW16 (16 << 0) 1276 # define RADEON_TXFORMAT_SHADOW32 (17 << 0) 1277 # define RADEON_TXFORMAT_DUDV88 (18 << 0) 1278 # define RADEON_TXFORMAT_LDUDV655 (19 << 0) 1279 # define RADEON_TXFORMAT_LDUDUV8888 (20 << 0) 1280 # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) 1281 # define RADEON_TXFORMAT_FORMAT_SHIFT 0 1282 # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) 1283 # define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) 1284 # define RADEON_TXFORMAT_NON_POWER2 (1 << 7) 1285 # define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) 1286 # define RADEON_TXFORMAT_WIDTH_SHIFT 8 1287 # define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) 1288 # define RADEON_TXFORMAT_HEIGHT_SHIFT 12 1289 # define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) 1290 # define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 1291 # define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) 1292 # define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 1293 # define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) 1294 # define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) 1295 # define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) 1296 # define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) 1297 # define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) 1298 # define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) 1299 # define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) 1300 # define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) 1301 # define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) 1302 # define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) 1303 # define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) 1304 # define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) 1305 #define RADEON_PP_CUBIC_FACES_0 0x1d24 1306 #define RADEON_PP_CUBIC_FACES_1 0x1d28 1307 #define RADEON_PP_CUBIC_FACES_2 0x1d2c 1308 # define RADEON_FACE_WIDTH_1_SHIFT 0 1309 # define RADEON_FACE_HEIGHT_1_SHIFT 4 1310 # define RADEON_FACE_WIDTH_1_MASK (0xf << 0) 1311 # define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) 1312 # define RADEON_FACE_WIDTH_2_SHIFT 8 1313 # define RADEON_FACE_HEIGHT_2_SHIFT 12 1314 # define RADEON_FACE_WIDTH_2_MASK (0xf << 8) 1315 # define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) 1316 # define RADEON_FACE_WIDTH_3_SHIFT 16 1317 # define RADEON_FACE_HEIGHT_3_SHIFT 20 1318 # define RADEON_FACE_WIDTH_3_MASK (0xf << 16) 1319 # define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) 1320 # define RADEON_FACE_WIDTH_4_SHIFT 24 1321 # define RADEON_FACE_HEIGHT_4_SHIFT 28 1322 # define RADEON_FACE_WIDTH_4_MASK (0xf << 24) 1323 # define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) 1324 1325 #define RADEON_PP_TXOFFSET_0 0x1c5c 1326 #define RADEON_PP_TXOFFSET_1 0x1c74 1327 #define RADEON_PP_TXOFFSET_2 0x1c8c 1328 # define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) 1329 # define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) 1330 # define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) 1331 # define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 1332 # define RADEON_TXO_MACRO_LINEAR (0 << 2) 1333 # define RADEON_TXO_MACRO_TILE (1 << 2) 1334 # define RADEON_TXO_MICRO_LINEAR (0 << 3) 1335 # define RADEON_TXO_MICRO_TILE_X2 (1 << 3) 1336 # define RADEON_TXO_MICRO_TILE_OPT (2 << 3) 1337 # define RADEON_TXO_OFFSET_MASK 0xffffffe0 1338 # define RADEON_TXO_OFFSET_SHIFT 5 1339 1340 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1341 #define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 1342 #define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 1343 #define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc 1344 #define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 1345 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1346 #define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 1347 #define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 1348 #define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c 1349 #define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 1350 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1351 #define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 1352 #define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c 1353 #define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 1354 #define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 1355 1356 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1357 #define RADEON_PP_TEX_SIZE_1 0x1d0c 1358 #define RADEON_PP_TEX_SIZE_2 0x1d14 1359 # define RADEON_TEX_USIZE_MASK (0x7ff << 0) 1360 # define RADEON_TEX_USIZE_SHIFT 0 1361 # define RADEON_TEX_VSIZE_MASK (0x7ff << 16) 1362 # define RADEON_TEX_VSIZE_SHIFT 16 1363 # define RADEON_SIGNED_RGB_MASK (1 << 30) 1364 # define RADEON_SIGNED_RGB_SHIFT 30 1365 # define RADEON_SIGNED_ALPHA_MASK (1 << 31) 1366 # define RADEON_SIGNED_ALPHA_SHIFT 31 1367 #define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ 1368 #define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ 1369 #define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ 1370 /* note: bits 13-5: 32 byte aligned stride of texture map */ 1371 1372 #define RADEON_PP_TXCBLEND_0 0x1c60 1373 #define RADEON_PP_TXCBLEND_1 0x1c78 1374 #define RADEON_PP_TXCBLEND_2 0x1c90 1375 # define RADEON_COLOR_ARG_A_SHIFT 0 1376 # define RADEON_COLOR_ARG_A_MASK (0x1f << 0) 1377 # define RADEON_COLOR_ARG_A_ZERO (0 << 0) 1378 # define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) 1379 # define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) 1380 # define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) 1381 # define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) 1382 # define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) 1383 # define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) 1384 # define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) 1385 # define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) 1386 # define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) 1387 # define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) 1388 # define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) 1389 # define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) 1390 # define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) 1391 # define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) 1392 # define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) 1393 # define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) 1394 # define RADEON_COLOR_ARG_B_SHIFT 5 1395 # define RADEON_COLOR_ARG_B_MASK (0x1f << 5) 1396 # define RADEON_COLOR_ARG_B_ZERO (0 << 5) 1397 # define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) 1398 # define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) 1399 # define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) 1400 # define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) 1401 # define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) 1402 # define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) 1403 # define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) 1404 # define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) 1405 # define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) 1406 # define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) 1407 # define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) 1408 # define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) 1409 # define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) 1410 # define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) 1411 # define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) 1412 # define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) 1413 # define RADEON_COLOR_ARG_C_SHIFT 10 1414 # define RADEON_COLOR_ARG_C_MASK (0x1f << 10) 1415 # define RADEON_COLOR_ARG_C_ZERO (0 << 10) 1416 # define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) 1417 # define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) 1418 # define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) 1419 # define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) 1420 # define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) 1421 # define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) 1422 # define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) 1423 # define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) 1424 # define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) 1425 # define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) 1426 # define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) 1427 # define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) 1428 # define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) 1429 # define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) 1430 # define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) 1431 # define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) 1432 # define RADEON_COMP_ARG_A (1 << 15) 1433 # define RADEON_COMP_ARG_A_SHIFT 15 1434 # define RADEON_COMP_ARG_B (1 << 16) 1435 # define RADEON_COMP_ARG_B_SHIFT 16 1436 # define RADEON_COMP_ARG_C (1 << 17) 1437 # define RADEON_COMP_ARG_C_SHIFT 17 1438 # define RADEON_BLEND_CTL_MASK (7 << 18) 1439 # define RADEON_BLEND_CTL_ADD (0 << 18) 1440 # define RADEON_BLEND_CTL_SUBTRACT (1 << 18) 1441 # define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) 1442 # define RADEON_BLEND_CTL_BLEND (3 << 18) 1443 # define RADEON_BLEND_CTL_DOT3 (4 << 18) 1444 # define RADEON_SCALE_SHIFT 21 1445 # define RADEON_SCALE_MASK (3 << 21) 1446 # define RADEON_SCALE_1X (0 << 21) 1447 # define RADEON_SCALE_2X (1 << 21) 1448 # define RADEON_SCALE_4X (2 << 21) 1449 # define RADEON_CLAMP_TX (1 << 23) 1450 # define RADEON_T0_EQ_TCUR (1 << 24) 1451 # define RADEON_T1_EQ_TCUR (1 << 25) 1452 # define RADEON_T2_EQ_TCUR (1 << 26) 1453 # define RADEON_T3_EQ_TCUR (1 << 27) 1454 # define RADEON_COLOR_ARG_MASK 0x1f 1455 # define RADEON_COMP_ARG_SHIFT 15 1456 #define RADEON_PP_TXABLEND_0 0x1c64 1457 #define RADEON_PP_TXABLEND_1 0x1c7c 1458 #define RADEON_PP_TXABLEND_2 0x1c94 1459 # define RADEON_ALPHA_ARG_A_SHIFT 0 1460 # define RADEON_ALPHA_ARG_A_MASK (0xf << 0) 1461 # define RADEON_ALPHA_ARG_A_ZERO (0 << 0) 1462 # define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) 1463 # define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) 1464 # define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) 1465 # define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) 1466 # define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) 1467 # define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) 1468 # define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) 1469 # define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) 1470 # define RADEON_ALPHA_ARG_B_SHIFT 4 1471 # define RADEON_ALPHA_ARG_B_MASK (0xf << 4) 1472 # define RADEON_ALPHA_ARG_B_ZERO (0 << 4) 1473 # define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) 1474 # define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) 1475 # define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) 1476 # define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) 1477 # define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) 1478 # define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) 1479 # define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) 1480 # define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) 1481 # define RADEON_ALPHA_ARG_C_SHIFT 8 1482 # define RADEON_ALPHA_ARG_C_MASK (0xf << 8) 1483 # define RADEON_ALPHA_ARG_C_ZERO (0 << 8) 1484 # define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) 1485 # define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) 1486 # define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) 1487 # define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) 1488 # define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) 1489 # define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) 1490 # define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) 1491 # define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) 1492 # define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 12) 1493 # define RADEON_ALPHA_ARG_MASK 0xf 1494 1495 #define RADEON_PP_TFACTOR_0 0x1c68 1496 #define RADEON_PP_TFACTOR_1 0x1c80 1497 #define RADEON_PP_TFACTOR_2 0x1c98 1498 1499 #define RADEON_RB3D_BLENDCNTL 0x1c20 1500 # define RADEON_COMB_FCN_MASK (3 << 12) 1501 # define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) 1502 # define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) 1503 # define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) 1504 # define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) 1505 # define RADEON_SRC_BLEND_GL_ZERO (32 << 16) 1506 # define RADEON_SRC_BLEND_GL_ONE (33 << 16) 1507 # define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) 1508 # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) 1509 # define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) 1510 # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) 1511 # define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) 1512 # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) 1513 # define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) 1514 # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) 1515 # define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) 1516 # define RADEON_SRC_BLEND_MASK (63 << 16) 1517 # define RADEON_DST_BLEND_GL_ZERO (32 << 24) 1518 # define RADEON_DST_BLEND_GL_ONE (33 << 24) 1519 # define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) 1520 # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) 1521 # define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) 1522 # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) 1523 # define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) 1524 # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) 1525 # define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) 1526 # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) 1527 # define RADEON_DST_BLEND_MASK (63 << 24) 1528 #define RADEON_RB3D_CNTL 0x1c3c 1529 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 1530 # define RADEON_PLANE_MASK_ENABLE (1 << 1) 1531 # define RADEON_DITHER_ENABLE (1 << 2) 1532 # define RADEON_ROUND_ENABLE (1 << 3) 1533 # define RADEON_SCALE_DITHER_ENABLE (1 << 4) 1534 # define RADEON_DITHER_INIT (1 << 5) 1535 # define RADEON_ROP_ENABLE (1 << 6) 1536 # define RADEON_STENCIL_ENABLE (1 << 7) 1537 # define RADEON_Z_ENABLE (1 << 8) 1538 # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) 1539 # define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) 1540 # define RADEON_COLOR_FORMAT_RGB565 (4 << 10) 1541 # define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) 1542 # define RADEON_COLOR_FORMAT_RGB332 (7 << 10) 1543 # define RADEON_COLOR_FORMAT_Y8 (8 << 10) 1544 # define RADEON_COLOR_FORMAT_RGB8 (9 << 10) 1545 # define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) 1546 # define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) 1547 # define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) 1548 # define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) 1549 # define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) 1550 # define RADEON_ZBLOCK16 (1 << 15) 1551 #define RADEON_RB3D_COLOROFFSET 0x1c40 1552 # define RADEON_COLOROFFSET_MASK 0xfffffff0 1553 #define RADEON_RB3D_COLORPITCH 0x1c48 1554 # define RADEON_COLORPITCH_MASK 0x000001ff8 1555 # define RADEON_COLOR_TILE_ENABLE (1 << 16) 1556 # define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) 1557 # define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) 1558 # define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) 1559 # define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) 1560 #define RADEON_RB3D_DEPTHOFFSET 0x1c24 1561 #define RADEON_RB3D_DEPTHPITCH 0x1c28 1562 # define RADEON_DEPTHPITCH_MASK 0x00001ff8 1563 # define RADEON_DEPTH_HYPERZ (3 << 16) 1564 # define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) 1565 # define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) 1566 # define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) 1567 #define RADEON_RB3D_PLANEMASK 0x1d84 1568 #define RADEON_RB3D_ROPCNTL 0x1d80 1569 # define RADEON_ROP_MASK (15 << 8) 1570 # define RADEON_ROP_CLEAR (0 << 8) 1571 # define RADEON_ROP_NOR (1 << 8) 1572 # define RADEON_ROP_AND_INVERTED (2 << 8) 1573 # define RADEON_ROP_COPY_INVERTED (3 << 8) 1574 # define RADEON_ROP_AND_REVERSE (4 << 8) 1575 # define RADEON_ROP_INVERT (5 << 8) 1576 # define RADEON_ROP_XOR (6 << 8) 1577 # define RADEON_ROP_NAND (7 << 8) 1578 # define RADEON_ROP_AND (8 << 8) 1579 # define RADEON_ROP_EQUIV (9 << 8) 1580 # define RADEON_ROP_NOOP (10 << 8) 1581 # define RADEON_ROP_OR_INVERTED (11 << 8) 1582 # define RADEON_ROP_COPY (12 << 8) 1583 # define RADEON_ROP_OR_REVERSE (13 << 8) 1584 # define RADEON_ROP_OR (14 << 8) 1585 # define RADEON_ROP_SET (15 << 8) 1586 #define RADEON_RB3D_STENCILREFMASK 0x1d7c 1587 # define RADEON_STENCIL_REF_SHIFT 0 1588 # define RADEON_STENCIL_REF_MASK (0xff << 0) 1589 # define RADEON_STENCIL_MASK_SHIFT 16 1590 # define RADEON_STENCIL_VALUE_MASK (0xff << 16) 1591 # define RADEON_STENCIL_WRITEMASK_SHIFT 24 1592 # define RADEON_STENCIL_WRITE_MASK (0xff << 24) 1593 #define RADEON_RB3D_ZPASS_DATA 0x3290 1594 #define RADEON_RB3D_ZPASS_ADDR 0x3294 1595 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1596 # define RADEON_DEPTH_FORMAT_MASK (0xf << 0) 1597 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1598 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1599 # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) 1600 # define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) 1601 # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) 1602 # define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) 1603 # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) 1604 # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) 1605 # define RADEON_Z_TEST_NEVER (0 << 4) 1606 # define RADEON_Z_TEST_LESS (1 << 4) 1607 # define RADEON_Z_TEST_LEQUAL (2 << 4) 1608 # define RADEON_Z_TEST_EQUAL (3 << 4) 1609 # define RADEON_Z_TEST_GEQUAL (4 << 4) 1610 # define RADEON_Z_TEST_GREATER (5 << 4) 1611 # define RADEON_Z_TEST_NEQUAL (6 << 4) 1612 # define RADEON_Z_TEST_ALWAYS (7 << 4) 1613 # define RADEON_Z_TEST_MASK (7 << 4) 1614 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 1615 # define RADEON_STENCIL_TEST_NEVER (0 << 12) 1616 # define RADEON_STENCIL_TEST_LESS (1 << 12) 1617 # define RADEON_STENCIL_TEST_LEQUAL (2 << 12) 1618 # define RADEON_STENCIL_TEST_EQUAL (3 << 12) 1619 # define RADEON_STENCIL_TEST_GEQUAL (4 << 12) 1620 # define RADEON_STENCIL_TEST_GREATER (5 << 12) 1621 # define RADEON_STENCIL_TEST_NEQUAL (6 << 12) 1622 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 1623 # define RADEON_STENCIL_TEST_MASK (0x7 << 12) 1624 # define RADEON_STENCIL_FAIL_KEEP (0 << 16) 1625 # define RADEON_STENCIL_FAIL_ZERO (1 << 16) 1626 # define RADEON_STENCIL_FAIL_REPLACE (2 << 16) 1627 # define RADEON_STENCIL_FAIL_INC (3 << 16) 1628 # define RADEON_STENCIL_FAIL_DEC (4 << 16) 1629 # define RADEON_STENCIL_FAIL_INVERT (5 << 16) 1630 # define RADEON_STENCIL_FAIL_INC_WRAP (6 << 16) 1631 # define RADEON_STENCIL_FAIL_DEC_WRAP (7 << 16) 1632 # define RADEON_STENCIL_FAIL_MASK (0x7 << 16) 1633 # define RADEON_STENCIL_ZPASS_KEEP (0 << 20) 1634 # define RADEON_STENCIL_ZPASS_ZERO (1 << 20) 1635 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 1636 # define RADEON_STENCIL_ZPASS_INC (3 << 20) 1637 # define RADEON_STENCIL_ZPASS_DEC (4 << 20) 1638 # define RADEON_STENCIL_ZPASS_INVERT (5 << 20) 1639 # define RADEON_STENCIL_ZPASS_INC_WRAP (6 << 20) 1640 # define RADEON_STENCIL_ZPASS_DEC_WRAP (7 << 20) 1641 # define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) 1642 # define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) 1643 # define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) 1644 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 1645 # define RADEON_STENCIL_ZFAIL_INC (3 << 24) 1646 # define RADEON_STENCIL_ZFAIL_DEC (4 << 24) 1647 # define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) 1648 # define RADEON_STENCIL_ZFAIL_INC_WRAP (6 << 24) 1649 # define RADEON_STENCIL_ZFAIL_DEC_WRAP (7 << 24) 1650 # define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) 1651 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 1652 # define RADEON_FORCE_Z_DIRTY (1 << 29) 1653 # define RADEON_Z_WRITE_ENABLE (1 << 30) 1654 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 1655 1656 #define RADEON_RE_STIPPLE_ADDR 0x1cc8 1657 #define RADEON_RE_STIPPLE_DATA 0x1ccc 1658 #define RADEON_RE_LINE_PATTERN 0x1cd0 1659 # define RADEON_LINE_PATTERN_MASK 0x0000ffff 1660 # define RADEON_LINE_REPEAT_COUNT_SHIFT 16 1661 # define RADEON_LINE_PATTERN_START_SHIFT 24 1662 # define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) 1663 # define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) 1664 # define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) 1665 #define RADEON_RE_LINE_STATE 0x1cd4 1666 # define RADEON_LINE_CURRENT_PTR_SHIFT 0 1667 # define RADEON_LINE_CURRENT_COUNT_SHIFT 8 1668 #define RADEON_RE_MISC 0x26c4 1669 # define RADEON_STIPPLE_COORD_MASK 0x1f 1670 # define RADEON_STIPPLE_X_OFFSET_SHIFT 0 1671 # define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) 1672 # define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 1673 # define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) 1674 # define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) 1675 # define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) 1676 #define RADEON_RE_SOLID_COLOR 0x1c1c 1677 #define RADEON_RE_TOP_LEFT 0x26c0 1678 # define RADEON_RE_LEFT_SHIFT 0 1679 # define RADEON_RE_TOP_SHIFT 16 1680 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 1681 # define RADEON_RE_WIDTH_SHIFT 0 1682 # define RADEON_RE_HEIGHT_SHIFT 16 1683 1684 #define RADEON_SE_CNTL 0x1c4c 1685 # define RADEON_FFACE_CULL_CW (0 << 0) 1686 # define RADEON_FFACE_CULL_CCW (1 << 0) 1687 # define RADEON_FFACE_CULL_DIR_MASK (1 << 0) 1688 # define RADEON_BFACE_CULL (0 << 1) 1689 # define RADEON_BFACE_SOLID (3 << 1) 1690 # define RADEON_FFACE_CULL (0 << 3) 1691 # define RADEON_FFACE_SOLID (3 << 3) 1692 # define RADEON_FFACE_CULL_MASK (3 << 3) 1693 # define RADEON_BADVTX_CULL_DISABLE (1 << 5) 1694 # define RADEON_FLAT_SHADE_VTX_0 (0 << 6) 1695 # define RADEON_FLAT_SHADE_VTX_1 (1 << 6) 1696 # define RADEON_FLAT_SHADE_VTX_2 (2 << 6) 1697 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 1698 # define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) 1699 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 1700 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 1701 # define RADEON_DIFFUSE_SHADE_MASK (3 << 8) 1702 # define RADEON_ALPHA_SHADE_SOLID (0 << 10) 1703 # define RADEON_ALPHA_SHADE_FLAT (1 << 10) 1704 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 1705 # define RADEON_ALPHA_SHADE_MASK (3 << 10) 1706 # define RADEON_SPECULAR_SHADE_SOLID (0 << 12) 1707 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 1708 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 1709 # define RADEON_SPECULAR_SHADE_MASK (3 << 12) 1710 # define RADEON_FOG_SHADE_SOLID (0 << 14) 1711 # define RADEON_FOG_SHADE_FLAT (1 << 14) 1712 # define RADEON_FOG_SHADE_GOURAUD (2 << 14) 1713 # define RADEON_FOG_SHADE_MASK (3 << 14) 1714 # define RADEON_ZBIAS_ENABLE_POINT (1 << 16) 1715 # define RADEON_ZBIAS_ENABLE_LINE (1 << 17) 1716 # define RADEON_ZBIAS_ENABLE_TRI (1 << 18) 1717 # define RADEON_WIDELINE_ENABLE (1 << 20) 1718 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 1719 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 1720 # define RADEON_VTX_PIX_CENTER_D3D (0 << 27) 1721 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 1722 # define RADEON_ROUND_MODE_TRUNC (0 << 28) 1723 # define RADEON_ROUND_MODE_ROUND (1 << 28) 1724 # define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) 1725 # define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) 1726 # define RADEON_ROUND_PREC_16TH_PIX (0 << 30) 1727 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 1728 # define RADEON_ROUND_PREC_4TH_PIX (2 << 30) 1729 # define RADEON_ROUND_PREC_HALF_PIX (3 << 30) 1730 #define RADEON_SE_CNTL_STATUS 0x2140 1731 # define RADEON_VC_NO_SWAP (0 << 0) 1732 # define RADEON_VC_16BIT_SWAP (1 << 0) 1733 # define RADEON_VC_32BIT_SWAP (2 << 0) 1734 # define RADEON_VC_HALF_DWORD_SWAP (3 << 0) 1735 # define RADEON_TCL_BYPASS (1 << 8) 1736 #define RADEON_SE_COORD_FMT 0x1c50 1737 # define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) 1738 # define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) 1739 # define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) 1740 # define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) 1741 # define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) 1742 # define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) 1743 # define RADEON_VTX_W0_NORMALIZE (1 << 12) 1744 # define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) 1745 # define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) 1746 # define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) 1747 # define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) 1748 # define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) 1749 # define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) 1750 # define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) 1751 #define RADEON_SE_LINE_WIDTH 0x1db8 1752 #define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c 1753 # define RADEON_LIGHTING_ENABLE (1 << 0) 1754 # define RADEON_LIGHT_IN_MODELSPACE (1 << 1) 1755 # define RADEON_LOCAL_VIEWER (1 << 2) 1756 # define RADEON_NORMALIZE_NORMALS (1 << 3) 1757 # define RADEON_RESCALE_NORMALS (1 << 4) 1758 # define RADEON_SPECULAR_LIGHTS (1 << 5) 1759 # define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) 1760 # define RADEON_LIGHT_ALPHA (1 << 7) 1761 # define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) 1762 # define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) 1763 # define RADEON_LM_SOURCE_STATE_PREMULT 0 1764 # define RADEON_LM_SOURCE_STATE_MULT 1 1765 # define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 1766 # define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 1767 # define RADEON_EMISSIVE_SOURCE_SHIFT 16 1768 # define RADEON_AMBIENT_SOURCE_SHIFT 18 1769 # define RADEON_DIFFUSE_SOURCE_SHIFT 20 1770 # define RADEON_SPECULAR_SOURCE_SHIFT 22 1771 #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 1772 #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 1773 #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 1774 #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c 1775 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 1776 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 1777 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 1778 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c 1779 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 1780 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 1781 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 1782 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c 1783 #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 1784 #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 1785 #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 1786 #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c 1787 #define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c 1788 # define RADEON_MODELVIEW_0_SHIFT 0 1789 # define RADEON_MODELVIEW_1_SHIFT 4 1790 # define RADEON_MODELVIEW_2_SHIFT 8 1791 # define RADEON_MODELVIEW_3_SHIFT 12 1792 # define RADEON_IT_MODELVIEW_0_SHIFT 16 1793 # define RADEON_IT_MODELVIEW_1_SHIFT 20 1794 # define RADEON_IT_MODELVIEW_2_SHIFT 24 1795 # define RADEON_IT_MODELVIEW_3_SHIFT 28 1796 #define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 1797 # define RADEON_MODELPROJECT_0_SHIFT 0 1798 # define RADEON_MODELPROJECT_1_SHIFT 4 1799 # define RADEON_MODELPROJECT_2_SHIFT 8 1800 # define RADEON_MODELPROJECT_3_SHIFT 12 1801 # define RADEON_TEXMAT_0_SHIFT 16 1802 # define RADEON_TEXMAT_1_SHIFT 20 1803 # define RADEON_TEXMAT_2_SHIFT 24 1804 # define RADEON_TEXMAT_3_SHIFT 28 1805 1806 1807 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 1808 # define RADEON_TCL_VTX_W0 (1 << 0) 1809 # define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) 1810 # define RADEON_TCL_VTX_FP_ALPHA (1 << 2) 1811 # define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) 1812 # define RADEON_TCL_VTX_FP_SPEC (1 << 4) 1813 # define RADEON_TCL_VTX_FP_FOG (1 << 5) 1814 # define RADEON_TCL_VTX_PK_SPEC (1 << 6) 1815 # define RADEON_TCL_VTX_ST0 (1 << 7) 1816 # define RADEON_TCL_VTX_ST1 (1 << 8) 1817 # define RADEON_TCL_VTX_Q1 (1 << 9) 1818 # define RADEON_TCL_VTX_ST2 (1 << 10) 1819 # define RADEON_TCL_VTX_Q2 (1 << 11) 1820 # define RADEON_TCL_VTX_ST3 (1 << 12) 1821 # define RADEON_TCL_VTX_Q3 (1 << 13) 1822 # define RADEON_TCL_VTX_Q0 (1 << 14) 1823 # define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 1824 # define RADEON_TCL_VTX_NORM0 (1 << 18) 1825 # define RADEON_TCL_VTX_XY1 (1 << 27) 1826 # define RADEON_TCL_VTX_Z1 (1 << 28) 1827 # define RADEON_TCL_VTX_W1 (1 << 29) 1828 # define RADEON_TCL_VTX_NORM1 (1 << 30) 1829 # define RADEON_TCL_VTX_Z0 (1 << 31) 1830 1831 #define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 1832 # define RADEON_TCL_COMPUTE_XYZW (1 << 0) 1833 # define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) 1834 # define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) 1835 # define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) 1836 # define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) 1837 # define RADEON_TCL_TEX_INPUT_TEX_0 0 1838 # define RADEON_TCL_TEX_INPUT_TEX_1 1 1839 # define RADEON_TCL_TEX_INPUT_TEX_2 2 1840 # define RADEON_TCL_TEX_INPUT_TEX_3 3 1841 # define RADEON_TCL_TEX_COMPUTED_TEX_0 8 1842 # define RADEON_TCL_TEX_COMPUTED_TEX_1 9 1843 # define RADEON_TCL_TEX_COMPUTED_TEX_2 10 1844 # define RADEON_TCL_TEX_COMPUTED_TEX_3 11 1845 # define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 1846 # define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 1847 # define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 1848 # define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 1849 1850 #define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 1851 # define RADEON_LIGHT_0_ENABLE (1 << 0) 1852 # define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) 1853 # define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) 1854 # define RADEON_LIGHT_0_IS_LOCAL (1 << 3) 1855 # define RADEON_LIGHT_0_IS_SPOT (1 << 4) 1856 # define RADEON_LIGHT_0_DUAL_CONE (1 << 5) 1857 # define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) 1858 # define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) 1859 # define RADEON_LIGHT_0_SHIFT 0 1860 # define RADEON_LIGHT_1_ENABLE (1 << 16) 1861 # define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) 1862 # define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) 1863 # define RADEON_LIGHT_1_IS_LOCAL (1 << 19) 1864 # define RADEON_LIGHT_1_IS_SPOT (1 << 20) 1865 # define RADEON_LIGHT_1_DUAL_CONE (1 << 21) 1866 # define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) 1867 # define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) 1868 # define RADEON_LIGHT_1_SHIFT 16 1869 #define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 1870 # define RADEON_LIGHT_2_SHIFT 0 1871 # define RADEON_LIGHT_3_SHIFT 16 1872 #define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 1873 # define RADEON_LIGHT_4_SHIFT 0 1874 # define RADEON_LIGHT_5_SHIFT 16 1875 #define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c 1876 # define RADEON_LIGHT_6_SHIFT 0 1877 # define RADEON_LIGHT_7_SHIFT 16 1878 1879 #define RADEON_SE_TCL_STATE_FLUSH 0x2284 1880 1881 #define RADEON_SE_TCL_SHININESS 0x2250 1882 1883 #define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 1884 # define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) 1885 # define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) 1886 # define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) 1887 # define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) 1888 # define RADEON_TEXMAT_0_ENABLE (1 << 4) 1889 # define RADEON_TEXMAT_1_ENABLE (1 << 5) 1890 # define RADEON_TEXMAT_2_ENABLE (1 << 6) 1891 # define RADEON_TEXMAT_3_ENABLE (1 << 7) 1892 # define RADEON_TEXGEN_INPUT_MASK 0xf 1893 # define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 1894 # define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 1895 # define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 1896 # define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 1897 # define RADEON_TEXGEN_INPUT_OBJ 4 1898 # define RADEON_TEXGEN_INPUT_EYE 5 1899 # define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 1900 # define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 1901 # define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 1902 # define RADEON_TEXGEN_0_INPUT_SHIFT 16 1903 # define RADEON_TEXGEN_1_INPUT_SHIFT 20 1904 # define RADEON_TEXGEN_2_INPUT_SHIFT 24 1905 # define RADEON_TEXGEN_3_INPUT_SHIFT 28 1906 1907 #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 1908 # define RADEON_UCP_IN_CLIP_SPACE (1 << 0) 1909 # define RADEON_UCP_IN_MODEL_SPACE (1 << 1) 1910 # define RADEON_UCP_ENABLE_0 (1 << 2) 1911 # define RADEON_UCP_ENABLE_1 (1 << 3) 1912 # define RADEON_UCP_ENABLE_2 (1 << 4) 1913 # define RADEON_UCP_ENABLE_3 (1 << 5) 1914 # define RADEON_UCP_ENABLE_4 (1 << 6) 1915 # define RADEON_UCP_ENABLE_5 (1 << 7) 1916 # define RADEON_TCL_FOG_MASK (3 << 8) 1917 # define RADEON_TCL_FOG_DISABLE (0 << 8) 1918 # define RADEON_TCL_FOG_EXP (1 << 8) 1919 # define RADEON_TCL_FOG_EXP2 (2 << 8) 1920 # define RADEON_TCL_FOG_LINEAR (3 << 8) 1921 # define RADEON_RNG_BASED_FOG (1 << 10) 1922 # define RADEON_LIGHT_TWOSIDE (1 << 11) 1923 # define RADEON_BLEND_OP_COUNT_MASK (7 << 12) 1924 # define RADEON_BLEND_OP_COUNT_SHIFT 12 1925 # define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) 1926 # define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) 1927 # define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (0 << 18) 1928 # define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) 1929 # define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (0 << 19) 1930 # define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) 1931 # define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (0 << 20) 1932 # define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) 1933 # define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (0 << 21) 1934 # define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) 1935 # define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) 1936 # define RADEON_CULL_FRONT_IS_CW (0 << 28) 1937 # define RADEON_CULL_FRONT_IS_CCW (1 << 28) 1938 # define RADEON_CULL_FRONT (1 << 29) 1939 # define RADEON_CULL_BACK (1 << 30) 1940 # define RADEON_FORCE_W_TO_ONE (1 << 31) 1941 1942 #define RADEON_SE_VPORT_XSCALE 0x1d98 1943 #define RADEON_SE_VPORT_XOFFSET 0x1d9c 1944 #define RADEON_SE_VPORT_YSCALE 0x1da0 1945 #define RADEON_SE_VPORT_YOFFSET 0x1da4 1946 #define RADEON_SE_VPORT_ZSCALE 0x1da8 1947 #define RADEON_SE_VPORT_ZOFFSET 0x1dac 1948 #define RADEON_SE_ZBIAS_FACTOR 0x1db0 1949 #define RADEON_SE_ZBIAS_CONSTANT 0x1db4 1950 1951 #define RADEON_SE_VTX_FMT 0x2080 1952 # define RADEON_SE_VTX_FMT_XY 0x00000000 1953 # define RADEON_SE_VTX_FMT_W0 0x00000001 1954 # define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 1955 # define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 1956 # define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 1957 # define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 1958 # define RADEON_SE_VTX_FMT_FPFOG 0x00000020 1959 # define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 1960 # define RADEON_SE_VTX_FMT_ST0 0x00000080 1961 # define RADEON_SE_VTX_FMT_ST1 0x00000100 1962 # define RADEON_SE_VTX_FMT_Q1 0x00000200 1963 # define RADEON_SE_VTX_FMT_ST2 0x00000400 1964 # define RADEON_SE_VTX_FMT_Q2 0x00000800 1965 # define RADEON_SE_VTX_FMT_ST3 0x00001000 1966 # define RADEON_SE_VTX_FMT_Q3 0x00002000 1967 # define RADEON_SE_VTX_FMT_Q0 0x00004000 1968 # define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 1969 # define RADEON_SE_VTX_FMT_N0 0x00040000 1970 # define RADEON_SE_VTX_FMT_XY1 0x08000000 1971 # define RADEON_SE_VTX_FMT_Z1 0x10000000 1972 # define RADEON_SE_VTX_FMT_W1 0x20000000 1973 # define RADEON_SE_VTX_FMT_N1 0x40000000 1974 # define RADEON_SE_VTX_FMT_Z 0x80000000 1975 1976 /* Registers for CP and Microcode Engine */ 1977 #define RADEON_CP_ME_RAM_ADDR 0x07d4 1978 #define RADEON_CP_ME_RAM_RADDR 0x07d8 1979 #define RADEON_CP_ME_RAM_DATAH 0x07dc 1980 #define RADEON_CP_ME_RAM_DATAL 0x07e0 1981 1982 #define RADEON_CP_RB_BASE 0x0700 1983 #define RADEON_CP_RB_CNTL 0x0704 1984 #define RADEON_CP_RB_RPTR_ADDR 0x070c 1985 #define RADEON_CP_RB_RPTR 0x0710 1986 #define RADEON_CP_RB_WPTR 0x0714 1987 1988 #define RADEON_CP_IB_BASE 0x0738 1989 #define RADEON_CP_IB_BUFSZ 0x073c 1990 1991 #define RADEON_CP_CSQ_CNTL 0x0740 1992 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1993 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1994 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1995 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1996 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1997 # define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1998 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1999 #define RADEON_CP_CSQ_STAT 0x07f8 2000 # define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) 2001 # define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) 2002 # define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) 2003 # define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) 2004 #define RADEON_CP_CSQ_ADDR 0x07f0 2005 #define RADEON_CP_CSQ_DATA 0x07f4 2006 #define RADEON_CP_CSQ_APER_PRIMARY 0x1000 2007 #define RADEON_CP_CSQ_APER_INDIRECT 0x1300 2008 2009 #define RADEON_CP_RB_WPTR_DELAY 0x0718 2010 # define RADEON_PRE_WRITE_TIMER_SHIFT 0 2011 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 2012 2013 #define RADEON_AIC_CNTL 0x01d0 2014 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 2015 #define RADEON_AIC_LO_ADDR 0x01dc 2016 2017 2018 2019 /* Constants */ 2020 #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 2021 #define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 2022 2023 2024 2025 /* CP packet types */ 2026 #define RADEON_CP_PACKET0 0x00000000 2027 #define RADEON_CP_PACKET1 0x40000000 2028 #define RADEON_CP_PACKET2 0x80000000 2029 #define RADEON_CP_PACKET3 0xC0000000 2030 # define RADEON_CP_PACKET_MASK 0xC0000000 2031 # define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 2032 # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) 2033 # define RADEON_CP_PACKET0_REG_MASK 0x000007ff 2034 # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 2035 # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 2036 2037 #define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 2038 2039 #define RADEON_CP_PACKET3_NOP 0xC0001000 2040 #define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 2041 #define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 2042 #define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 2043 #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 2044 #define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 2045 #define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 2046 #define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 2047 #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 2048 #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 2049 #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 2050 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 2051 #define R200_CP_CMD_3D_DRAW_VBUF_2 0xC0003400 2052 #define R200_CP_CMD_3D_DRAW_IMMD_2 0xC0003500 2053 #define R200_CP_CMD_3D_DRAW_INDX_2 0xC0003600 2054 #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 2055 #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 2056 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 2057 #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 2058 #define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 2059 #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 2060 #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 2061 #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 2062 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 2063 2064 2065 #define RADEON_CP_VC_FRMT_XY 0x00000000 2066 #define RADEON_CP_VC_FRMT_W0 0x00000001 2067 #define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 2068 #define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 2069 #define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 2070 #define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 2071 #define RADEON_CP_VC_FRMT_FPFOG 0x00000020 2072 #define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 2073 #define RADEON_CP_VC_FRMT_ST0 0x00000080 2074 #define RADEON_CP_VC_FRMT_ST1 0x00000100 2075 #define RADEON_CP_VC_FRMT_Q1 0x00000200 2076 #define RADEON_CP_VC_FRMT_ST2 0x00000400 2077 #define RADEON_CP_VC_FRMT_Q2 0x00000800 2078 #define RADEON_CP_VC_FRMT_ST3 0x00001000 2079 #define RADEON_CP_VC_FRMT_Q3 0x00002000 2080 #define RADEON_CP_VC_FRMT_Q0 0x00004000 2081 #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 2082 #define RADEON_CP_VC_FRMT_N0 0x00040000 2083 #define RADEON_CP_VC_FRMT_XY1 0x08000000 2084 #define RADEON_CP_VC_FRMT_Z1 0x10000000 2085 #define RADEON_CP_VC_FRMT_W1 0x20000000 2086 #define RADEON_CP_VC_FRMT_N1 0x40000000 2087 #define RADEON_CP_VC_FRMT_Z 0x80000000 2088 2089 #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 2090 #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 2091 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 2092 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 2093 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 2094 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 2095 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 2096 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 2097 #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 2098 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 2099 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a 2100 #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 2101 #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 2102 #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 2103 #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 2104 #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 2105 #define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 2106 #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 2107 #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 2108 #define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 2109 #define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 2110 #define RADEON_CP_VC_CNTL_NUM_SHIFT 16 2111 2112 #define RADEON_VS_MATRIX_0_ADDR 0 2113 #define RADEON_VS_MATRIX_1_ADDR 4 2114 #define RADEON_VS_MATRIX_2_ADDR 8 2115 #define RADEON_VS_MATRIX_3_ADDR 12 2116 #define RADEON_VS_MATRIX_4_ADDR 16 2117 #define RADEON_VS_MATRIX_5_ADDR 20 2118 #define RADEON_VS_MATRIX_6_ADDR 24 2119 #define RADEON_VS_MATRIX_7_ADDR 28 2120 #define RADEON_VS_MATRIX_8_ADDR 32 2121 #define RADEON_VS_MATRIX_9_ADDR 36 2122 #define RADEON_VS_MATRIX_10_ADDR 40 2123 #define RADEON_VS_MATRIX_11_ADDR 44 2124 #define RADEON_VS_MATRIX_12_ADDR 48 2125 #define RADEON_VS_MATRIX_13_ADDR 52 2126 #define RADEON_VS_MATRIX_14_ADDR 56 2127 #define RADEON_VS_MATRIX_15_ADDR 60 2128 #define RADEON_VS_LIGHT_AMBIENT_ADDR 64 2129 #define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 2130 #define RADEON_VS_LIGHT_SPECULAR_ADDR 80 2131 #define RADEON_VS_LIGHT_DIRPOS_ADDR 88 2132 #define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 2133 #define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 2134 #define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 2135 #define RADEON_VS_UCP_ADDR 116 2136 #define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 2137 #define RADEON_VS_FOG_PARAM_ADDR 123 2138 #define RADEON_VS_EYE_VECTOR_ADDR 124 2139 2140 #define RADEON_SS_LIGHT_DCD_ADDR 0 2141 #define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 2142 #define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 2143 #define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 2144 #define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 2145 #define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 2146 #define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 2147 #define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 2148 #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 2149 #define RADEON_SS_SHININESS 60 2150 2151 #define RADEON_TV_MASTER_CNTL 0x0800 2152 # define RADEON_TVCLK_ALWAYS_ONb (1 << 30) 2153 #define RADEON_TV_DAC_CNTL 0x088c 2154 # define RADEON_TV_DAC_CMPOUT (1 << 5) 2155 #define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 2156 # define RADEON_Y_RED_EN (1 << 0) 2157 # define RADEON_C_GRN_EN (1 << 1) 2158 # define RADEON_CMP_BLU_EN (1 << 2) 2159 # define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) 2160 # define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) 2161 # define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) 2162 # define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 2163 #endif 2164