1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4 5; These tests are each targeted at a particular RISC-V ALU instruction. Other 6; files in this folder exercise LLVM IR instructions that don't directly match a 7; RISC-V instruction 8 9; Register-immediate instructions 10 11define i32 @addi(i32 %a) nounwind { 12; RV32I-LABEL: addi: 13; RV32I: # %bb.0: 14; RV32I-NEXT: addi a0, a0, 1 15; RV32I-NEXT: ret 16 %1 = add i32 %a, 1 17 ret i32 %1 18} 19 20define i32 @slti(i32 %a) nounwind { 21; RV32I-LABEL: slti: 22; RV32I: # %bb.0: 23; RV32I-NEXT: slti a0, a0, 2 24; RV32I-NEXT: ret 25 %1 = icmp slt i32 %a, 2 26 %2 = zext i1 %1 to i32 27 ret i32 %2 28} 29 30define i32 @sltiu(i32 %a) nounwind { 31; RV32I-LABEL: sltiu: 32; RV32I: # %bb.0: 33; RV32I-NEXT: sltiu a0, a0, 3 34; RV32I-NEXT: ret 35 %1 = icmp ult i32 %a, 3 36 %2 = zext i1 %1 to i32 37 ret i32 %2 38} 39 40define i32 @xori(i32 %a) nounwind { 41; RV32I-LABEL: xori: 42; RV32I: # %bb.0: 43; RV32I-NEXT: xori a0, a0, 4 44; RV32I-NEXT: ret 45 %1 = xor i32 %a, 4 46 ret i32 %1 47} 48 49define i32 @ori(i32 %a) nounwind { 50; RV32I-LABEL: ori: 51; RV32I: # %bb.0: 52; RV32I-NEXT: ori a0, a0, 5 53; RV32I-NEXT: ret 54 %1 = or i32 %a, 5 55 ret i32 %1 56} 57 58define i32 @andi(i32 %a) nounwind { 59; RV32I-LABEL: andi: 60; RV32I: # %bb.0: 61; RV32I-NEXT: andi a0, a0, 6 62; RV32I-NEXT: ret 63 %1 = and i32 %a, 6 64 ret i32 %1 65} 66 67define i32 @slli(i32 %a) nounwind { 68; RV32I-LABEL: slli: 69; RV32I: # %bb.0: 70; RV32I-NEXT: slli a0, a0, 7 71; RV32I-NEXT: ret 72 %1 = shl i32 %a, 7 73 ret i32 %1 74} 75 76define i32 @srli(i32 %a) nounwind { 77; RV32I-LABEL: srli: 78; RV32I: # %bb.0: 79; RV32I-NEXT: srli a0, a0, 8 80; RV32I-NEXT: ret 81 %1 = lshr i32 %a, 8 82 ret i32 %1 83} 84 85define i32 @srai(i32 %a) nounwind { 86; RV32I-LABEL: srai: 87; RV32I: # %bb.0: 88; RV32I-NEXT: srai a0, a0, 9 89; RV32I-NEXT: ret 90 %1 = ashr i32 %a, 9 91 ret i32 %1 92} 93 94; Register-register instructions 95 96define i32 @add(i32 %a, i32 %b) nounwind { 97; RV32I-LABEL: add: 98; RV32I: # %bb.0: 99; RV32I-NEXT: add a0, a0, a1 100; RV32I-NEXT: ret 101 %1 = add i32 %a, %b 102 ret i32 %1 103} 104 105define i32 @sub(i32 %a, i32 %b) nounwind { 106; RV32I-LABEL: sub: 107; RV32I: # %bb.0: 108; RV32I-NEXT: sub a0, a0, a1 109; RV32I-NEXT: ret 110 %1 = sub i32 %a, %b 111 ret i32 %1 112} 113 114define i32 @sll(i32 %a, i32 %b) nounwind { 115; RV32I-LABEL: sll: 116; RV32I: # %bb.0: 117; RV32I-NEXT: sll a0, a0, a1 118; RV32I-NEXT: ret 119 %1 = shl i32 %a, %b 120 ret i32 %1 121} 122 123define i32 @slt(i32 %a, i32 %b) nounwind { 124; RV32I-LABEL: slt: 125; RV32I: # %bb.0: 126; RV32I-NEXT: slt a0, a0, a1 127; RV32I-NEXT: ret 128 %1 = icmp slt i32 %a, %b 129 %2 = zext i1 %1 to i32 130 ret i32 %2 131} 132 133define i32 @sltu(i32 %a, i32 %b) nounwind { 134; RV32I-LABEL: sltu: 135; RV32I: # %bb.0: 136; RV32I-NEXT: sltu a0, a0, a1 137; RV32I-NEXT: ret 138 %1 = icmp ult i32 %a, %b 139 %2 = zext i1 %1 to i32 140 ret i32 %2 141} 142 143define i32 @xor(i32 %a, i32 %b) nounwind { 144; RV32I-LABEL: xor: 145; RV32I: # %bb.0: 146; RV32I-NEXT: xor a0, a0, a1 147; RV32I-NEXT: ret 148 %1 = xor i32 %a, %b 149 ret i32 %1 150} 151 152define i32 @srl(i32 %a, i32 %b) nounwind { 153; RV32I-LABEL: srl: 154; RV32I: # %bb.0: 155; RV32I-NEXT: srl a0, a0, a1 156; RV32I-NEXT: ret 157 %1 = lshr i32 %a, %b 158 ret i32 %1 159} 160 161define i32 @sra(i32 %a, i32 %b) nounwind { 162; RV32I-LABEL: sra: 163; RV32I: # %bb.0: 164; RV32I-NEXT: sra a0, a0, a1 165; RV32I-NEXT: ret 166 %1 = ashr i32 %a, %b 167 ret i32 %1 168} 169 170define i32 @or(i32 %a, i32 %b) nounwind { 171; RV32I-LABEL: or: 172; RV32I: # %bb.0: 173; RV32I-NEXT: or a0, a0, a1 174; RV32I-NEXT: ret 175 %1 = or i32 %a, %b 176 ret i32 %1 177} 178 179define i32 @and(i32 %a, i32 %b) nounwind { 180; RV32I-LABEL: and: 181; RV32I: # %bb.0: 182; RV32I-NEXT: and a0, a0, a1 183; RV32I-NEXT: ret 184 %1 = and i32 %a, %b 185 ret i32 %1 186} 187