1//===- ARCRegisterInfo.td - ARC Register defs --------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the ARC register file 12//===----------------------------------------------------------------------===// 13 14class ARCReg<string n, list<string> altNames> : Register<n, altNames> { 15 field bits<6> HwEncoding; 16 let Namespace = "ARC"; 17} 18 19// Registers are identified with 6-bit ID numbers. 20// Core - 32-bit core registers 21class Core<int num, string n, list<string>altNames=[]> : ARCReg<n, altNames> { 22 let HWEncoding = num; 23} 24 25class Status<string n> : ARCReg<n, []> { 26} 27 28// Integer registers 29def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>; 30def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>; 31def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>; 32def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>; 33let CostPerUse=1 in { 34def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>; 35def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>; 36def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>; 37def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>; 38def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>; 39def R9 : Core< 9, "%r9">, DwarfRegNum<[9]>; 40def R10 : Core<10, "%r10">, DwarfRegNum<[10]>; 41def R11 : Core<11, "%r11">, DwarfRegNum<[11]>; 42} 43def R12 : Core<12, "%r12">, DwarfRegNum<[12]>; 44def R13 : Core<13, "%r13">, DwarfRegNum<[13]>; 45def R14 : Core<14, "%r14">, DwarfRegNum<[14]>; 46def R15 : Core<15, "%r15">, DwarfRegNum<[15]>; 47 48let CostPerUse=1 in { 49def R16 : Core<16, "%r16">, DwarfRegNum<[16]>; 50def R17 : Core<17, "%r17">, DwarfRegNum<[17]>; 51def R18 : Core<18, "%r18">, DwarfRegNum<[18]>; 52def R19 : Core<19, "%r19">, DwarfRegNum<[19]>; 53def R20 : Core<20, "%r20">, DwarfRegNum<[20]>; 54def R21 : Core<21, "%r21">, DwarfRegNum<[21]>; 55def R22 : Core<22, "%r22">, DwarfRegNum<[22]>; 56def R23 : Core<23, "%r23">, DwarfRegNum<[23]>; 57def R24 : Core<24, "%r24">, DwarfRegNum<[24]>; 58def R25 : Core<25, "%r25">, DwarfRegNum<[25]>; 59def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>; 60def FP : Core<27, "%fp", ["%r27"]>, DwarfRegNum<[27]>; 61def SP : Core<28, "%sp", ["%r28"]>, DwarfRegNum<[28]>; 62def ILINK : Core<29, "%ilink">, DwarfRegNum<[29]>; 63def R30 : Core<30, "%r30">, DwarfRegNum<[30]>; 64def BLINK: Core<31, "%blink">, DwarfRegNum<[31]>; 65 66def STATUS32 : Status<"status32">, DwarfRegNum<[32]>; 67} 68 69// Register classes. 70// 71def GPR32: RegisterClass<"ARC", [i32], 32, 72 (add R0, R1, R2, R3, 73 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, 74 R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>; 75 76def SREG : RegisterClass<"ARC", [i32], 1, (add STATUS32)>; 77 78def GPR_S : RegisterClass<"ARC", [i32], 8, 79 (add R0, R1, R2, R3, R12, R13, R14, R15)>; 80 81