1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* "Fast" Instruction Selector for the ARM target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10// FastEmit Immediate Predicate functions. 11static bool Predicate_mod_imm(int64_t Imm) { 12 13 return ARM_AM::getSOImmVal(Imm) != -1; 14 15} 16static bool Predicate_imm0_65535(int64_t Imm) { 17 18 return Imm >= 0 && Imm < 65536; 19 20} 21static bool Predicate_imm0_7(int64_t Imm) { 22 23 return Imm >= 0 && Imm < 8; 24 25} 26static bool Predicate_imm8_255(int64_t Imm) { 27 28 return Imm >= 8 && Imm < 256; 29 30} 31static bool Predicate_imm0_255(int64_t Imm) { 32 return Imm >= 0 && Imm < 256; 33} 34static bool Predicate_t2_so_imm(int64_t Imm) { 35 36 return ARM_AM::getT2SOImmVal(Imm) != -1; 37 38} 39static bool Predicate_imm0_4095(int64_t Imm) { 40 41 return Imm >= 0 && Imm < 4096; 42 43} 44static bool Predicate_imm1_31(int64_t Imm) { 45 return Imm > 0 && Imm < 32; 46} 47static bool Predicate_imm0_31(int64_t Imm) { 48 49 return Imm >= 0 && Imm < 32; 50 51} 52static bool Predicate_shr_imm8(int64_t Imm) { 53 return Imm > 0 && Imm <= 8; 54} 55static bool Predicate_shr_imm16(int64_t Imm) { 56 return Imm > 0 && Imm <= 16; 57} 58static bool Predicate_shr_imm32(int64_t Imm) { 59 return Imm > 0 && Imm <= 32; 60} 61static bool Predicate_VectorIndex32(int64_t Imm) { 62 63 return ((uint64_t)Imm) < 2; 64 65} 66static bool Predicate_t2_so_imm_neg(int64_t Imm) { 67 68 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; 69 70} 71 72 73// FastEmit functions for ARMISD::CALL. 74 75unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 76 if (RetVT.SimpleTy != MVT::isVoid) 77 return 0; 78 if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) { 79 return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill); 80 } 81 return 0; 82} 83 84unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 85 switch (VT.SimpleTy) { 86 case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill); 87 default: return 0; 88 } 89} 90 91// FastEmit functions for ARMISD::CALL_NOLINK. 92 93unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 94 if (RetVT.SimpleTy != MVT::isVoid) 95 return 0; 96 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 97 return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill); 98 } 99 if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) { 100 return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill); 101 } 102 if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) { 103 return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill); 104 } 105 return 0; 106} 107 108unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 109 switch (VT.SimpleTy) { 110 case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill); 111 default: return 0; 112 } 113} 114 115// FastEmit functions for ARMISD::CALL_PRED. 116 117unsigned fastEmit_ARMISD_CALL_PRED_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 118 if (RetVT.SimpleTy != MVT::isVoid) 119 return 0; 120 if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) { 121 return fastEmitInst_r(ARM::BLX_pred, &ARM::GPRRegClass, Op0, Op0IsKill); 122 } 123 return 0; 124} 125 126unsigned fastEmit_ARMISD_CALL_PRED_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 127 switch (VT.SimpleTy) { 128 case MVT::i32: return fastEmit_ARMISD_CALL_PRED_MVT_i32_r(RetVT, Op0, Op0IsKill); 129 default: return 0; 130 } 131} 132 133// FastEmit functions for ARMISD::RRX. 134 135unsigned fastEmit_ARMISD_RRX_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 136 if (RetVT.SimpleTy != MVT::i32) 137 return 0; 138 if ((Subtarget->isThumb2())) { 139 return fastEmitInst_r(ARM::t2RRX, &ARM::rGPRRegClass, Op0, Op0IsKill); 140 } 141 if ((!Subtarget->isThumb())) { 142 return fastEmitInst_r(ARM::RRX, &ARM::GPRRegClass, Op0, Op0IsKill); 143 } 144 return 0; 145} 146 147unsigned fastEmit_ARMISD_RRX_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 148 switch (VT.SimpleTy) { 149 case MVT::i32: return fastEmit_ARMISD_RRX_MVT_i32_r(RetVT, Op0, Op0IsKill); 150 default: return 0; 151 } 152} 153 154// FastEmit functions for ARMISD::SRA_FLAG. 155 156unsigned fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 157 if (RetVT.SimpleTy != MVT::i32) 158 return 0; 159 if ((Subtarget->isThumb2())) { 160 return fastEmitInst_r(ARM::t2MOVsra_flag, &ARM::rGPRRegClass, Op0, Op0IsKill); 161 } 162 if ((!Subtarget->isThumb())) { 163 return fastEmitInst_r(ARM::MOVsra_flag, &ARM::GPRRegClass, Op0, Op0IsKill); 164 } 165 return 0; 166} 167 168unsigned fastEmit_ARMISD_SRA_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 169 switch (VT.SimpleTy) { 170 case MVT::i32: return fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill); 171 default: return 0; 172 } 173} 174 175// FastEmit functions for ARMISD::SRL_FLAG. 176 177unsigned fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 178 if (RetVT.SimpleTy != MVT::i32) 179 return 0; 180 if ((Subtarget->isThumb2())) { 181 return fastEmitInst_r(ARM::t2MOVsrl_flag, &ARM::rGPRRegClass, Op0, Op0IsKill); 182 } 183 if ((!Subtarget->isThumb())) { 184 return fastEmitInst_r(ARM::MOVsrl_flag, &ARM::GPRRegClass, Op0, Op0IsKill); 185 } 186 return 0; 187} 188 189unsigned fastEmit_ARMISD_SRL_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 190 switch (VT.SimpleTy) { 191 case MVT::i32: return fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill); 192 default: return 0; 193 } 194} 195 196// FastEmit functions for ARMISD::TC_RETURN. 197 198unsigned fastEmit_ARMISD_TC_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 199 if (RetVT.SimpleTy != MVT::isVoid) 200 return 0; 201 return fastEmitInst_r(ARM::TCRETURNri, &ARM::tcGPRRegClass, Op0, Op0IsKill); 202} 203 204unsigned fastEmit_ARMISD_TC_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 205 switch (VT.SimpleTy) { 206 case MVT::i32: return fastEmit_ARMISD_TC_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill); 207 default: return 0; 208 } 209} 210 211// FastEmit functions for ARMISD::VCEQZ. 212 213unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 214 if (RetVT.SimpleTy != MVT::v8i8) 215 return 0; 216 if ((Subtarget->hasNEON())) { 217 return fastEmitInst_r(ARM::VCEQzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 218 } 219 return 0; 220} 221 222unsigned fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 223 if (RetVT.SimpleTy != MVT::v16i8) 224 return 0; 225 if ((Subtarget->hasNEON())) { 226 return fastEmitInst_r(ARM::VCEQzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill); 227 } 228 return 0; 229} 230 231unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 232 if (RetVT.SimpleTy != MVT::v4i16) 233 return 0; 234 if ((Subtarget->hasNEON())) { 235 return fastEmitInst_r(ARM::VCEQzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 236 } 237 return 0; 238} 239 240unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 241 if (RetVT.SimpleTy != MVT::v8i16) 242 return 0; 243 if ((Subtarget->hasNEON())) { 244 return fastEmitInst_r(ARM::VCEQzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 245 } 246 return 0; 247} 248 249unsigned fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 250 if (RetVT.SimpleTy != MVT::v2i32) 251 return 0; 252 if ((Subtarget->hasNEON())) { 253 return fastEmitInst_r(ARM::VCEQzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 254 } 255 return 0; 256} 257 258unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 259 if (RetVT.SimpleTy != MVT::v4i32) 260 return 0; 261 if ((Subtarget->hasNEON())) { 262 return fastEmitInst_r(ARM::VCEQzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 263 } 264 return 0; 265} 266 267unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 268 if (RetVT.SimpleTy != MVT::v4i16) 269 return 0; 270 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 271 return fastEmitInst_r(ARM::VCEQzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill); 272 } 273 return 0; 274} 275 276unsigned fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 277 if (RetVT.SimpleTy != MVT::v8i16) 278 return 0; 279 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 280 return fastEmitInst_r(ARM::VCEQzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill); 281 } 282 return 0; 283} 284 285unsigned fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 286 if (RetVT.SimpleTy != MVT::v2i32) 287 return 0; 288 if ((Subtarget->hasNEON())) { 289 return fastEmitInst_r(ARM::VCEQzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill); 290 } 291 return 0; 292} 293 294unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 295 if (RetVT.SimpleTy != MVT::v4i32) 296 return 0; 297 if ((Subtarget->hasNEON())) { 298 return fastEmitInst_r(ARM::VCEQzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill); 299 } 300 return 0; 301} 302 303unsigned fastEmit_ARMISD_VCEQZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 304 switch (VT.SimpleTy) { 305 case MVT::v8i8: return fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 306 case MVT::v16i8: return fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 307 case MVT::v4i16: return fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 308 case MVT::v8i16: return fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 309 case MVT::v2i32: return fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 310 case MVT::v4i32: return fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 311 case MVT::v4f16: return fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 312 case MVT::v8f16: return fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 313 case MVT::v2f32: return fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 314 case MVT::v4f32: return fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 315 default: return 0; 316 } 317} 318 319// FastEmit functions for ARMISD::VCGEZ. 320 321unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 322 if (RetVT.SimpleTy != MVT::v8i8) 323 return 0; 324 if ((Subtarget->hasNEON())) { 325 return fastEmitInst_r(ARM::VCGEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 326 } 327 return 0; 328} 329 330unsigned fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 331 if (RetVT.SimpleTy != MVT::v16i8) 332 return 0; 333 if ((Subtarget->hasNEON())) { 334 return fastEmitInst_r(ARM::VCGEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill); 335 } 336 return 0; 337} 338 339unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 340 if (RetVT.SimpleTy != MVT::v4i16) 341 return 0; 342 if ((Subtarget->hasNEON())) { 343 return fastEmitInst_r(ARM::VCGEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 344 } 345 return 0; 346} 347 348unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 349 if (RetVT.SimpleTy != MVT::v8i16) 350 return 0; 351 if ((Subtarget->hasNEON())) { 352 return fastEmitInst_r(ARM::VCGEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 353 } 354 return 0; 355} 356 357unsigned fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 358 if (RetVT.SimpleTy != MVT::v2i32) 359 return 0; 360 if ((Subtarget->hasNEON())) { 361 return fastEmitInst_r(ARM::VCGEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 362 } 363 return 0; 364} 365 366unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 367 if (RetVT.SimpleTy != MVT::v4i32) 368 return 0; 369 if ((Subtarget->hasNEON())) { 370 return fastEmitInst_r(ARM::VCGEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 371 } 372 return 0; 373} 374 375unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 376 if (RetVT.SimpleTy != MVT::v4i16) 377 return 0; 378 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 379 return fastEmitInst_r(ARM::VCGEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill); 380 } 381 return 0; 382} 383 384unsigned fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 385 if (RetVT.SimpleTy != MVT::v8i16) 386 return 0; 387 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 388 return fastEmitInst_r(ARM::VCGEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill); 389 } 390 return 0; 391} 392 393unsigned fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 394 if (RetVT.SimpleTy != MVT::v2i32) 395 return 0; 396 if ((Subtarget->hasNEON())) { 397 return fastEmitInst_r(ARM::VCGEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill); 398 } 399 return 0; 400} 401 402unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 403 if (RetVT.SimpleTy != MVT::v4i32) 404 return 0; 405 if ((Subtarget->hasNEON())) { 406 return fastEmitInst_r(ARM::VCGEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill); 407 } 408 return 0; 409} 410 411unsigned fastEmit_ARMISD_VCGEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 412 switch (VT.SimpleTy) { 413 case MVT::v8i8: return fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 414 case MVT::v16i8: return fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 415 case MVT::v4i16: return fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 416 case MVT::v8i16: return fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 417 case MVT::v2i32: return fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 418 case MVT::v4i32: return fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 419 case MVT::v4f16: return fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 420 case MVT::v8f16: return fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 421 case MVT::v2f32: return fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 422 case MVT::v4f32: return fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 423 default: return 0; 424 } 425} 426 427// FastEmit functions for ARMISD::VCGTZ. 428 429unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 430 if (RetVT.SimpleTy != MVT::v8i8) 431 return 0; 432 if ((Subtarget->hasNEON())) { 433 return fastEmitInst_r(ARM::VCGTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 434 } 435 return 0; 436} 437 438unsigned fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 439 if (RetVT.SimpleTy != MVT::v16i8) 440 return 0; 441 if ((Subtarget->hasNEON())) { 442 return fastEmitInst_r(ARM::VCGTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill); 443 } 444 return 0; 445} 446 447unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 448 if (RetVT.SimpleTy != MVT::v4i16) 449 return 0; 450 if ((Subtarget->hasNEON())) { 451 return fastEmitInst_r(ARM::VCGTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 452 } 453 return 0; 454} 455 456unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 457 if (RetVT.SimpleTy != MVT::v8i16) 458 return 0; 459 if ((Subtarget->hasNEON())) { 460 return fastEmitInst_r(ARM::VCGTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 461 } 462 return 0; 463} 464 465unsigned fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 466 if (RetVT.SimpleTy != MVT::v2i32) 467 return 0; 468 if ((Subtarget->hasNEON())) { 469 return fastEmitInst_r(ARM::VCGTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 470 } 471 return 0; 472} 473 474unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 475 if (RetVT.SimpleTy != MVT::v4i32) 476 return 0; 477 if ((Subtarget->hasNEON())) { 478 return fastEmitInst_r(ARM::VCGTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 479 } 480 return 0; 481} 482 483unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 484 if (RetVT.SimpleTy != MVT::v4i16) 485 return 0; 486 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 487 return fastEmitInst_r(ARM::VCGTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill); 488 } 489 return 0; 490} 491 492unsigned fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 493 if (RetVT.SimpleTy != MVT::v8i16) 494 return 0; 495 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 496 return fastEmitInst_r(ARM::VCGTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill); 497 } 498 return 0; 499} 500 501unsigned fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 502 if (RetVT.SimpleTy != MVT::v2i32) 503 return 0; 504 if ((Subtarget->hasNEON())) { 505 return fastEmitInst_r(ARM::VCGTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill); 506 } 507 return 0; 508} 509 510unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 511 if (RetVT.SimpleTy != MVT::v4i32) 512 return 0; 513 if ((Subtarget->hasNEON())) { 514 return fastEmitInst_r(ARM::VCGTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill); 515 } 516 return 0; 517} 518 519unsigned fastEmit_ARMISD_VCGTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 520 switch (VT.SimpleTy) { 521 case MVT::v8i8: return fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 522 case MVT::v16i8: return fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 523 case MVT::v4i16: return fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 524 case MVT::v8i16: return fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 525 case MVT::v2i32: return fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 526 case MVT::v4i32: return fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 527 case MVT::v4f16: return fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 528 case MVT::v8f16: return fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 529 case MVT::v2f32: return fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 530 case MVT::v4f32: return fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 531 default: return 0; 532 } 533} 534 535// FastEmit functions for ARMISD::VCLEZ. 536 537unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 538 if (RetVT.SimpleTy != MVT::v8i8) 539 return 0; 540 if ((Subtarget->hasNEON())) { 541 return fastEmitInst_r(ARM::VCLEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 542 } 543 return 0; 544} 545 546unsigned fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 547 if (RetVT.SimpleTy != MVT::v16i8) 548 return 0; 549 if ((Subtarget->hasNEON())) { 550 return fastEmitInst_r(ARM::VCLEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill); 551 } 552 return 0; 553} 554 555unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 556 if (RetVT.SimpleTy != MVT::v4i16) 557 return 0; 558 if ((Subtarget->hasNEON())) { 559 return fastEmitInst_r(ARM::VCLEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 560 } 561 return 0; 562} 563 564unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 565 if (RetVT.SimpleTy != MVT::v8i16) 566 return 0; 567 if ((Subtarget->hasNEON())) { 568 return fastEmitInst_r(ARM::VCLEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 569 } 570 return 0; 571} 572 573unsigned fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 574 if (RetVT.SimpleTy != MVT::v2i32) 575 return 0; 576 if ((Subtarget->hasNEON())) { 577 return fastEmitInst_r(ARM::VCLEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 578 } 579 return 0; 580} 581 582unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 583 if (RetVT.SimpleTy != MVT::v4i32) 584 return 0; 585 if ((Subtarget->hasNEON())) { 586 return fastEmitInst_r(ARM::VCLEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 587 } 588 return 0; 589} 590 591unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 592 if (RetVT.SimpleTy != MVT::v4i16) 593 return 0; 594 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 595 return fastEmitInst_r(ARM::VCLEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill); 596 } 597 return 0; 598} 599 600unsigned fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 601 if (RetVT.SimpleTy != MVT::v8i16) 602 return 0; 603 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 604 return fastEmitInst_r(ARM::VCLEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill); 605 } 606 return 0; 607} 608 609unsigned fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 610 if (RetVT.SimpleTy != MVT::v2i32) 611 return 0; 612 if ((Subtarget->hasNEON())) { 613 return fastEmitInst_r(ARM::VCLEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill); 614 } 615 return 0; 616} 617 618unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 619 if (RetVT.SimpleTy != MVT::v4i32) 620 return 0; 621 if ((Subtarget->hasNEON())) { 622 return fastEmitInst_r(ARM::VCLEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill); 623 } 624 return 0; 625} 626 627unsigned fastEmit_ARMISD_VCLEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 628 switch (VT.SimpleTy) { 629 case MVT::v8i8: return fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 630 case MVT::v16i8: return fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 631 case MVT::v4i16: return fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 632 case MVT::v8i16: return fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 633 case MVT::v2i32: return fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 634 case MVT::v4i32: return fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 635 case MVT::v4f16: return fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 636 case MVT::v8f16: return fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 637 case MVT::v2f32: return fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 638 case MVT::v4f32: return fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 639 default: return 0; 640 } 641} 642 643// FastEmit functions for ARMISD::VCLTZ. 644 645unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 646 if (RetVT.SimpleTy != MVT::v8i8) 647 return 0; 648 if ((Subtarget->hasNEON())) { 649 return fastEmitInst_r(ARM::VCLTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 650 } 651 return 0; 652} 653 654unsigned fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 655 if (RetVT.SimpleTy != MVT::v16i8) 656 return 0; 657 if ((Subtarget->hasNEON())) { 658 return fastEmitInst_r(ARM::VCLTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill); 659 } 660 return 0; 661} 662 663unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 664 if (RetVT.SimpleTy != MVT::v4i16) 665 return 0; 666 if ((Subtarget->hasNEON())) { 667 return fastEmitInst_r(ARM::VCLTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 668 } 669 return 0; 670} 671 672unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 673 if (RetVT.SimpleTy != MVT::v8i16) 674 return 0; 675 if ((Subtarget->hasNEON())) { 676 return fastEmitInst_r(ARM::VCLTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 677 } 678 return 0; 679} 680 681unsigned fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 682 if (RetVT.SimpleTy != MVT::v2i32) 683 return 0; 684 if ((Subtarget->hasNEON())) { 685 return fastEmitInst_r(ARM::VCLTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 686 } 687 return 0; 688} 689 690unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 691 if (RetVT.SimpleTy != MVT::v4i32) 692 return 0; 693 if ((Subtarget->hasNEON())) { 694 return fastEmitInst_r(ARM::VCLTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 695 } 696 return 0; 697} 698 699unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 700 if (RetVT.SimpleTy != MVT::v4i16) 701 return 0; 702 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 703 return fastEmitInst_r(ARM::VCLTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill); 704 } 705 return 0; 706} 707 708unsigned fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 709 if (RetVT.SimpleTy != MVT::v8i16) 710 return 0; 711 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 712 return fastEmitInst_r(ARM::VCLTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill); 713 } 714 return 0; 715} 716 717unsigned fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 718 if (RetVT.SimpleTy != MVT::v2i32) 719 return 0; 720 if ((Subtarget->hasNEON())) { 721 return fastEmitInst_r(ARM::VCLTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill); 722 } 723 return 0; 724} 725 726unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 727 if (RetVT.SimpleTy != MVT::v4i32) 728 return 0; 729 if ((Subtarget->hasNEON())) { 730 return fastEmitInst_r(ARM::VCLTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill); 731 } 732 return 0; 733} 734 735unsigned fastEmit_ARMISD_VCLTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 736 switch (VT.SimpleTy) { 737 case MVT::v8i8: return fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 738 case MVT::v16i8: return fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 739 case MVT::v4i16: return fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 740 case MVT::v8i16: return fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 741 case MVT::v2i32: return fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 742 case MVT::v4i32: return fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 743 case MVT::v4f16: return fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 744 case MVT::v8f16: return fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 745 case MVT::v2f32: return fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 746 case MVT::v4f32: return fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 747 default: return 0; 748 } 749} 750 751// FastEmit functions for ARMISD::VDUP. 752 753unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 754 if ((Subtarget->hasNEON())) { 755 return fastEmitInst_r(ARM::VDUP8d, &ARM::DPRRegClass, Op0, Op0IsKill); 756 } 757 return 0; 758} 759 760unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 761 if ((Subtarget->hasNEON())) { 762 return fastEmitInst_r(ARM::VDUP8q, &ARM::QPRRegClass, Op0, Op0IsKill); 763 } 764 return 0; 765} 766 767unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 768 if ((Subtarget->hasNEON())) { 769 return fastEmitInst_r(ARM::VDUP16d, &ARM::DPRRegClass, Op0, Op0IsKill); 770 } 771 return 0; 772} 773 774unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 775 if ((Subtarget->hasNEON())) { 776 return fastEmitInst_r(ARM::VDUP16q, &ARM::QPRRegClass, Op0, Op0IsKill); 777 } 778 return 0; 779} 780 781unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 782 if ((!Subtarget->hasSlowVDUP32()) && (Subtarget->hasNEON())) { 783 return fastEmitInst_r(ARM::VDUP32d, &ARM::DPRRegClass, Op0, Op0IsKill); 784 } 785 return 0; 786} 787 788unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 789 if ((Subtarget->hasNEON())) { 790 return fastEmitInst_r(ARM::VDUP32q, &ARM::QPRRegClass, Op0, Op0IsKill); 791 } 792 return 0; 793} 794 795unsigned fastEmit_ARMISD_VDUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 796switch (RetVT.SimpleTy) { 797 case MVT::v8i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill); 798 case MVT::v16i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill); 799 case MVT::v4i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill); 800 case MVT::v8i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill); 801 case MVT::v2i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill); 802 case MVT::v4i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill); 803 default: return 0; 804} 805} 806 807unsigned fastEmit_ARMISD_VDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 808 switch (VT.SimpleTy) { 809 case MVT::i32: return fastEmit_ARMISD_VDUP_MVT_i32_r(RetVT, Op0, Op0IsKill); 810 default: return 0; 811 } 812} 813 814// FastEmit functions for ARMISD::VMOVSR. 815 816unsigned fastEmit_ARMISD_VMOVSR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 817 if (RetVT.SimpleTy != MVT::f32) 818 return 0; 819 if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) { 820 return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill); 821 } 822 return 0; 823} 824 825unsigned fastEmit_ARMISD_VMOVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 826 switch (VT.SimpleTy) { 827 case MVT::i32: return fastEmit_ARMISD_VMOVSR_MVT_i32_r(RetVT, Op0, Op0IsKill); 828 default: return 0; 829 } 830} 831 832// FastEmit functions for ARMISD::VMOVhr. 833 834unsigned fastEmit_ARMISD_VMOVhr_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 835 if (RetVT.SimpleTy != MVT::f16) 836 return 0; 837 if ((Subtarget->hasFullFP16())) { 838 return fastEmitInst_r(ARM::VMOVHR, &ARM::HPRRegClass, Op0, Op0IsKill); 839 } 840 return 0; 841} 842 843unsigned fastEmit_ARMISD_VMOVhr_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 844 switch (VT.SimpleTy) { 845 case MVT::i32: return fastEmit_ARMISD_VMOVhr_MVT_i32_r(RetVT, Op0, Op0IsKill); 846 default: return 0; 847 } 848} 849 850// FastEmit functions for ARMISD::VMOVrh. 851 852unsigned fastEmit_ARMISD_VMOVrh_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 853 if (RetVT.SimpleTy != MVT::i32) 854 return 0; 855 if ((Subtarget->hasFullFP16())) { 856 return fastEmitInst_r(ARM::VMOVRH, &ARM::GPRRegClass, Op0, Op0IsKill); 857 } 858 return 0; 859} 860 861unsigned fastEmit_ARMISD_VMOVrh_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 862 switch (VT.SimpleTy) { 863 case MVT::f16: return fastEmit_ARMISD_VMOVrh_MVT_f16_r(RetVT, Op0, Op0IsKill); 864 default: return 0; 865 } 866} 867 868// FastEmit functions for ARMISD::VREV16. 869 870unsigned fastEmit_ARMISD_VREV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 871 if (RetVT.SimpleTy != MVT::v8i8) 872 return 0; 873 if ((Subtarget->hasNEON())) { 874 return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill); 875 } 876 return 0; 877} 878 879unsigned fastEmit_ARMISD_VREV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 880 if (RetVT.SimpleTy != MVT::v16i8) 881 return 0; 882 if ((Subtarget->hasNEON())) { 883 return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill); 884 } 885 return 0; 886} 887 888unsigned fastEmit_ARMISD_VREV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 889 switch (VT.SimpleTy) { 890 case MVT::v8i8: return fastEmit_ARMISD_VREV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 891 case MVT::v16i8: return fastEmit_ARMISD_VREV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 892 default: return 0; 893 } 894} 895 896// FastEmit functions for ARMISD::VREV32. 897 898unsigned fastEmit_ARMISD_VREV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 899 if (RetVT.SimpleTy != MVT::v8i8) 900 return 0; 901 if ((Subtarget->hasNEON())) { 902 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 903 } 904 return 0; 905} 906 907unsigned fastEmit_ARMISD_VREV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 908 if (RetVT.SimpleTy != MVT::v16i8) 909 return 0; 910 if ((Subtarget->hasNEON())) { 911 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 912 } 913 return 0; 914} 915 916unsigned fastEmit_ARMISD_VREV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 917 if (RetVT.SimpleTy != MVT::v4i16) 918 return 0; 919 if ((Subtarget->hasNEON())) { 920 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 921 } 922 return 0; 923} 924 925unsigned fastEmit_ARMISD_VREV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 926 if (RetVT.SimpleTy != MVT::v8i16) 927 return 0; 928 if ((Subtarget->hasNEON())) { 929 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 930 } 931 return 0; 932} 933 934unsigned fastEmit_ARMISD_VREV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 935 switch (VT.SimpleTy) { 936 case MVT::v8i8: return fastEmit_ARMISD_VREV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 937 case MVT::v16i8: return fastEmit_ARMISD_VREV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 938 case MVT::v4i16: return fastEmit_ARMISD_VREV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 939 case MVT::v8i16: return fastEmit_ARMISD_VREV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 940 default: return 0; 941 } 942} 943 944// FastEmit functions for ARMISD::VREV64. 945 946unsigned fastEmit_ARMISD_VREV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 947 if (RetVT.SimpleTy != MVT::v8i8) 948 return 0; 949 if ((Subtarget->hasNEON())) { 950 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 951 } 952 return 0; 953} 954 955unsigned fastEmit_ARMISD_VREV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 956 if (RetVT.SimpleTy != MVT::v16i8) 957 return 0; 958 if ((Subtarget->hasNEON())) { 959 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 960 } 961 return 0; 962} 963 964unsigned fastEmit_ARMISD_VREV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 965 if (RetVT.SimpleTy != MVT::v4i16) 966 return 0; 967 if ((Subtarget->hasNEON())) { 968 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 969 } 970 return 0; 971} 972 973unsigned fastEmit_ARMISD_VREV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 974 if (RetVT.SimpleTy != MVT::v8i16) 975 return 0; 976 if ((Subtarget->hasNEON())) { 977 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 978 } 979 return 0; 980} 981 982unsigned fastEmit_ARMISD_VREV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 983 if (RetVT.SimpleTy != MVT::v2i32) 984 return 0; 985 if ((Subtarget->hasNEON())) { 986 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 987 } 988 return 0; 989} 990 991unsigned fastEmit_ARMISD_VREV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 992 if (RetVT.SimpleTy != MVT::v4i32) 993 return 0; 994 if ((Subtarget->hasNEON())) { 995 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 996 } 997 return 0; 998} 999 1000unsigned fastEmit_ARMISD_VREV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1001 if (RetVT.SimpleTy != MVT::v2f32) 1002 return 0; 1003 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1004} 1005 1006unsigned fastEmit_ARMISD_VREV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1007 if (RetVT.SimpleTy != MVT::v4f32) 1008 return 0; 1009 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1010} 1011 1012unsigned fastEmit_ARMISD_VREV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1013 switch (VT.SimpleTy) { 1014 case MVT::v8i8: return fastEmit_ARMISD_VREV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1015 case MVT::v16i8: return fastEmit_ARMISD_VREV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1016 case MVT::v4i16: return fastEmit_ARMISD_VREV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1017 case MVT::v8i16: return fastEmit_ARMISD_VREV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1018 case MVT::v2i32: return fastEmit_ARMISD_VREV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1019 case MVT::v4i32: return fastEmit_ARMISD_VREV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1020 case MVT::v2f32: return fastEmit_ARMISD_VREV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1021 case MVT::v4f32: return fastEmit_ARMISD_VREV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1022 default: return 0; 1023 } 1024} 1025 1026// FastEmit functions for ARMISD::WIN__DBZCHK. 1027 1028unsigned fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1029 if (RetVT.SimpleTy != MVT::isVoid) 1030 return 0; 1031 return fastEmitInst_r(ARM::WIN__DBZCHK, &ARM::tGPRRegClass, Op0, Op0IsKill); 1032} 1033 1034unsigned fastEmit_ARMISD_WIN__DBZCHK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1035 switch (VT.SimpleTy) { 1036 case MVT::i32: return fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(RetVT, Op0, Op0IsKill); 1037 default: return 0; 1038 } 1039} 1040 1041// FastEmit functions for ISD::ABS. 1042 1043unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1044 if (RetVT.SimpleTy != MVT::v8i8) 1045 return 0; 1046 if ((Subtarget->hasNEON())) { 1047 return fastEmitInst_r(ARM::VABSv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 1048 } 1049 return 0; 1050} 1051 1052unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1053 if (RetVT.SimpleTy != MVT::v16i8) 1054 return 0; 1055 if ((Subtarget->hasNEON())) { 1056 return fastEmitInst_r(ARM::VABSv16i8, &ARM::QPRRegClass, Op0, Op0IsKill); 1057 } 1058 return 0; 1059} 1060 1061unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1062 if (RetVT.SimpleTy != MVT::v4i16) 1063 return 0; 1064 if ((Subtarget->hasNEON())) { 1065 return fastEmitInst_r(ARM::VABSv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 1066 } 1067 return 0; 1068} 1069 1070unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1071 if (RetVT.SimpleTy != MVT::v8i16) 1072 return 0; 1073 if ((Subtarget->hasNEON())) { 1074 return fastEmitInst_r(ARM::VABSv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 1075 } 1076 return 0; 1077} 1078 1079unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1080 if (RetVT.SimpleTy != MVT::v2i32) 1081 return 0; 1082 if ((Subtarget->hasNEON())) { 1083 return fastEmitInst_r(ARM::VABSv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 1084 } 1085 return 0; 1086} 1087 1088unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1089 if (RetVT.SimpleTy != MVT::v4i32) 1090 return 0; 1091 if ((Subtarget->hasNEON())) { 1092 return fastEmitInst_r(ARM::VABSv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 1093 } 1094 return 0; 1095} 1096 1097unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1098 switch (VT.SimpleTy) { 1099 case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1100 case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1101 case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1102 case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1103 case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1104 case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1105 default: return 0; 1106 } 1107} 1108 1109// FastEmit functions for ISD::ANY_EXTEND. 1110 1111unsigned fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1112 if (RetVT.SimpleTy != MVT::v8i16) 1113 return 0; 1114 return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 1115} 1116 1117unsigned fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1118 if (RetVT.SimpleTy != MVT::v4i32) 1119 return 0; 1120 return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 1121} 1122 1123unsigned fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1124 if (RetVT.SimpleTy != MVT::v2i64) 1125 return 0; 1126 return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill); 1127} 1128 1129unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1130 switch (VT.SimpleTy) { 1131 case MVT::v8i8: return fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1132 case MVT::v4i16: return fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1133 case MVT::v2i32: return fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1134 default: return 0; 1135 } 1136} 1137 1138// FastEmit functions for ISD::BITCAST. 1139 1140unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1141 if (RetVT.SimpleTy != MVT::f32) 1142 return 0; 1143 if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) { 1144 return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill); 1145 } 1146 return 0; 1147} 1148 1149unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1150 if (RetVT.SimpleTy != MVT::i32) 1151 return 0; 1152 if ((Subtarget->hasVFP2())) { 1153 return fastEmitInst_r(ARM::VMOVRS, &ARM::GPRRegClass, Op0, Op0IsKill); 1154 } 1155 return 0; 1156} 1157 1158unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1159 if ((MF->getDataLayout().isBigEndian())) { 1160 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1161 } 1162 return 0; 1163} 1164 1165unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1166 if ((MF->getDataLayout().isBigEndian())) { 1167 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1168 } 1169 return 0; 1170} 1171 1172unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1173 if ((MF->getDataLayout().isBigEndian())) { 1174 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1175 } 1176 return 0; 1177} 1178 1179unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1180 if ((MF->getDataLayout().isBigEndian())) { 1181 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1182 } 1183 return 0; 1184} 1185 1186unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1187switch (RetVT.SimpleTy) { 1188 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill); 1189 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill); 1190 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill); 1191 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill); 1192 default: return 0; 1193} 1194} 1195 1196unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1197 if ((MF->getDataLayout().isBigEndian())) { 1198 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1199 } 1200 return 0; 1201} 1202 1203unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1204 if ((MF->getDataLayout().isBigEndian())) { 1205 return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1206 } 1207 return 0; 1208} 1209 1210unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1211 if ((MF->getDataLayout().isBigEndian())) { 1212 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1213 } 1214 return 0; 1215} 1216 1217unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1218 if ((MF->getDataLayout().isBigEndian())) { 1219 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1220 } 1221 return 0; 1222} 1223 1224unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1225 if ((MF->getDataLayout().isBigEndian())) { 1226 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1227 } 1228 return 0; 1229} 1230 1231unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1232switch (RetVT.SimpleTy) { 1233 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill); 1234 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill); 1235 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill); 1236 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill); 1237 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill); 1238 default: return 0; 1239} 1240} 1241 1242unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1243 if ((MF->getDataLayout().isBigEndian())) { 1244 return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1245 } 1246 return 0; 1247} 1248 1249unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1250 if ((MF->getDataLayout().isBigEndian())) { 1251 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1252 } 1253 return 0; 1254} 1255 1256unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1257 if ((MF->getDataLayout().isBigEndian())) { 1258 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1259 } 1260 return 0; 1261} 1262 1263unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1264 if ((MF->getDataLayout().isBigEndian())) { 1265 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1266 } 1267 return 0; 1268} 1269 1270unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1271 if ((MF->getDataLayout().isBigEndian())) { 1272 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1273 } 1274 return 0; 1275} 1276 1277unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1278switch (RetVT.SimpleTy) { 1279 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill); 1280 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill); 1281 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill); 1282 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill); 1283 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill); 1284 default: return 0; 1285} 1286} 1287 1288unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1289 if ((MF->getDataLayout().isBigEndian())) { 1290 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1291 } 1292 return 0; 1293} 1294 1295unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1296 if ((MF->getDataLayout().isBigEndian())) { 1297 return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1298 } 1299 return 0; 1300} 1301 1302unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1303 if ((MF->getDataLayout().isBigEndian())) { 1304 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1305 } 1306 return 0; 1307} 1308 1309unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1310 if ((MF->getDataLayout().isBigEndian())) { 1311 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1312 } 1313 return 0; 1314} 1315 1316unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1317 if ((MF->getDataLayout().isBigEndian())) { 1318 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1319 } 1320 return 0; 1321} 1322 1323unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1324switch (RetVT.SimpleTy) { 1325 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill); 1326 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill); 1327 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill); 1328 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill); 1329 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill); 1330 default: return 0; 1331} 1332} 1333 1334unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1335 if ((MF->getDataLayout().isBigEndian())) { 1336 return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1337 } 1338 return 0; 1339} 1340 1341unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1342 if ((MF->getDataLayout().isBigEndian())) { 1343 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1344 } 1345 return 0; 1346} 1347 1348unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1349 if ((MF->getDataLayout().isBigEndian())) { 1350 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1351 } 1352 return 0; 1353} 1354 1355unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1356 if ((MF->getDataLayout().isBigEndian())) { 1357 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1358 } 1359 return 0; 1360} 1361 1362unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1363 if ((MF->getDataLayout().isBigEndian())) { 1364 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1365 } 1366 return 0; 1367} 1368 1369unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1370switch (RetVT.SimpleTy) { 1371 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill); 1372 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill); 1373 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill); 1374 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill); 1375 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill); 1376 default: return 0; 1377} 1378} 1379 1380unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1381 if ((MF->getDataLayout().isBigEndian())) { 1382 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1383 } 1384 return 0; 1385} 1386 1387unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1388 if ((MF->getDataLayout().isBigEndian())) { 1389 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1390 } 1391 return 0; 1392} 1393 1394unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1395 if ((MF->getDataLayout().isBigEndian())) { 1396 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1397 } 1398 return 0; 1399} 1400 1401unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1402 if ((MF->getDataLayout().isBigEndian())) { 1403 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1404 } 1405 return 0; 1406} 1407 1408unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1409switch (RetVT.SimpleTy) { 1410 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill); 1411 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill); 1412 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill); 1413 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill); 1414 default: return 0; 1415} 1416} 1417 1418unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1419 if ((MF->getDataLayout().isBigEndian())) { 1420 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1421 } 1422 return 0; 1423} 1424 1425unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1426 if ((MF->getDataLayout().isBigEndian())) { 1427 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1428 } 1429 return 0; 1430} 1431 1432unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1433 if ((MF->getDataLayout().isBigEndian())) { 1434 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1435 } 1436 return 0; 1437} 1438 1439unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1440 if ((MF->getDataLayout().isBigEndian())) { 1441 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1442 } 1443 return 0; 1444} 1445 1446unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1447switch (RetVT.SimpleTy) { 1448 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill); 1449 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill); 1450 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill); 1451 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill); 1452 default: return 0; 1453} 1454} 1455 1456unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1457 if ((MF->getDataLayout().isBigEndian())) { 1458 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1459 } 1460 return 0; 1461} 1462 1463unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1464 if ((MF->getDataLayout().isBigEndian())) { 1465 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1466 } 1467 return 0; 1468} 1469 1470unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1471 if ((MF->getDataLayout().isBigEndian())) { 1472 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1473 } 1474 return 0; 1475} 1476 1477unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1478 if ((MF->getDataLayout().isBigEndian())) { 1479 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1480 } 1481 return 0; 1482} 1483 1484unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1485switch (RetVT.SimpleTy) { 1486 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill); 1487 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill); 1488 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill); 1489 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill); 1490 default: return 0; 1491} 1492} 1493 1494unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1495 if ((MF->getDataLayout().isBigEndian())) { 1496 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1497 } 1498 return 0; 1499} 1500 1501unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1502 if ((MF->getDataLayout().isBigEndian())) { 1503 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1504 } 1505 return 0; 1506} 1507 1508unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1509 if ((MF->getDataLayout().isBigEndian())) { 1510 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1511 } 1512 return 0; 1513} 1514 1515unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1516 if ((MF->getDataLayout().isBigEndian())) { 1517 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1518 } 1519 return 0; 1520} 1521 1522unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1523switch (RetVT.SimpleTy) { 1524 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill); 1525 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill); 1526 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill); 1527 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill); 1528 default: return 0; 1529} 1530} 1531 1532unsigned fastEmit_ISD_BITCAST_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1533 if (RetVT.SimpleTy != MVT::f64) 1534 return 0; 1535 if ((MF->getDataLayout().isBigEndian())) { 1536 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1537 } 1538 return 0; 1539} 1540 1541unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1542 if ((MF->getDataLayout().isBigEndian())) { 1543 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1544 } 1545 return 0; 1546} 1547 1548unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1549 if ((MF->getDataLayout().isBigEndian())) { 1550 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1551 } 1552 return 0; 1553} 1554 1555unsigned fastEmit_ISD_BITCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1556switch (RetVT.SimpleTy) { 1557 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(Op0, Op0IsKill); 1558 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(Op0, Op0IsKill); 1559 default: return 0; 1560} 1561} 1562 1563unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1564 if ((MF->getDataLayout().isBigEndian())) { 1565 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1566 } 1567 return 0; 1568} 1569 1570unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1571 if ((MF->getDataLayout().isBigEndian())) { 1572 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1573 } 1574 return 0; 1575} 1576 1577unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1578 if ((MF->getDataLayout().isBigEndian())) { 1579 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1580 } 1581 return 0; 1582} 1583 1584unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1585 if ((MF->getDataLayout().isBigEndian())) { 1586 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1587 } 1588 return 0; 1589} 1590 1591unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1592switch (RetVT.SimpleTy) { 1593 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill); 1594 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill); 1595 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill); 1596 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill); 1597 default: return 0; 1598} 1599} 1600 1601unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1602 if ((MF->getDataLayout().isBigEndian())) { 1603 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1604 } 1605 return 0; 1606} 1607 1608unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1609 if ((MF->getDataLayout().isBigEndian())) { 1610 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1611 } 1612 return 0; 1613} 1614 1615unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1616 if ((MF->getDataLayout().isBigEndian())) { 1617 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1618 } 1619 return 0; 1620} 1621 1622unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1623 if ((MF->getDataLayout().isBigEndian())) { 1624 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1625 } 1626 return 0; 1627} 1628 1629unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1630switch (RetVT.SimpleTy) { 1631 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill); 1632 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill); 1633 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill); 1634 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill); 1635 default: return 0; 1636} 1637} 1638 1639unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1640 if ((MF->getDataLayout().isBigEndian())) { 1641 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1642 } 1643 return 0; 1644} 1645 1646unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1647 if ((MF->getDataLayout().isBigEndian())) { 1648 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1649 } 1650 return 0; 1651} 1652 1653unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1654 if ((MF->getDataLayout().isBigEndian())) { 1655 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1656 } 1657 return 0; 1658} 1659 1660unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 1661 if ((MF->getDataLayout().isBigEndian())) { 1662 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1663 } 1664 return 0; 1665} 1666 1667unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1668 if ((MF->getDataLayout().isBigEndian())) { 1669 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1670 } 1671 return 0; 1672} 1673 1674unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1675switch (RetVT.SimpleTy) { 1676 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill); 1677 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill); 1678 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill); 1679 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill); 1680 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill); 1681 default: return 0; 1682} 1683} 1684 1685unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1686 switch (VT.SimpleTy) { 1687 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill); 1688 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill); 1689 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill); 1690 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1691 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1692 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1693 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1694 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1695 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1696 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 1697 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1698 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 1699 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1700 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1701 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1702 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 1703 default: return 0; 1704 } 1705} 1706 1707// FastEmit functions for ISD::BITREVERSE. 1708 1709unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1710 if (RetVT.SimpleTy != MVT::i32) 1711 return 0; 1712 if ((Subtarget->isThumb2())) { 1713 return fastEmitInst_r(ARM::t2RBIT, &ARM::rGPRRegClass, Op0, Op0IsKill); 1714 } 1715 if ((Subtarget->hasV6T2Ops()) && (!Subtarget->isThumb())) { 1716 return fastEmitInst_r(ARM::RBIT, &ARM::GPRRegClass, Op0, Op0IsKill); 1717 } 1718 return 0; 1719} 1720 1721unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1722 switch (VT.SimpleTy) { 1723 case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill); 1724 default: return 0; 1725 } 1726} 1727 1728// FastEmit functions for ISD::BRIND. 1729 1730unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1731 if (RetVT.SimpleTy != MVT::isVoid) 1732 return 0; 1733 if ((Subtarget->isThumb())) { 1734 return fastEmitInst_r(ARM::tBRIND, &ARM::GPRRegClass, Op0, Op0IsKill); 1735 } 1736 if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) { 1737 return fastEmitInst_r(ARM::MOVPCRX, &ARM::GPRRegClass, Op0, Op0IsKill); 1738 } 1739 if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) { 1740 return fastEmitInst_r(ARM::BX, &ARM::GPRRegClass, Op0, Op0IsKill); 1741 } 1742 return 0; 1743} 1744 1745unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1746 switch (VT.SimpleTy) { 1747 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill); 1748 default: return 0; 1749 } 1750} 1751 1752// FastEmit functions for ISD::BSWAP. 1753 1754unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1755 if (RetVT.SimpleTy != MVT::i32) 1756 return 0; 1757 if ((Subtarget->isThumb2())) { 1758 return fastEmitInst_r(ARM::t2REV, &ARM::rGPRRegClass, Op0, Op0IsKill); 1759 } 1760 if ((Subtarget->hasV6Ops()) && (Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 1761 return fastEmitInst_r(ARM::tREV, &ARM::tGPRRegClass, Op0, Op0IsKill); 1762 } 1763 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 1764 return fastEmitInst_r(ARM::REV, &ARM::GPRRegClass, Op0, Op0IsKill); 1765 } 1766 return 0; 1767} 1768 1769unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1770 switch (VT.SimpleTy) { 1771 case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill); 1772 default: return 0; 1773 } 1774} 1775 1776// FastEmit functions for ISD::CTLZ. 1777 1778unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1779 if (RetVT.SimpleTy != MVT::i32) 1780 return 0; 1781 if ((Subtarget->isThumb2())) { 1782 return fastEmitInst_r(ARM::t2CLZ, &ARM::rGPRRegClass, Op0, Op0IsKill); 1783 } 1784 if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) { 1785 return fastEmitInst_r(ARM::CLZ, &ARM::GPRRegClass, Op0, Op0IsKill); 1786 } 1787 return 0; 1788} 1789 1790unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1791 if (RetVT.SimpleTy != MVT::v8i8) 1792 return 0; 1793 if ((Subtarget->hasNEON())) { 1794 return fastEmitInst_r(ARM::VCLZv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 1795 } 1796 return 0; 1797} 1798 1799unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1800 if (RetVT.SimpleTy != MVT::v16i8) 1801 return 0; 1802 if ((Subtarget->hasNEON())) { 1803 return fastEmitInst_r(ARM::VCLZv16i8, &ARM::QPRRegClass, Op0, Op0IsKill); 1804 } 1805 return 0; 1806} 1807 1808unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1809 if (RetVT.SimpleTy != MVT::v4i16) 1810 return 0; 1811 if ((Subtarget->hasNEON())) { 1812 return fastEmitInst_r(ARM::VCLZv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 1813 } 1814 return 0; 1815} 1816 1817unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1818 if (RetVT.SimpleTy != MVT::v8i16) 1819 return 0; 1820 if ((Subtarget->hasNEON())) { 1821 return fastEmitInst_r(ARM::VCLZv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 1822 } 1823 return 0; 1824} 1825 1826unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1827 if (RetVT.SimpleTy != MVT::v2i32) 1828 return 0; 1829 if ((Subtarget->hasNEON())) { 1830 return fastEmitInst_r(ARM::VCLZv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 1831 } 1832 return 0; 1833} 1834 1835unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1836 if (RetVT.SimpleTy != MVT::v4i32) 1837 return 0; 1838 if ((Subtarget->hasNEON())) { 1839 return fastEmitInst_r(ARM::VCLZv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 1840 } 1841 return 0; 1842} 1843 1844unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1845 switch (VT.SimpleTy) { 1846 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill); 1847 case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1848 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1849 case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1850 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1851 case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1852 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1853 default: return 0; 1854 } 1855} 1856 1857// FastEmit functions for ISD::CTPOP. 1858 1859unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1860 if (RetVT.SimpleTy != MVT::v8i8) 1861 return 0; 1862 if ((Subtarget->hasNEON())) { 1863 return fastEmitInst_r(ARM::VCNTd, &ARM::DPRRegClass, Op0, Op0IsKill); 1864 } 1865 return 0; 1866} 1867 1868unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1869 if (RetVT.SimpleTy != MVT::v16i8) 1870 return 0; 1871 if ((Subtarget->hasNEON())) { 1872 return fastEmitInst_r(ARM::VCNTq, &ARM::QPRRegClass, Op0, Op0IsKill); 1873 } 1874 return 0; 1875} 1876 1877unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1878 switch (VT.SimpleTy) { 1879 case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1880 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1881 default: return 0; 1882 } 1883} 1884 1885// FastEmit functions for ISD::FABS. 1886 1887unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1888 if (RetVT.SimpleTy != MVT::f32) 1889 return 0; 1890 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) { 1891 return fastEmitInst_r(ARM::VABSS, &ARM::SPRRegClass, Op0, Op0IsKill); 1892 } 1893 return 0; 1894} 1895 1896unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1897 if (RetVT.SimpleTy != MVT::f64) 1898 return 0; 1899 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) { 1900 return fastEmitInst_r(ARM::VABSD, &ARM::DPRRegClass, Op0, Op0IsKill); 1901 } 1902 return 0; 1903} 1904 1905unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1906 if (RetVT.SimpleTy != MVT::v4f16) 1907 return 0; 1908 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 1909 return fastEmitInst_r(ARM::VABShd, &ARM::DPRRegClass, Op0, Op0IsKill); 1910 } 1911 return 0; 1912} 1913 1914unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1915 if (RetVT.SimpleTy != MVT::v8f16) 1916 return 0; 1917 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 1918 return fastEmitInst_r(ARM::VABShq, &ARM::QPRRegClass, Op0, Op0IsKill); 1919 } 1920 return 0; 1921} 1922 1923unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1924 if (RetVT.SimpleTy != MVT::v2f32) 1925 return 0; 1926 if ((Subtarget->hasNEON())) { 1927 return fastEmitInst_r(ARM::VABSfd, &ARM::DPRRegClass, Op0, Op0IsKill); 1928 } 1929 return 0; 1930} 1931 1932unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1933 if (RetVT.SimpleTy != MVT::v4f32) 1934 return 0; 1935 if ((Subtarget->hasNEON())) { 1936 return fastEmitInst_r(ARM::VABSfq, &ARM::QPRRegClass, Op0, Op0IsKill); 1937 } 1938 return 0; 1939} 1940 1941unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1942 switch (VT.SimpleTy) { 1943 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill); 1944 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill); 1945 case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 1946 case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1947 case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1948 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1949 default: return 0; 1950 } 1951} 1952 1953// FastEmit functions for ISD::FCEIL. 1954 1955unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1956 if (RetVT.SimpleTy != MVT::f32) 1957 return 0; 1958 if ((Subtarget->hasFPARMv8())) { 1959 return fastEmitInst_r(ARM::VRINTPS, &ARM::SPRRegClass, Op0, Op0IsKill); 1960 } 1961 return 0; 1962} 1963 1964unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1965 if (RetVT.SimpleTy != MVT::f64) 1966 return 0; 1967 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) { 1968 return fastEmitInst_r(ARM::VRINTPD, &ARM::DPRRegClass, Op0, Op0IsKill); 1969 } 1970 return 0; 1971} 1972 1973unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1974 switch (VT.SimpleTy) { 1975 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill); 1976 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill); 1977 default: return 0; 1978 } 1979} 1980 1981// FastEmit functions for ISD::FFLOOR. 1982 1983unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1984 if (RetVT.SimpleTy != MVT::f32) 1985 return 0; 1986 if ((Subtarget->hasFPARMv8())) { 1987 return fastEmitInst_r(ARM::VRINTMS, &ARM::SPRRegClass, Op0, Op0IsKill); 1988 } 1989 return 0; 1990} 1991 1992unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1993 if (RetVT.SimpleTy != MVT::f64) 1994 return 0; 1995 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) { 1996 return fastEmitInst_r(ARM::VRINTMD, &ARM::DPRRegClass, Op0, Op0IsKill); 1997 } 1998 return 0; 1999} 2000 2001unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2002 switch (VT.SimpleTy) { 2003 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill); 2004 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill); 2005 default: return 0; 2006 } 2007} 2008 2009// FastEmit functions for ISD::FNEARBYINT. 2010 2011unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2012 if (RetVT.SimpleTy != MVT::f32) 2013 return 0; 2014 if ((Subtarget->hasFPARMv8())) { 2015 return fastEmitInst_r(ARM::VRINTRS, &ARM::SPRRegClass, Op0, Op0IsKill); 2016 } 2017 return 0; 2018} 2019 2020unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2021 if (RetVT.SimpleTy != MVT::f64) 2022 return 0; 2023 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) { 2024 return fastEmitInst_r(ARM::VRINTRD, &ARM::DPRRegClass, Op0, Op0IsKill); 2025 } 2026 return 0; 2027} 2028 2029unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2030 switch (VT.SimpleTy) { 2031 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 2032 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 2033 default: return 0; 2034 } 2035} 2036 2037// FastEmit functions for ISD::FNEG. 2038 2039unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2040 if (RetVT.SimpleTy != MVT::f16) 2041 return 0; 2042 if ((Subtarget->hasFullFP16())) { 2043 return fastEmitInst_r(ARM::VNEGH, &ARM::HPRRegClass, Op0, Op0IsKill); 2044 } 2045 return 0; 2046} 2047 2048unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2049 if (RetVT.SimpleTy != MVT::f32) 2050 return 0; 2051 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) { 2052 return fastEmitInst_r(ARM::VNEGS, &ARM::SPRRegClass, Op0, Op0IsKill); 2053 } 2054 return 0; 2055} 2056 2057unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2058 if (RetVT.SimpleTy != MVT::f64) 2059 return 0; 2060 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) { 2061 return fastEmitInst_r(ARM::VNEGD, &ARM::DPRRegClass, Op0, Op0IsKill); 2062 } 2063 return 0; 2064} 2065 2066unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2067 if (RetVT.SimpleTy != MVT::v4f16) 2068 return 0; 2069 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2070 return fastEmitInst_r(ARM::VNEGhd, &ARM::DPRRegClass, Op0, Op0IsKill); 2071 } 2072 return 0; 2073} 2074 2075unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2076 if (RetVT.SimpleTy != MVT::v8f16) 2077 return 0; 2078 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2079 return fastEmitInst_r(ARM::VNEGhq, &ARM::QPRRegClass, Op0, Op0IsKill); 2080 } 2081 return 0; 2082} 2083 2084unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2085 if (RetVT.SimpleTy != MVT::v2f32) 2086 return 0; 2087 if ((Subtarget->hasNEON())) { 2088 return fastEmitInst_r(ARM::VNEGfd, &ARM::DPRRegClass, Op0, Op0IsKill); 2089 } 2090 return 0; 2091} 2092 2093unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2094 if (RetVT.SimpleTy != MVT::v4f32) 2095 return 0; 2096 if ((Subtarget->hasNEON())) { 2097 return fastEmitInst_r(ARM::VNEGf32q, &ARM::QPRRegClass, Op0, Op0IsKill); 2098 } 2099 return 0; 2100} 2101 2102unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2103 switch (VT.SimpleTy) { 2104 case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0, Op0IsKill); 2105 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill); 2106 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill); 2107 case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2108 case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2109 case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2110 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2111 default: return 0; 2112 } 2113} 2114 2115// FastEmit functions for ISD::FP_EXTEND. 2116 2117unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2118 if (RetVT.SimpleTy != MVT::f64) 2119 return 0; 2120 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) { 2121 return fastEmitInst_r(ARM::VCVTDS, &ARM::DPRRegClass, Op0, Op0IsKill); 2122 } 2123 return 0; 2124} 2125 2126unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2127 switch (VT.SimpleTy) { 2128 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill); 2129 default: return 0; 2130 } 2131} 2132 2133// FastEmit functions for ISD::FP_ROUND. 2134 2135unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2136 if (RetVT.SimpleTy != MVT::f32) 2137 return 0; 2138 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) { 2139 return fastEmitInst_r(ARM::VCVTSD, &ARM::SPRRegClass, Op0, Op0IsKill); 2140 } 2141 return 0; 2142} 2143 2144unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2145 switch (VT.SimpleTy) { 2146 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 2147 default: return 0; 2148 } 2149} 2150 2151// FastEmit functions for ISD::FP_TO_SINT. 2152 2153unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2154 if (RetVT.SimpleTy != MVT::v4i16) 2155 return 0; 2156 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2157 return fastEmitInst_r(ARM::VCVTh2sd, &ARM::DPRRegClass, Op0, Op0IsKill); 2158 } 2159 return 0; 2160} 2161 2162unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2163 if (RetVT.SimpleTy != MVT::v8i16) 2164 return 0; 2165 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2166 return fastEmitInst_r(ARM::VCVTh2sq, &ARM::QPRRegClass, Op0, Op0IsKill); 2167 } 2168 return 0; 2169} 2170 2171unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2172 if (RetVT.SimpleTy != MVT::v2i32) 2173 return 0; 2174 if ((Subtarget->hasNEON())) { 2175 return fastEmitInst_r(ARM::VCVTf2sd, &ARM::DPRRegClass, Op0, Op0IsKill); 2176 } 2177 return 0; 2178} 2179 2180unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2181 if (RetVT.SimpleTy != MVT::v4i32) 2182 return 0; 2183 if ((Subtarget->hasNEON())) { 2184 return fastEmitInst_r(ARM::VCVTf2sq, &ARM::QPRRegClass, Op0, Op0IsKill); 2185 } 2186 return 0; 2187} 2188 2189unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2190 switch (VT.SimpleTy) { 2191 case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2192 case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2193 case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2194 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2195 default: return 0; 2196 } 2197} 2198 2199// FastEmit functions for ISD::FP_TO_UINT. 2200 2201unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2202 if (RetVT.SimpleTy != MVT::v4i16) 2203 return 0; 2204 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2205 return fastEmitInst_r(ARM::VCVTh2ud, &ARM::DPRRegClass, Op0, Op0IsKill); 2206 } 2207 return 0; 2208} 2209 2210unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2211 if (RetVT.SimpleTy != MVT::v8i16) 2212 return 0; 2213 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2214 return fastEmitInst_r(ARM::VCVTh2uq, &ARM::QPRRegClass, Op0, Op0IsKill); 2215 } 2216 return 0; 2217} 2218 2219unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2220 if (RetVT.SimpleTy != MVT::v2i32) 2221 return 0; 2222 if ((Subtarget->hasNEON())) { 2223 return fastEmitInst_r(ARM::VCVTf2ud, &ARM::DPRRegClass, Op0, Op0IsKill); 2224 } 2225 return 0; 2226} 2227 2228unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2229 if (RetVT.SimpleTy != MVT::v4i32) 2230 return 0; 2231 if ((Subtarget->hasNEON())) { 2232 return fastEmitInst_r(ARM::VCVTf2uq, &ARM::QPRRegClass, Op0, Op0IsKill); 2233 } 2234 return 0; 2235} 2236 2237unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2238 switch (VT.SimpleTy) { 2239 case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2240 case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2241 case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2242 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2243 default: return 0; 2244 } 2245} 2246 2247// FastEmit functions for ISD::FRINT. 2248 2249unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2250 if (RetVT.SimpleTy != MVT::f32) 2251 return 0; 2252 if ((Subtarget->hasFPARMv8())) { 2253 return fastEmitInst_r(ARM::VRINTXS, &ARM::SPRRegClass, Op0, Op0IsKill); 2254 } 2255 return 0; 2256} 2257 2258unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2259 if (RetVT.SimpleTy != MVT::f64) 2260 return 0; 2261 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) { 2262 return fastEmitInst_r(ARM::VRINTXD, &ARM::DPRRegClass, Op0, Op0IsKill); 2263 } 2264 return 0; 2265} 2266 2267unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2268 switch (VT.SimpleTy) { 2269 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 2270 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 2271 default: return 0; 2272 } 2273} 2274 2275// FastEmit functions for ISD::FROUND. 2276 2277unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2278 if (RetVT.SimpleTy != MVT::f32) 2279 return 0; 2280 if ((Subtarget->hasFPARMv8())) { 2281 return fastEmitInst_r(ARM::VRINTAS, &ARM::SPRRegClass, Op0, Op0IsKill); 2282 } 2283 return 0; 2284} 2285 2286unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2287 if (RetVT.SimpleTy != MVT::f64) 2288 return 0; 2289 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) { 2290 return fastEmitInst_r(ARM::VRINTAD, &ARM::DPRRegClass, Op0, Op0IsKill); 2291 } 2292 return 0; 2293} 2294 2295unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2296 switch (VT.SimpleTy) { 2297 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 2298 case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 2299 default: return 0; 2300 } 2301} 2302 2303// FastEmit functions for ISD::FSQRT. 2304 2305unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2306 if (RetVT.SimpleTy != MVT::f32) 2307 return 0; 2308 if ((Subtarget->hasVFP2())) { 2309 return fastEmitInst_r(ARM::VSQRTS, &ARM::SPRRegClass, Op0, Op0IsKill); 2310 } 2311 return 0; 2312} 2313 2314unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2315 if (RetVT.SimpleTy != MVT::f64) 2316 return 0; 2317 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) { 2318 return fastEmitInst_r(ARM::VSQRTD, &ARM::DPRRegClass, Op0, Op0IsKill); 2319 } 2320 return 0; 2321} 2322 2323unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2324 switch (VT.SimpleTy) { 2325 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill); 2326 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill); 2327 default: return 0; 2328 } 2329} 2330 2331// FastEmit functions for ISD::FTRUNC. 2332 2333unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2334 if (RetVT.SimpleTy != MVT::f32) 2335 return 0; 2336 if ((Subtarget->hasFPARMv8())) { 2337 return fastEmitInst_r(ARM::VRINTZS, &ARM::SPRRegClass, Op0, Op0IsKill); 2338 } 2339 return 0; 2340} 2341 2342unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2343 if (RetVT.SimpleTy != MVT::f64) 2344 return 0; 2345 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) { 2346 return fastEmitInst_r(ARM::VRINTZD, &ARM::DPRRegClass, Op0, Op0IsKill); 2347 } 2348 return 0; 2349} 2350 2351unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2352 switch (VT.SimpleTy) { 2353 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill); 2354 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill); 2355 default: return 0; 2356 } 2357} 2358 2359// FastEmit functions for ISD::SIGN_EXTEND. 2360 2361unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2362 if (RetVT.SimpleTy != MVT::v8i16) 2363 return 0; 2364 if ((Subtarget->hasNEON())) { 2365 return fastEmitInst_r(ARM::VMOVLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 2366 } 2367 return 0; 2368} 2369 2370unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2371 if (RetVT.SimpleTy != MVT::v4i32) 2372 return 0; 2373 if ((Subtarget->hasNEON())) { 2374 return fastEmitInst_r(ARM::VMOVLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 2375 } 2376 return 0; 2377} 2378 2379unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2380 if (RetVT.SimpleTy != MVT::v2i64) 2381 return 0; 2382 if ((Subtarget->hasNEON())) { 2383 return fastEmitInst_r(ARM::VMOVLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill); 2384 } 2385 return 0; 2386} 2387 2388unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2389 switch (VT.SimpleTy) { 2390 case MVT::v8i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2391 case MVT::v4i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2392 case MVT::v2i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2393 default: return 0; 2394 } 2395} 2396 2397// FastEmit functions for ISD::SINT_TO_FP. 2398 2399unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2400 if (RetVT.SimpleTy != MVT::v4f16) 2401 return 0; 2402 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2403 return fastEmitInst_r(ARM::VCVTs2hd, &ARM::DPRRegClass, Op0, Op0IsKill); 2404 } 2405 return 0; 2406} 2407 2408unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2409 if (RetVT.SimpleTy != MVT::v8f16) 2410 return 0; 2411 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2412 return fastEmitInst_r(ARM::VCVTs2hq, &ARM::QPRRegClass, Op0, Op0IsKill); 2413 } 2414 return 0; 2415} 2416 2417unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2418 if (RetVT.SimpleTy != MVT::v2f32) 2419 return 0; 2420 if ((Subtarget->hasNEON())) { 2421 return fastEmitInst_r(ARM::VCVTs2fd, &ARM::DPRRegClass, Op0, Op0IsKill); 2422 } 2423 return 0; 2424} 2425 2426unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2427 if (RetVT.SimpleTy != MVT::v4f32) 2428 return 0; 2429 if ((Subtarget->hasNEON())) { 2430 return fastEmitInst_r(ARM::VCVTs2fq, &ARM::QPRRegClass, Op0, Op0IsKill); 2431 } 2432 return 0; 2433} 2434 2435unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2436 switch (VT.SimpleTy) { 2437 case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2438 case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2439 case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2440 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2441 default: return 0; 2442 } 2443} 2444 2445// FastEmit functions for ISD::TRUNCATE. 2446 2447unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2448 if (RetVT.SimpleTy != MVT::v8i8) 2449 return 0; 2450 if ((Subtarget->hasNEON())) { 2451 return fastEmitInst_r(ARM::VMOVNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 2452 } 2453 return 0; 2454} 2455 2456unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2457 if (RetVT.SimpleTy != MVT::v4i16) 2458 return 0; 2459 if ((Subtarget->hasNEON())) { 2460 return fastEmitInst_r(ARM::VMOVNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 2461 } 2462 return 0; 2463} 2464 2465unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2466 if (RetVT.SimpleTy != MVT::v2i32) 2467 return 0; 2468 if ((Subtarget->hasNEON())) { 2469 return fastEmitInst_r(ARM::VMOVNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 2470 } 2471 return 0; 2472} 2473 2474unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2475 switch (VT.SimpleTy) { 2476 case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2477 case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2478 case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 2479 default: return 0; 2480 } 2481} 2482 2483// FastEmit functions for ISD::UINT_TO_FP. 2484 2485unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2486 if (RetVT.SimpleTy != MVT::v4f16) 2487 return 0; 2488 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2489 return fastEmitInst_r(ARM::VCVTu2hd, &ARM::DPRRegClass, Op0, Op0IsKill); 2490 } 2491 return 0; 2492} 2493 2494unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2495 if (RetVT.SimpleTy != MVT::v8f16) 2496 return 0; 2497 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2498 return fastEmitInst_r(ARM::VCVTu2hq, &ARM::QPRRegClass, Op0, Op0IsKill); 2499 } 2500 return 0; 2501} 2502 2503unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2504 if (RetVT.SimpleTy != MVT::v2f32) 2505 return 0; 2506 if ((Subtarget->hasNEON())) { 2507 return fastEmitInst_r(ARM::VCVTu2fd, &ARM::DPRRegClass, Op0, Op0IsKill); 2508 } 2509 return 0; 2510} 2511 2512unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2513 if (RetVT.SimpleTy != MVT::v4f32) 2514 return 0; 2515 if ((Subtarget->hasNEON())) { 2516 return fastEmitInst_r(ARM::VCVTu2fq, &ARM::QPRRegClass, Op0, Op0IsKill); 2517 } 2518 return 0; 2519} 2520 2521unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2522 switch (VT.SimpleTy) { 2523 case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2524 case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2525 case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2526 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2527 default: return 0; 2528 } 2529} 2530 2531// FastEmit functions for ISD::ZERO_EXTEND. 2532 2533unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2534 if (RetVT.SimpleTy != MVT::v8i16) 2535 return 0; 2536 if ((Subtarget->hasNEON())) { 2537 return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 2538 } 2539 return 0; 2540} 2541 2542unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2543 if (RetVT.SimpleTy != MVT::v4i32) 2544 return 0; 2545 if ((Subtarget->hasNEON())) { 2546 return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 2547 } 2548 return 0; 2549} 2550 2551unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2552 if (RetVT.SimpleTy != MVT::v2i64) 2553 return 0; 2554 if ((Subtarget->hasNEON())) { 2555 return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill); 2556 } 2557 return 0; 2558} 2559 2560unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2561 switch (VT.SimpleTy) { 2562 case MVT::v8i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2563 case MVT::v4i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2564 case MVT::v2i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2565 default: return 0; 2566 } 2567} 2568 2569// Top-level FastEmit function. 2570 2571unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override { 2572 switch (Opcode) { 2573 case ARMISD::CALL: return fastEmit_ARMISD_CALL_r(VT, RetVT, Op0, Op0IsKill); 2574 case ARMISD::CALL_NOLINK: return fastEmit_ARMISD_CALL_NOLINK_r(VT, RetVT, Op0, Op0IsKill); 2575 case ARMISD::CALL_PRED: return fastEmit_ARMISD_CALL_PRED_r(VT, RetVT, Op0, Op0IsKill); 2576 case ARMISD::RRX: return fastEmit_ARMISD_RRX_r(VT, RetVT, Op0, Op0IsKill); 2577 case ARMISD::SRA_FLAG: return fastEmit_ARMISD_SRA_FLAG_r(VT, RetVT, Op0, Op0IsKill); 2578 case ARMISD::SRL_FLAG: return fastEmit_ARMISD_SRL_FLAG_r(VT, RetVT, Op0, Op0IsKill); 2579 case ARMISD::TC_RETURN: return fastEmit_ARMISD_TC_RETURN_r(VT, RetVT, Op0, Op0IsKill); 2580 case ARMISD::VCEQZ: return fastEmit_ARMISD_VCEQZ_r(VT, RetVT, Op0, Op0IsKill); 2581 case ARMISD::VCGEZ: return fastEmit_ARMISD_VCGEZ_r(VT, RetVT, Op0, Op0IsKill); 2582 case ARMISD::VCGTZ: return fastEmit_ARMISD_VCGTZ_r(VT, RetVT, Op0, Op0IsKill); 2583 case ARMISD::VCLEZ: return fastEmit_ARMISD_VCLEZ_r(VT, RetVT, Op0, Op0IsKill); 2584 case ARMISD::VCLTZ: return fastEmit_ARMISD_VCLTZ_r(VT, RetVT, Op0, Op0IsKill); 2585 case ARMISD::VDUP: return fastEmit_ARMISD_VDUP_r(VT, RetVT, Op0, Op0IsKill); 2586 case ARMISD::VMOVSR: return fastEmit_ARMISD_VMOVSR_r(VT, RetVT, Op0, Op0IsKill); 2587 case ARMISD::VMOVhr: return fastEmit_ARMISD_VMOVhr_r(VT, RetVT, Op0, Op0IsKill); 2588 case ARMISD::VMOVrh: return fastEmit_ARMISD_VMOVrh_r(VT, RetVT, Op0, Op0IsKill); 2589 case ARMISD::VREV16: return fastEmit_ARMISD_VREV16_r(VT, RetVT, Op0, Op0IsKill); 2590 case ARMISD::VREV32: return fastEmit_ARMISD_VREV32_r(VT, RetVT, Op0, Op0IsKill); 2591 case ARMISD::VREV64: return fastEmit_ARMISD_VREV64_r(VT, RetVT, Op0, Op0IsKill); 2592 case ARMISD::WIN__DBZCHK: return fastEmit_ARMISD_WIN__DBZCHK_r(VT, RetVT, Op0, Op0IsKill); 2593 case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill); 2594 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 2595 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill); 2596 case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill); 2597 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill); 2598 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill); 2599 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill); 2600 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill); 2601 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill); 2602 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill); 2603 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill); 2604 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill); 2605 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill); 2606 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 2607 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill); 2608 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill); 2609 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill); 2610 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill); 2611 case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill); 2612 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill); 2613 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill); 2614 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 2615 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 2616 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill); 2617 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 2618 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 2619 default: return 0; 2620 } 2621} 2622 2623// FastEmit functions for ARMISD::CMP. 2624 2625unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2626 if (RetVT.SimpleTy != MVT::isVoid) 2627 return 0; 2628 if ((Subtarget->isThumb2())) { 2629 return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2630 } 2631 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 2632 return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2633 } 2634 if ((!Subtarget->isThumb())) { 2635 return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2636 } 2637 return 0; 2638} 2639 2640unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2641 switch (VT.SimpleTy) { 2642 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2643 default: return 0; 2644 } 2645} 2646 2647// FastEmit functions for ARMISD::CMPZ. 2648 2649unsigned fastEmit_ARMISD_CMPZ_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2650 if (RetVT.SimpleTy != MVT::isVoid) 2651 return 0; 2652 if ((Subtarget->isThumb2())) { 2653 return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2654 } 2655 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 2656 return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2657 } 2658 if ((!Subtarget->isThumb())) { 2659 return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2660 } 2661 return 0; 2662} 2663 2664unsigned fastEmit_ARMISD_CMPZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2665 switch (VT.SimpleTy) { 2666 case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2667 default: return 0; 2668 } 2669} 2670 2671// FastEmit functions for ARMISD::EH_SJLJ_LONGJMP. 2672 2673unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2674 if (RetVT.SimpleTy != MVT::isVoid) 2675 return 0; 2676 if ((Subtarget->isThumb()) && (Subtarget->isTargetWindows())) { 2677 return fastEmitInst_rr(ARM::tInt_WIN_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2678 } 2679 if ((!Subtarget->isTargetWindows()) && (Subtarget->isThumb())) { 2680 return fastEmitInst_rr(ARM::tInt_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2681 } 2682 if ((!Subtarget->isThumb())) { 2683 return fastEmitInst_rr(ARM::Int_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2684 } 2685 return 0; 2686} 2687 2688unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2689 switch (VT.SimpleTy) { 2690 case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2691 default: return 0; 2692 } 2693} 2694 2695// FastEmit functions for ARMISD::EH_SJLJ_SETJMP. 2696 2697unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2698 if (RetVT.SimpleTy != MVT::i32) 2699 return 0; 2700 if ((Subtarget->isThumb2()) && (!Subtarget->hasVFP2())) { 2701 return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp_nofp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2702 } 2703 if ((Subtarget->hasVFP2()) && (Subtarget->isThumb2())) { 2704 return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2705 } 2706 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 2707 return fastEmitInst_rr(ARM::tInt_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2708 } 2709 if ((!Subtarget->isThumb()) && (!Subtarget->hasVFP2())) { 2710 return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp_nofp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2711 } 2712 if ((Subtarget->hasVFP2()) && (!Subtarget->isThumb())) { 2713 return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2714 } 2715 return 0; 2716} 2717 2718unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2719 switch (VT.SimpleTy) { 2720 case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2721 default: return 0; 2722 } 2723} 2724 2725// FastEmit functions for ARMISD::SMULWB. 2726 2727unsigned fastEmit_ARMISD_SMULWB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2728 if (RetVT.SimpleTy != MVT::i32) 2729 return 0; 2730 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 2731 return fastEmitInst_rr(ARM::t2SMULWB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2732 } 2733 if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) { 2734 return fastEmitInst_rr(ARM::SMULWB, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2735 } 2736 return 0; 2737} 2738 2739unsigned fastEmit_ARMISD_SMULWB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2740 switch (VT.SimpleTy) { 2741 case MVT::i32: return fastEmit_ARMISD_SMULWB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2742 default: return 0; 2743 } 2744} 2745 2746// FastEmit functions for ARMISD::SMULWT. 2747 2748unsigned fastEmit_ARMISD_SMULWT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2749 if (RetVT.SimpleTy != MVT::i32) 2750 return 0; 2751 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 2752 return fastEmitInst_rr(ARM::t2SMULWT, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2753 } 2754 if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) { 2755 return fastEmitInst_rr(ARM::SMULWT, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2756 } 2757 return 0; 2758} 2759 2760unsigned fastEmit_ARMISD_SMULWT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2761 switch (VT.SimpleTy) { 2762 case MVT::i32: return fastEmit_ARMISD_SMULWT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2763 default: return 0; 2764 } 2765} 2766 2767// FastEmit functions for ARMISD::VCEQ. 2768 2769unsigned fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2770 if (RetVT.SimpleTy != MVT::v8i8) 2771 return 0; 2772 if ((Subtarget->hasNEON())) { 2773 return fastEmitInst_rr(ARM::VCEQv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2774 } 2775 return 0; 2776} 2777 2778unsigned fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2779 if (RetVT.SimpleTy != MVT::v16i8) 2780 return 0; 2781 if ((Subtarget->hasNEON())) { 2782 return fastEmitInst_rr(ARM::VCEQv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2783 } 2784 return 0; 2785} 2786 2787unsigned fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2788 if (RetVT.SimpleTy != MVT::v4i16) 2789 return 0; 2790 if ((Subtarget->hasNEON())) { 2791 return fastEmitInst_rr(ARM::VCEQv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2792 } 2793 return 0; 2794} 2795 2796unsigned fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2797 if (RetVT.SimpleTy != MVT::v8i16) 2798 return 0; 2799 if ((Subtarget->hasNEON())) { 2800 return fastEmitInst_rr(ARM::VCEQv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2801 } 2802 return 0; 2803} 2804 2805unsigned fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2806 if (RetVT.SimpleTy != MVT::v2i32) 2807 return 0; 2808 if ((Subtarget->hasNEON())) { 2809 return fastEmitInst_rr(ARM::VCEQv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2810 } 2811 return 0; 2812} 2813 2814unsigned fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2815 if (RetVT.SimpleTy != MVT::v4i32) 2816 return 0; 2817 if ((Subtarget->hasNEON())) { 2818 return fastEmitInst_rr(ARM::VCEQv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2819 } 2820 return 0; 2821} 2822 2823unsigned fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2824 if (RetVT.SimpleTy != MVT::v4i16) 2825 return 0; 2826 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2827 return fastEmitInst_rr(ARM::VCEQhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2828 } 2829 return 0; 2830} 2831 2832unsigned fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2833 if (RetVT.SimpleTy != MVT::v8i16) 2834 return 0; 2835 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2836 return fastEmitInst_rr(ARM::VCEQhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2837 } 2838 return 0; 2839} 2840 2841unsigned fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2842 if (RetVT.SimpleTy != MVT::v2i32) 2843 return 0; 2844 if ((Subtarget->hasNEON())) { 2845 return fastEmitInst_rr(ARM::VCEQfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2846 } 2847 return 0; 2848} 2849 2850unsigned fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2851 if (RetVT.SimpleTy != MVT::v4i32) 2852 return 0; 2853 if ((Subtarget->hasNEON())) { 2854 return fastEmitInst_rr(ARM::VCEQfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2855 } 2856 return 0; 2857} 2858 2859unsigned fastEmit_ARMISD_VCEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2860 switch (VT.SimpleTy) { 2861 case MVT::v8i8: return fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2862 case MVT::v16i8: return fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2863 case MVT::v4i16: return fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2864 case MVT::v8i16: return fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2865 case MVT::v2i32: return fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2866 case MVT::v4i32: return fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2867 case MVT::v4f16: return fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2868 case MVT::v8f16: return fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2869 case MVT::v2f32: return fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2870 case MVT::v4f32: return fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2871 default: return 0; 2872 } 2873} 2874 2875// FastEmit functions for ARMISD::VCGE. 2876 2877unsigned fastEmit_ARMISD_VCGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2878 if (RetVT.SimpleTy != MVT::v8i8) 2879 return 0; 2880 if ((Subtarget->hasNEON())) { 2881 return fastEmitInst_rr(ARM::VCGEsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2882 } 2883 return 0; 2884} 2885 2886unsigned fastEmit_ARMISD_VCGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2887 if (RetVT.SimpleTy != MVT::v16i8) 2888 return 0; 2889 if ((Subtarget->hasNEON())) { 2890 return fastEmitInst_rr(ARM::VCGEsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2891 } 2892 return 0; 2893} 2894 2895unsigned fastEmit_ARMISD_VCGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2896 if (RetVT.SimpleTy != MVT::v4i16) 2897 return 0; 2898 if ((Subtarget->hasNEON())) { 2899 return fastEmitInst_rr(ARM::VCGEsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2900 } 2901 return 0; 2902} 2903 2904unsigned fastEmit_ARMISD_VCGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2905 if (RetVT.SimpleTy != MVT::v8i16) 2906 return 0; 2907 if ((Subtarget->hasNEON())) { 2908 return fastEmitInst_rr(ARM::VCGEsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2909 } 2910 return 0; 2911} 2912 2913unsigned fastEmit_ARMISD_VCGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2914 if (RetVT.SimpleTy != MVT::v2i32) 2915 return 0; 2916 if ((Subtarget->hasNEON())) { 2917 return fastEmitInst_rr(ARM::VCGEsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2918 } 2919 return 0; 2920} 2921 2922unsigned fastEmit_ARMISD_VCGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2923 if (RetVT.SimpleTy != MVT::v4i32) 2924 return 0; 2925 if ((Subtarget->hasNEON())) { 2926 return fastEmitInst_rr(ARM::VCGEsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2927 } 2928 return 0; 2929} 2930 2931unsigned fastEmit_ARMISD_VCGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2932 if (RetVT.SimpleTy != MVT::v4i16) 2933 return 0; 2934 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2935 return fastEmitInst_rr(ARM::VCGEhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2936 } 2937 return 0; 2938} 2939 2940unsigned fastEmit_ARMISD_VCGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2941 if (RetVT.SimpleTy != MVT::v8i16) 2942 return 0; 2943 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2944 return fastEmitInst_rr(ARM::VCGEhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2945 } 2946 return 0; 2947} 2948 2949unsigned fastEmit_ARMISD_VCGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2950 if (RetVT.SimpleTy != MVT::v2i32) 2951 return 0; 2952 if ((Subtarget->hasNEON())) { 2953 return fastEmitInst_rr(ARM::VCGEfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2954 } 2955 return 0; 2956} 2957 2958unsigned fastEmit_ARMISD_VCGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2959 if (RetVT.SimpleTy != MVT::v4i32) 2960 return 0; 2961 if ((Subtarget->hasNEON())) { 2962 return fastEmitInst_rr(ARM::VCGEfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2963 } 2964 return 0; 2965} 2966 2967unsigned fastEmit_ARMISD_VCGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2968 switch (VT.SimpleTy) { 2969 case MVT::v8i8: return fastEmit_ARMISD_VCGE_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2970 case MVT::v16i8: return fastEmit_ARMISD_VCGE_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2971 case MVT::v4i16: return fastEmit_ARMISD_VCGE_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2972 case MVT::v8i16: return fastEmit_ARMISD_VCGE_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2973 case MVT::v2i32: return fastEmit_ARMISD_VCGE_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2974 case MVT::v4i32: return fastEmit_ARMISD_VCGE_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2975 case MVT::v4f16: return fastEmit_ARMISD_VCGE_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2976 case MVT::v8f16: return fastEmit_ARMISD_VCGE_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2977 case MVT::v2f32: return fastEmit_ARMISD_VCGE_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2978 case MVT::v4f32: return fastEmit_ARMISD_VCGE_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2979 default: return 0; 2980 } 2981} 2982 2983// FastEmit functions for ARMISD::VCGEU. 2984 2985unsigned fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2986 if (RetVT.SimpleTy != MVT::v8i8) 2987 return 0; 2988 if ((Subtarget->hasNEON())) { 2989 return fastEmitInst_rr(ARM::VCGEuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2990 } 2991 return 0; 2992} 2993 2994unsigned fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2995 if (RetVT.SimpleTy != MVT::v16i8) 2996 return 0; 2997 if ((Subtarget->hasNEON())) { 2998 return fastEmitInst_rr(ARM::VCGEuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2999 } 3000 return 0; 3001} 3002 3003unsigned fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3004 if (RetVT.SimpleTy != MVT::v4i16) 3005 return 0; 3006 if ((Subtarget->hasNEON())) { 3007 return fastEmitInst_rr(ARM::VCGEuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3008 } 3009 return 0; 3010} 3011 3012unsigned fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3013 if (RetVT.SimpleTy != MVT::v8i16) 3014 return 0; 3015 if ((Subtarget->hasNEON())) { 3016 return fastEmitInst_rr(ARM::VCGEuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3017 } 3018 return 0; 3019} 3020 3021unsigned fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3022 if (RetVT.SimpleTy != MVT::v2i32) 3023 return 0; 3024 if ((Subtarget->hasNEON())) { 3025 return fastEmitInst_rr(ARM::VCGEuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3026 } 3027 return 0; 3028} 3029 3030unsigned fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3031 if (RetVT.SimpleTy != MVT::v4i32) 3032 return 0; 3033 if ((Subtarget->hasNEON())) { 3034 return fastEmitInst_rr(ARM::VCGEuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3035 } 3036 return 0; 3037} 3038 3039unsigned fastEmit_ARMISD_VCGEU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3040 switch (VT.SimpleTy) { 3041 case MVT::v8i8: return fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3042 case MVT::v16i8: return fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3043 case MVT::v4i16: return fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3044 case MVT::v8i16: return fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3045 case MVT::v2i32: return fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3046 case MVT::v4i32: return fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3047 default: return 0; 3048 } 3049} 3050 3051// FastEmit functions for ARMISD::VCGT. 3052 3053unsigned fastEmit_ARMISD_VCGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3054 if (RetVT.SimpleTy != MVT::v8i8) 3055 return 0; 3056 if ((Subtarget->hasNEON())) { 3057 return fastEmitInst_rr(ARM::VCGTsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3058 } 3059 return 0; 3060} 3061 3062unsigned fastEmit_ARMISD_VCGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3063 if (RetVT.SimpleTy != MVT::v16i8) 3064 return 0; 3065 if ((Subtarget->hasNEON())) { 3066 return fastEmitInst_rr(ARM::VCGTsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3067 } 3068 return 0; 3069} 3070 3071unsigned fastEmit_ARMISD_VCGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3072 if (RetVT.SimpleTy != MVT::v4i16) 3073 return 0; 3074 if ((Subtarget->hasNEON())) { 3075 return fastEmitInst_rr(ARM::VCGTsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3076 } 3077 return 0; 3078} 3079 3080unsigned fastEmit_ARMISD_VCGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3081 if (RetVT.SimpleTy != MVT::v8i16) 3082 return 0; 3083 if ((Subtarget->hasNEON())) { 3084 return fastEmitInst_rr(ARM::VCGTsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3085 } 3086 return 0; 3087} 3088 3089unsigned fastEmit_ARMISD_VCGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3090 if (RetVT.SimpleTy != MVT::v2i32) 3091 return 0; 3092 if ((Subtarget->hasNEON())) { 3093 return fastEmitInst_rr(ARM::VCGTsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3094 } 3095 return 0; 3096} 3097 3098unsigned fastEmit_ARMISD_VCGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3099 if (RetVT.SimpleTy != MVT::v4i32) 3100 return 0; 3101 if ((Subtarget->hasNEON())) { 3102 return fastEmitInst_rr(ARM::VCGTsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3103 } 3104 return 0; 3105} 3106 3107unsigned fastEmit_ARMISD_VCGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3108 if (RetVT.SimpleTy != MVT::v4i16) 3109 return 0; 3110 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3111 return fastEmitInst_rr(ARM::VCGThd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3112 } 3113 return 0; 3114} 3115 3116unsigned fastEmit_ARMISD_VCGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3117 if (RetVT.SimpleTy != MVT::v8i16) 3118 return 0; 3119 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3120 return fastEmitInst_rr(ARM::VCGThq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3121 } 3122 return 0; 3123} 3124 3125unsigned fastEmit_ARMISD_VCGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3126 if (RetVT.SimpleTy != MVT::v2i32) 3127 return 0; 3128 if ((Subtarget->hasNEON())) { 3129 return fastEmitInst_rr(ARM::VCGTfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3130 } 3131 return 0; 3132} 3133 3134unsigned fastEmit_ARMISD_VCGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3135 if (RetVT.SimpleTy != MVT::v4i32) 3136 return 0; 3137 if ((Subtarget->hasNEON())) { 3138 return fastEmitInst_rr(ARM::VCGTfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3139 } 3140 return 0; 3141} 3142 3143unsigned fastEmit_ARMISD_VCGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3144 switch (VT.SimpleTy) { 3145 case MVT::v8i8: return fastEmit_ARMISD_VCGT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3146 case MVT::v16i8: return fastEmit_ARMISD_VCGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3147 case MVT::v4i16: return fastEmit_ARMISD_VCGT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3148 case MVT::v8i16: return fastEmit_ARMISD_VCGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3149 case MVT::v2i32: return fastEmit_ARMISD_VCGT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3150 case MVT::v4i32: return fastEmit_ARMISD_VCGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3151 case MVT::v4f16: return fastEmit_ARMISD_VCGT_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3152 case MVT::v8f16: return fastEmit_ARMISD_VCGT_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3153 case MVT::v2f32: return fastEmit_ARMISD_VCGT_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3154 case MVT::v4f32: return fastEmit_ARMISD_VCGT_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3155 default: return 0; 3156 } 3157} 3158 3159// FastEmit functions for ARMISD::VCGTU. 3160 3161unsigned fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3162 if (RetVT.SimpleTy != MVT::v8i8) 3163 return 0; 3164 if ((Subtarget->hasNEON())) { 3165 return fastEmitInst_rr(ARM::VCGTuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3166 } 3167 return 0; 3168} 3169 3170unsigned fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3171 if (RetVT.SimpleTy != MVT::v16i8) 3172 return 0; 3173 if ((Subtarget->hasNEON())) { 3174 return fastEmitInst_rr(ARM::VCGTuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3175 } 3176 return 0; 3177} 3178 3179unsigned fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3180 if (RetVT.SimpleTy != MVT::v4i16) 3181 return 0; 3182 if ((Subtarget->hasNEON())) { 3183 return fastEmitInst_rr(ARM::VCGTuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3184 } 3185 return 0; 3186} 3187 3188unsigned fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3189 if (RetVT.SimpleTy != MVT::v8i16) 3190 return 0; 3191 if ((Subtarget->hasNEON())) { 3192 return fastEmitInst_rr(ARM::VCGTuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3193 } 3194 return 0; 3195} 3196 3197unsigned fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3198 if (RetVT.SimpleTy != MVT::v2i32) 3199 return 0; 3200 if ((Subtarget->hasNEON())) { 3201 return fastEmitInst_rr(ARM::VCGTuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3202 } 3203 return 0; 3204} 3205 3206unsigned fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3207 if (RetVT.SimpleTy != MVT::v4i32) 3208 return 0; 3209 if ((Subtarget->hasNEON())) { 3210 return fastEmitInst_rr(ARM::VCGTuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3211 } 3212 return 0; 3213} 3214 3215unsigned fastEmit_ARMISD_VCGTU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3216 switch (VT.SimpleTy) { 3217 case MVT::v8i8: return fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3218 case MVT::v16i8: return fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3219 case MVT::v4i16: return fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3220 case MVT::v8i16: return fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3221 case MVT::v2i32: return fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3222 case MVT::v4i32: return fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3223 default: return 0; 3224 } 3225} 3226 3227// FastEmit functions for ARMISD::VMOVDRR. 3228 3229unsigned fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3230 if (RetVT.SimpleTy != MVT::f64) 3231 return 0; 3232 if ((Subtarget->hasVFP2())) { 3233 return fastEmitInst_rr(ARM::VMOVDRR, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3234 } 3235 return 0; 3236} 3237 3238unsigned fastEmit_ARMISD_VMOVDRR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3239 switch (VT.SimpleTy) { 3240 case MVT::i32: return fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3241 default: return 0; 3242 } 3243} 3244 3245// FastEmit functions for ARMISD::VMULLs. 3246 3247unsigned fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3248 if (RetVT.SimpleTy != MVT::v8i16) 3249 return 0; 3250 if ((Subtarget->hasNEON())) { 3251 return fastEmitInst_rr(ARM::VMULLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3252 } 3253 return 0; 3254} 3255 3256unsigned fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3257 if (RetVT.SimpleTy != MVT::v4i32) 3258 return 0; 3259 if ((Subtarget->hasNEON())) { 3260 return fastEmitInst_rr(ARM::VMULLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3261 } 3262 return 0; 3263} 3264 3265unsigned fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3266 if (RetVT.SimpleTy != MVT::v2i64) 3267 return 0; 3268 if ((Subtarget->hasNEON())) { 3269 return fastEmitInst_rr(ARM::VMULLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3270 } 3271 return 0; 3272} 3273 3274unsigned fastEmit_ARMISD_VMULLs_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3275 switch (VT.SimpleTy) { 3276 case MVT::v8i8: return fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3277 case MVT::v4i16: return fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3278 case MVT::v2i32: return fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3279 default: return 0; 3280 } 3281} 3282 3283// FastEmit functions for ARMISD::VMULLu. 3284 3285unsigned fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3286 if (RetVT.SimpleTy != MVT::v8i16) 3287 return 0; 3288 if ((Subtarget->hasNEON())) { 3289 return fastEmitInst_rr(ARM::VMULLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3290 } 3291 return 0; 3292} 3293 3294unsigned fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3295 if (RetVT.SimpleTy != MVT::v4i32) 3296 return 0; 3297 if ((Subtarget->hasNEON())) { 3298 return fastEmitInst_rr(ARM::VMULLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3299 } 3300 return 0; 3301} 3302 3303unsigned fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3304 if (RetVT.SimpleTy != MVT::v2i64) 3305 return 0; 3306 if ((Subtarget->hasNEON())) { 3307 return fastEmitInst_rr(ARM::VMULLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3308 } 3309 return 0; 3310} 3311 3312unsigned fastEmit_ARMISD_VMULLu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3313 switch (VT.SimpleTy) { 3314 case MVT::v8i8: return fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3315 case MVT::v4i16: return fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3316 case MVT::v2i32: return fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3317 default: return 0; 3318 } 3319} 3320 3321// FastEmit functions for ARMISD::VTBL1. 3322 3323unsigned fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3324 if (RetVT.SimpleTy != MVT::v8i8) 3325 return 0; 3326 if ((Subtarget->hasNEON())) { 3327 return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3328 } 3329 return 0; 3330} 3331 3332unsigned fastEmit_ARMISD_VTBL1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3333 switch (VT.SimpleTy) { 3334 case MVT::v8i8: return fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3335 default: return 0; 3336 } 3337} 3338 3339// FastEmit functions for ARMISD::VTST. 3340 3341unsigned fastEmit_ARMISD_VTST_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3342 if (RetVT.SimpleTy != MVT::v8i8) 3343 return 0; 3344 if ((Subtarget->hasNEON())) { 3345 return fastEmitInst_rr(ARM::VTSTv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3346 } 3347 return 0; 3348} 3349 3350unsigned fastEmit_ARMISD_VTST_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3351 if (RetVT.SimpleTy != MVT::v16i8) 3352 return 0; 3353 if ((Subtarget->hasNEON())) { 3354 return fastEmitInst_rr(ARM::VTSTv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3355 } 3356 return 0; 3357} 3358 3359unsigned fastEmit_ARMISD_VTST_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3360 if (RetVT.SimpleTy != MVT::v4i16) 3361 return 0; 3362 if ((Subtarget->hasNEON())) { 3363 return fastEmitInst_rr(ARM::VTSTv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3364 } 3365 return 0; 3366} 3367 3368unsigned fastEmit_ARMISD_VTST_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3369 if (RetVT.SimpleTy != MVT::v8i16) 3370 return 0; 3371 if ((Subtarget->hasNEON())) { 3372 return fastEmitInst_rr(ARM::VTSTv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3373 } 3374 return 0; 3375} 3376 3377unsigned fastEmit_ARMISD_VTST_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3378 if (RetVT.SimpleTy != MVT::v2i32) 3379 return 0; 3380 if ((Subtarget->hasNEON())) { 3381 return fastEmitInst_rr(ARM::VTSTv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3382 } 3383 return 0; 3384} 3385 3386unsigned fastEmit_ARMISD_VTST_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3387 if (RetVT.SimpleTy != MVT::v4i32) 3388 return 0; 3389 if ((Subtarget->hasNEON())) { 3390 return fastEmitInst_rr(ARM::VTSTv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3391 } 3392 return 0; 3393} 3394 3395unsigned fastEmit_ARMISD_VTST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3396 switch (VT.SimpleTy) { 3397 case MVT::v8i8: return fastEmit_ARMISD_VTST_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3398 case MVT::v16i8: return fastEmit_ARMISD_VTST_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3399 case MVT::v4i16: return fastEmit_ARMISD_VTST_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3400 case MVT::v8i16: return fastEmit_ARMISD_VTST_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3401 case MVT::v2i32: return fastEmit_ARMISD_VTST_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3402 case MVT::v4i32: return fastEmit_ARMISD_VTST_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3403 default: return 0; 3404 } 3405} 3406 3407// FastEmit functions for ISD::ADD. 3408 3409unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3410 if (RetVT.SimpleTy != MVT::i32) 3411 return 0; 3412 if ((Subtarget->isThumb2())) { 3413 return fastEmitInst_rr(ARM::t2ADDrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3414 } 3415 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 3416 return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3417 } 3418 if ((!Subtarget->isThumb())) { 3419 return fastEmitInst_rr(ARM::ADDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3420 } 3421 return 0; 3422} 3423 3424unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3425 if (RetVT.SimpleTy != MVT::v8i8) 3426 return 0; 3427 if ((Subtarget->hasNEON())) { 3428 return fastEmitInst_rr(ARM::VADDv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3429 } 3430 return 0; 3431} 3432 3433unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3434 if (RetVT.SimpleTy != MVT::v16i8) 3435 return 0; 3436 if ((Subtarget->hasNEON())) { 3437 return fastEmitInst_rr(ARM::VADDv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3438 } 3439 return 0; 3440} 3441 3442unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3443 if (RetVT.SimpleTy != MVT::v4i16) 3444 return 0; 3445 if ((Subtarget->hasNEON())) { 3446 return fastEmitInst_rr(ARM::VADDv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3447 } 3448 return 0; 3449} 3450 3451unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3452 if (RetVT.SimpleTy != MVT::v8i16) 3453 return 0; 3454 if ((Subtarget->hasNEON())) { 3455 return fastEmitInst_rr(ARM::VADDv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3456 } 3457 return 0; 3458} 3459 3460unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3461 if (RetVT.SimpleTy != MVT::v2i32) 3462 return 0; 3463 if ((Subtarget->hasNEON())) { 3464 return fastEmitInst_rr(ARM::VADDv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3465 } 3466 return 0; 3467} 3468 3469unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3470 if (RetVT.SimpleTy != MVT::v4i32) 3471 return 0; 3472 if ((Subtarget->hasNEON())) { 3473 return fastEmitInst_rr(ARM::VADDv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3474 } 3475 return 0; 3476} 3477 3478unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3479 if (RetVT.SimpleTy != MVT::v1i64) 3480 return 0; 3481 if ((Subtarget->hasNEON())) { 3482 return fastEmitInst_rr(ARM::VADDv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3483 } 3484 return 0; 3485} 3486 3487unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3488 if (RetVT.SimpleTy != MVT::v2i64) 3489 return 0; 3490 if ((Subtarget->hasNEON())) { 3491 return fastEmitInst_rr(ARM::VADDv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3492 } 3493 return 0; 3494} 3495 3496unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3497 switch (VT.SimpleTy) { 3498 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3499 case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3500 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3501 case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3502 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3503 case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3504 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3505 case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3506 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3507 default: return 0; 3508 } 3509} 3510 3511// FastEmit functions for ISD::AND. 3512 3513unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3514 if (RetVT.SimpleTy != MVT::i32) 3515 return 0; 3516 if ((Subtarget->isThumb2())) { 3517 return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3518 } 3519 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 3520 return fastEmitInst_rr(ARM::tAND, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3521 } 3522 if ((!Subtarget->isThumb())) { 3523 return fastEmitInst_rr(ARM::ANDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3524 } 3525 return 0; 3526} 3527 3528unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3529 if (RetVT.SimpleTy != MVT::v2i32) 3530 return 0; 3531 if ((Subtarget->hasNEON())) { 3532 return fastEmitInst_rr(ARM::VANDd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3533 } 3534 return 0; 3535} 3536 3537unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3538 if (RetVT.SimpleTy != MVT::v4i32) 3539 return 0; 3540 if ((Subtarget->hasNEON())) { 3541 return fastEmitInst_rr(ARM::VANDq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3542 } 3543 return 0; 3544} 3545 3546unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3547 switch (VT.SimpleTy) { 3548 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3549 case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3550 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3551 default: return 0; 3552 } 3553} 3554 3555// FastEmit functions for ISD::FADD. 3556 3557unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3558 if (RetVT.SimpleTy != MVT::f16) 3559 return 0; 3560 if ((Subtarget->hasFullFP16())) { 3561 return fastEmitInst_rr(ARM::VADDH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3562 } 3563 return 0; 3564} 3565 3566unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3567 if (RetVT.SimpleTy != MVT::f32) 3568 return 0; 3569 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) { 3570 return fastEmitInst_rr(ARM::VADDS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3571 } 3572 return 0; 3573} 3574 3575unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3576 if (RetVT.SimpleTy != MVT::f64) 3577 return 0; 3578 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) { 3579 return fastEmitInst_rr(ARM::VADDD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3580 } 3581 return 0; 3582} 3583 3584unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3585 if (RetVT.SimpleTy != MVT::v4f16) 3586 return 0; 3587 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3588 return fastEmitInst_rr(ARM::VADDhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3589 } 3590 return 0; 3591} 3592 3593unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3594 if (RetVT.SimpleTy != MVT::v8f16) 3595 return 0; 3596 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3597 return fastEmitInst_rr(ARM::VADDhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3598 } 3599 return 0; 3600} 3601 3602unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3603 if (RetVT.SimpleTy != MVT::v2f32) 3604 return 0; 3605 if ((Subtarget->hasNEON())) { 3606 return fastEmitInst_rr(ARM::VADDfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3607 } 3608 return 0; 3609} 3610 3611unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3612 if (RetVT.SimpleTy != MVT::v4f32) 3613 return 0; 3614 if ((Subtarget->hasNEON())) { 3615 return fastEmitInst_rr(ARM::VADDfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3616 } 3617 return 0; 3618} 3619 3620unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3621 switch (VT.SimpleTy) { 3622 case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3623 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3624 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3625 case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3626 case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3627 case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3628 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3629 default: return 0; 3630 } 3631} 3632 3633// FastEmit functions for ISD::FDIV. 3634 3635unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3636 if (RetVT.SimpleTy != MVT::f16) 3637 return 0; 3638 if ((Subtarget->hasFullFP16())) { 3639 return fastEmitInst_rr(ARM::VDIVH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3640 } 3641 return 0; 3642} 3643 3644unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3645 if (RetVT.SimpleTy != MVT::f32) 3646 return 0; 3647 if ((Subtarget->hasVFP2())) { 3648 return fastEmitInst_rr(ARM::VDIVS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3649 } 3650 return 0; 3651} 3652 3653unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3654 if (RetVT.SimpleTy != MVT::f64) 3655 return 0; 3656 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) { 3657 return fastEmitInst_rr(ARM::VDIVD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3658 } 3659 return 0; 3660} 3661 3662unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3663 switch (VT.SimpleTy) { 3664 case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3665 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3666 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3667 default: return 0; 3668 } 3669} 3670 3671// FastEmit functions for ISD::FMAXNAN. 3672 3673unsigned fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3674 if (RetVT.SimpleTy != MVT::v4f16) 3675 return 0; 3676 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3677 return fastEmitInst_rr(ARM::VMAXhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3678 } 3679 return 0; 3680} 3681 3682unsigned fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3683 if (RetVT.SimpleTy != MVT::v8f16) 3684 return 0; 3685 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3686 return fastEmitInst_rr(ARM::VMAXhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3687 } 3688 return 0; 3689} 3690 3691unsigned fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3692 if (RetVT.SimpleTy != MVT::v2f32) 3693 return 0; 3694 if ((Subtarget->hasNEON())) { 3695 return fastEmitInst_rr(ARM::VMAXfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3696 } 3697 return 0; 3698} 3699 3700unsigned fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3701 if (RetVT.SimpleTy != MVT::v4f32) 3702 return 0; 3703 if ((Subtarget->hasNEON())) { 3704 return fastEmitInst_rr(ARM::VMAXfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3705 } 3706 return 0; 3707} 3708 3709unsigned fastEmit_ISD_FMAXNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3710 switch (VT.SimpleTy) { 3711 case MVT::v4f16: return fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3712 case MVT::v8f16: return fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3713 case MVT::v2f32: return fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3714 case MVT::v4f32: return fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3715 default: return 0; 3716 } 3717} 3718 3719// FastEmit functions for ISD::FMAXNUM. 3720 3721unsigned fastEmit_ISD_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3722 if (RetVT.SimpleTy != MVT::f16) 3723 return 0; 3724 if ((Subtarget->hasFullFP16())) { 3725 return fastEmitInst_rr(ARM::VMAXNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3726 } 3727 return 0; 3728} 3729 3730unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3731 if (RetVT.SimpleTy != MVT::f32) 3732 return 0; 3733 if ((Subtarget->hasFPARMv8())) { 3734 return fastEmitInst_rr(ARM::VMAXNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3735 } 3736 return 0; 3737} 3738 3739unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3740 if (RetVT.SimpleTy != MVT::f64) 3741 return 0; 3742 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) { 3743 return fastEmitInst_rr(ARM::VMAXNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3744 } 3745 return 0; 3746} 3747 3748unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3749 if (RetVT.SimpleTy != MVT::v4f16) 3750 return 0; 3751 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3752 return fastEmitInst_rr(ARM::VMAXNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3753 } 3754 return 0; 3755} 3756 3757unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3758 if (RetVT.SimpleTy != MVT::v8f16) 3759 return 0; 3760 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3761 return fastEmitInst_rr(ARM::VMAXNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3762 } 3763 return 0; 3764} 3765 3766unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3767 if (RetVT.SimpleTy != MVT::v2f32) 3768 return 0; 3769 if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3770 return fastEmitInst_rr(ARM::VMAXNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3771 } 3772 return 0; 3773} 3774 3775unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3776 if (RetVT.SimpleTy != MVT::v4f32) 3777 return 0; 3778 if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3779 return fastEmitInst_rr(ARM::VMAXNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3780 } 3781 return 0; 3782} 3783 3784unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3785 switch (VT.SimpleTy) { 3786 case MVT::f16: return fastEmit_ISD_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3787 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3788 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3789 case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3790 case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3791 case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3792 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3793 default: return 0; 3794 } 3795} 3796 3797// FastEmit functions for ISD::FMINNAN. 3798 3799unsigned fastEmit_ISD_FMINNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3800 if (RetVT.SimpleTy != MVT::v4f16) 3801 return 0; 3802 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3803 return fastEmitInst_rr(ARM::VMINhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3804 } 3805 return 0; 3806} 3807 3808unsigned fastEmit_ISD_FMINNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3809 if (RetVT.SimpleTy != MVT::v8f16) 3810 return 0; 3811 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3812 return fastEmitInst_rr(ARM::VMINhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3813 } 3814 return 0; 3815} 3816 3817unsigned fastEmit_ISD_FMINNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3818 if (RetVT.SimpleTy != MVT::v2f32) 3819 return 0; 3820 if ((Subtarget->hasNEON())) { 3821 return fastEmitInst_rr(ARM::VMINfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3822 } 3823 return 0; 3824} 3825 3826unsigned fastEmit_ISD_FMINNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3827 if (RetVT.SimpleTy != MVT::v4f32) 3828 return 0; 3829 if ((Subtarget->hasNEON())) { 3830 return fastEmitInst_rr(ARM::VMINfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3831 } 3832 return 0; 3833} 3834 3835unsigned fastEmit_ISD_FMINNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3836 switch (VT.SimpleTy) { 3837 case MVT::v4f16: return fastEmit_ISD_FMINNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3838 case MVT::v8f16: return fastEmit_ISD_FMINNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3839 case MVT::v2f32: return fastEmit_ISD_FMINNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3840 case MVT::v4f32: return fastEmit_ISD_FMINNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3841 default: return 0; 3842 } 3843} 3844 3845// FastEmit functions for ISD::FMINNUM. 3846 3847unsigned fastEmit_ISD_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3848 if (RetVT.SimpleTy != MVT::f16) 3849 return 0; 3850 if ((Subtarget->hasFullFP16())) { 3851 return fastEmitInst_rr(ARM::VMINNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3852 } 3853 return 0; 3854} 3855 3856unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3857 if (RetVT.SimpleTy != MVT::f32) 3858 return 0; 3859 if ((Subtarget->hasFPARMv8())) { 3860 return fastEmitInst_rr(ARM::VMINNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3861 } 3862 return 0; 3863} 3864 3865unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3866 if (RetVT.SimpleTy != MVT::f64) 3867 return 0; 3868 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) { 3869 return fastEmitInst_rr(ARM::VMINNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3870 } 3871 return 0; 3872} 3873 3874unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3875 if (RetVT.SimpleTy != MVT::v4f16) 3876 return 0; 3877 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3878 return fastEmitInst_rr(ARM::VMINNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3879 } 3880 return 0; 3881} 3882 3883unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3884 if (RetVT.SimpleTy != MVT::v8f16) 3885 return 0; 3886 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3887 return fastEmitInst_rr(ARM::VMINNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3888 } 3889 return 0; 3890} 3891 3892unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3893 if (RetVT.SimpleTy != MVT::v2f32) 3894 return 0; 3895 if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3896 return fastEmitInst_rr(ARM::VMINNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3897 } 3898 return 0; 3899} 3900 3901unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3902 if (RetVT.SimpleTy != MVT::v4f32) 3903 return 0; 3904 if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3905 return fastEmitInst_rr(ARM::VMINNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3906 } 3907 return 0; 3908} 3909 3910unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3911 switch (VT.SimpleTy) { 3912 case MVT::f16: return fastEmit_ISD_FMINNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3913 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3914 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3915 case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3916 case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3917 case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3918 case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3919 default: return 0; 3920 } 3921} 3922 3923// FastEmit functions for ISD::FMUL. 3924 3925unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3926 if (RetVT.SimpleTy != MVT::f16) 3927 return 0; 3928 if ((Subtarget->hasFullFP16())) { 3929 return fastEmitInst_rr(ARM::VMULH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3930 } 3931 return 0; 3932} 3933 3934unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3935 if (RetVT.SimpleTy != MVT::f32) 3936 return 0; 3937 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) { 3938 return fastEmitInst_rr(ARM::VMULS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3939 } 3940 return 0; 3941} 3942 3943unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3944 if (RetVT.SimpleTy != MVT::f64) 3945 return 0; 3946 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) { 3947 return fastEmitInst_rr(ARM::VMULD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3948 } 3949 return 0; 3950} 3951 3952unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3953 if (RetVT.SimpleTy != MVT::v4f16) 3954 return 0; 3955 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3956 return fastEmitInst_rr(ARM::VMULhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3957 } 3958 return 0; 3959} 3960 3961unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3962 if (RetVT.SimpleTy != MVT::v8f16) 3963 return 0; 3964 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3965 return fastEmitInst_rr(ARM::VMULhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3966 } 3967 return 0; 3968} 3969 3970unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3971 if (RetVT.SimpleTy != MVT::v2f32) 3972 return 0; 3973 if ((Subtarget->hasNEON())) { 3974 return fastEmitInst_rr(ARM::VMULfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3975 } 3976 return 0; 3977} 3978 3979unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3980 if (RetVT.SimpleTy != MVT::v4f32) 3981 return 0; 3982 if ((Subtarget->hasNEON())) { 3983 return fastEmitInst_rr(ARM::VMULfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3984 } 3985 return 0; 3986} 3987 3988unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3989 switch (VT.SimpleTy) { 3990 case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3991 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3992 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3993 case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3994 case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3995 case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3996 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3997 default: return 0; 3998 } 3999} 4000 4001// FastEmit functions for ISD::FSUB. 4002 4003unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4004 if (RetVT.SimpleTy != MVT::f16) 4005 return 0; 4006 if ((Subtarget->hasFullFP16())) { 4007 return fastEmitInst_rr(ARM::VSUBH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4008 } 4009 return 0; 4010} 4011 4012unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4013 if (RetVT.SimpleTy != MVT::f32) 4014 return 0; 4015 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) { 4016 return fastEmitInst_rr(ARM::VSUBS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4017 } 4018 return 0; 4019} 4020 4021unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4022 if (RetVT.SimpleTy != MVT::f64) 4023 return 0; 4024 if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) { 4025 return fastEmitInst_rr(ARM::VSUBD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4026 } 4027 return 0; 4028} 4029 4030unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4031 if (RetVT.SimpleTy != MVT::v4f16) 4032 return 0; 4033 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4034 return fastEmitInst_rr(ARM::VSUBhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4035 } 4036 return 0; 4037} 4038 4039unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4040 if (RetVT.SimpleTy != MVT::v8f16) 4041 return 0; 4042 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4043 return fastEmitInst_rr(ARM::VSUBhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4044 } 4045 return 0; 4046} 4047 4048unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4049 if (RetVT.SimpleTy != MVT::v2f32) 4050 return 0; 4051 if ((Subtarget->hasNEON())) { 4052 return fastEmitInst_rr(ARM::VSUBfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4053 } 4054 return 0; 4055} 4056 4057unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4058 if (RetVT.SimpleTy != MVT::v4f32) 4059 return 0; 4060 if ((Subtarget->hasNEON())) { 4061 return fastEmitInst_rr(ARM::VSUBfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4062 } 4063 return 0; 4064} 4065 4066unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4067 switch (VT.SimpleTy) { 4068 case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4069 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4070 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4071 case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4072 case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4073 case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4074 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4075 default: return 0; 4076 } 4077} 4078 4079// FastEmit functions for ISD::MUL. 4080 4081unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4082 if (RetVT.SimpleTy != MVT::i32) 4083 return 0; 4084 if ((Subtarget->isThumb2())) { 4085 return fastEmitInst_rr(ARM::t2MUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4086 } 4087 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4088 return fastEmitInst_rr(ARM::tMUL, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4089 } 4090 if ((!Subtarget->isThumb()) && (!Subtarget->hasV6Ops()) && (Subtarget->useMulOps())) { 4091 return fastEmitInst_rr(ARM::MULv5, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4092 } 4093 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 4094 return fastEmitInst_rr(ARM::MUL, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4095 } 4096 return 0; 4097} 4098 4099unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4100 if (RetVT.SimpleTy != MVT::v8i8) 4101 return 0; 4102 if ((Subtarget->hasNEON())) { 4103 return fastEmitInst_rr(ARM::VMULv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4104 } 4105 return 0; 4106} 4107 4108unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4109 if (RetVT.SimpleTy != MVT::v16i8) 4110 return 0; 4111 if ((Subtarget->hasNEON())) { 4112 return fastEmitInst_rr(ARM::VMULv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4113 } 4114 return 0; 4115} 4116 4117unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4118 if (RetVT.SimpleTy != MVT::v4i16) 4119 return 0; 4120 if ((Subtarget->hasNEON())) { 4121 return fastEmitInst_rr(ARM::VMULv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4122 } 4123 return 0; 4124} 4125 4126unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4127 if (RetVT.SimpleTy != MVT::v8i16) 4128 return 0; 4129 if ((Subtarget->hasNEON())) { 4130 return fastEmitInst_rr(ARM::VMULv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4131 } 4132 return 0; 4133} 4134 4135unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4136 if (RetVT.SimpleTy != MVT::v2i32) 4137 return 0; 4138 if ((Subtarget->hasNEON())) { 4139 return fastEmitInst_rr(ARM::VMULv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4140 } 4141 return 0; 4142} 4143 4144unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4145 if (RetVT.SimpleTy != MVT::v4i32) 4146 return 0; 4147 if ((Subtarget->hasNEON())) { 4148 return fastEmitInst_rr(ARM::VMULv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4149 } 4150 return 0; 4151} 4152 4153unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4154 switch (VT.SimpleTy) { 4155 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4156 case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4157 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4158 case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4159 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4160 case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4161 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4162 default: return 0; 4163 } 4164} 4165 4166// FastEmit functions for ISD::MULHS. 4167 4168unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4169 if (RetVT.SimpleTy != MVT::i32) 4170 return 0; 4171 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 4172 return fastEmitInst_rr(ARM::t2SMMUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4173 } 4174 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 4175 return fastEmitInst_rr(ARM::SMMUL, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4176 } 4177 return 0; 4178} 4179 4180unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4181 switch (VT.SimpleTy) { 4182 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4183 default: return 0; 4184 } 4185} 4186 4187// FastEmit functions for ISD::OR. 4188 4189unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4190 if (RetVT.SimpleTy != MVT::i32) 4191 return 0; 4192 if ((Subtarget->isThumb2())) { 4193 return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4194 } 4195 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4196 return fastEmitInst_rr(ARM::tORR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4197 } 4198 if ((!Subtarget->isThumb())) { 4199 return fastEmitInst_rr(ARM::ORRrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4200 } 4201 return 0; 4202} 4203 4204unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4205 if (RetVT.SimpleTy != MVT::v2i32) 4206 return 0; 4207 if ((Subtarget->hasNEON())) { 4208 return fastEmitInst_rr(ARM::VORRd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4209 } 4210 return 0; 4211} 4212 4213unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4214 if (RetVT.SimpleTy != MVT::v4i32) 4215 return 0; 4216 if ((Subtarget->hasNEON())) { 4217 return fastEmitInst_rr(ARM::VORRq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4218 } 4219 return 0; 4220} 4221 4222unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4223 switch (VT.SimpleTy) { 4224 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4225 case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4226 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4227 default: return 0; 4228 } 4229} 4230 4231// FastEmit functions for ISD::ROTR. 4232 4233unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4234 if (RetVT.SimpleTy != MVT::i32) 4235 return 0; 4236 if ((Subtarget->isThumb2())) { 4237 return fastEmitInst_rr(ARM::t2RORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4238 } 4239 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4240 return fastEmitInst_rr(ARM::tROR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4241 } 4242 return 0; 4243} 4244 4245unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4246 switch (VT.SimpleTy) { 4247 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4248 default: return 0; 4249 } 4250} 4251 4252// FastEmit functions for ISD::SDIV. 4253 4254unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4255 if (RetVT.SimpleTy != MVT::i32) 4256 return 0; 4257 if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) { 4258 return fastEmitInst_rr(ARM::t2SDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4259 } 4260 if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) { 4261 return fastEmitInst_rr(ARM::SDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4262 } 4263 return 0; 4264} 4265 4266unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4267 switch (VT.SimpleTy) { 4268 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4269 default: return 0; 4270 } 4271} 4272 4273// FastEmit functions for ISD::SHL. 4274 4275unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4276 if (RetVT.SimpleTy != MVT::i32) 4277 return 0; 4278 if ((Subtarget->isThumb2())) { 4279 return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4280 } 4281 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4282 return fastEmitInst_rr(ARM::tLSLrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4283 } 4284 return 0; 4285} 4286 4287unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4288 switch (VT.SimpleTy) { 4289 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4290 default: return 0; 4291 } 4292} 4293 4294// FastEmit functions for ISD::SMAX. 4295 4296unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4297 if (RetVT.SimpleTy != MVT::v8i8) 4298 return 0; 4299 if ((Subtarget->hasNEON())) { 4300 return fastEmitInst_rr(ARM::VMAXsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4301 } 4302 return 0; 4303} 4304 4305unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4306 if (RetVT.SimpleTy != MVT::v16i8) 4307 return 0; 4308 if ((Subtarget->hasNEON())) { 4309 return fastEmitInst_rr(ARM::VMAXsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4310 } 4311 return 0; 4312} 4313 4314unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4315 if (RetVT.SimpleTy != MVT::v4i16) 4316 return 0; 4317 if ((Subtarget->hasNEON())) { 4318 return fastEmitInst_rr(ARM::VMAXsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4319 } 4320 return 0; 4321} 4322 4323unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4324 if (RetVT.SimpleTy != MVT::v8i16) 4325 return 0; 4326 if ((Subtarget->hasNEON())) { 4327 return fastEmitInst_rr(ARM::VMAXsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4328 } 4329 return 0; 4330} 4331 4332unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4333 if (RetVT.SimpleTy != MVT::v2i32) 4334 return 0; 4335 if ((Subtarget->hasNEON())) { 4336 return fastEmitInst_rr(ARM::VMAXsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4337 } 4338 return 0; 4339} 4340 4341unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4342 if (RetVT.SimpleTy != MVT::v4i32) 4343 return 0; 4344 if ((Subtarget->hasNEON())) { 4345 return fastEmitInst_rr(ARM::VMAXsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4346 } 4347 return 0; 4348} 4349 4350unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4351 switch (VT.SimpleTy) { 4352 case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4353 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4354 case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4355 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4356 case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4357 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4358 default: return 0; 4359 } 4360} 4361 4362// FastEmit functions for ISD::SMIN. 4363 4364unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4365 if (RetVT.SimpleTy != MVT::v8i8) 4366 return 0; 4367 if ((Subtarget->hasNEON())) { 4368 return fastEmitInst_rr(ARM::VMINsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4369 } 4370 return 0; 4371} 4372 4373unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4374 if (RetVT.SimpleTy != MVT::v16i8) 4375 return 0; 4376 if ((Subtarget->hasNEON())) { 4377 return fastEmitInst_rr(ARM::VMINsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4378 } 4379 return 0; 4380} 4381 4382unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4383 if (RetVT.SimpleTy != MVT::v4i16) 4384 return 0; 4385 if ((Subtarget->hasNEON())) { 4386 return fastEmitInst_rr(ARM::VMINsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4387 } 4388 return 0; 4389} 4390 4391unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4392 if (RetVT.SimpleTy != MVT::v8i16) 4393 return 0; 4394 if ((Subtarget->hasNEON())) { 4395 return fastEmitInst_rr(ARM::VMINsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4396 } 4397 return 0; 4398} 4399 4400unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4401 if (RetVT.SimpleTy != MVT::v2i32) 4402 return 0; 4403 if ((Subtarget->hasNEON())) { 4404 return fastEmitInst_rr(ARM::VMINsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4405 } 4406 return 0; 4407} 4408 4409unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4410 if (RetVT.SimpleTy != MVT::v4i32) 4411 return 0; 4412 if ((Subtarget->hasNEON())) { 4413 return fastEmitInst_rr(ARM::VMINsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4414 } 4415 return 0; 4416} 4417 4418unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4419 switch (VT.SimpleTy) { 4420 case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4421 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4422 case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4423 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4424 case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4425 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4426 default: return 0; 4427 } 4428} 4429 4430// FastEmit functions for ISD::SRA. 4431 4432unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4433 if (RetVT.SimpleTy != MVT::i32) 4434 return 0; 4435 if ((Subtarget->isThumb2())) { 4436 return fastEmitInst_rr(ARM::t2ASRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4437 } 4438 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4439 return fastEmitInst_rr(ARM::tASRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4440 } 4441 return 0; 4442} 4443 4444unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4445 switch (VT.SimpleTy) { 4446 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4447 default: return 0; 4448 } 4449} 4450 4451// FastEmit functions for ISD::SRL. 4452 4453unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4454 if (RetVT.SimpleTy != MVT::i32) 4455 return 0; 4456 if ((Subtarget->isThumb2())) { 4457 return fastEmitInst_rr(ARM::t2LSRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4458 } 4459 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4460 return fastEmitInst_rr(ARM::tLSRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4461 } 4462 return 0; 4463} 4464 4465unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4466 switch (VT.SimpleTy) { 4467 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4468 default: return 0; 4469 } 4470} 4471 4472// FastEmit functions for ISD::SUB. 4473 4474unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4475 if (RetVT.SimpleTy != MVT::i32) 4476 return 0; 4477 if ((Subtarget->isThumb2())) { 4478 return fastEmitInst_rr(ARM::t2SUBrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4479 } 4480 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4481 return fastEmitInst_rr(ARM::tSUBrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4482 } 4483 if ((!Subtarget->isThumb())) { 4484 return fastEmitInst_rr(ARM::SUBrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4485 } 4486 return 0; 4487} 4488 4489unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4490 if (RetVT.SimpleTy != MVT::v8i8) 4491 return 0; 4492 if ((Subtarget->hasNEON())) { 4493 return fastEmitInst_rr(ARM::VSUBv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4494 } 4495 return 0; 4496} 4497 4498unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4499 if (RetVT.SimpleTy != MVT::v16i8) 4500 return 0; 4501 if ((Subtarget->hasNEON())) { 4502 return fastEmitInst_rr(ARM::VSUBv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4503 } 4504 return 0; 4505} 4506 4507unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4508 if (RetVT.SimpleTy != MVT::v4i16) 4509 return 0; 4510 if ((Subtarget->hasNEON())) { 4511 return fastEmitInst_rr(ARM::VSUBv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4512 } 4513 return 0; 4514} 4515 4516unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4517 if (RetVT.SimpleTy != MVT::v8i16) 4518 return 0; 4519 if ((Subtarget->hasNEON())) { 4520 return fastEmitInst_rr(ARM::VSUBv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4521 } 4522 return 0; 4523} 4524 4525unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4526 if (RetVT.SimpleTy != MVT::v2i32) 4527 return 0; 4528 if ((Subtarget->hasNEON())) { 4529 return fastEmitInst_rr(ARM::VSUBv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4530 } 4531 return 0; 4532} 4533 4534unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4535 if (RetVT.SimpleTy != MVT::v4i32) 4536 return 0; 4537 if ((Subtarget->hasNEON())) { 4538 return fastEmitInst_rr(ARM::VSUBv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4539 } 4540 return 0; 4541} 4542 4543unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4544 if (RetVT.SimpleTy != MVT::v1i64) 4545 return 0; 4546 if ((Subtarget->hasNEON())) { 4547 return fastEmitInst_rr(ARM::VSUBv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4548 } 4549 return 0; 4550} 4551 4552unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4553 if (RetVT.SimpleTy != MVT::v2i64) 4554 return 0; 4555 if ((Subtarget->hasNEON())) { 4556 return fastEmitInst_rr(ARM::VSUBv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4557 } 4558 return 0; 4559} 4560 4561unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4562 switch (VT.SimpleTy) { 4563 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4564 case MVT::v8i8: return fastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4565 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4566 case MVT::v4i16: return fastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4567 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4568 case MVT::v2i32: return fastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4569 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4570 case MVT::v1i64: return fastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4571 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4572 default: return 0; 4573 } 4574} 4575 4576// FastEmit functions for ISD::UDIV. 4577 4578unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4579 if (RetVT.SimpleTy != MVT::i32) 4580 return 0; 4581 if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) { 4582 return fastEmitInst_rr(ARM::t2UDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4583 } 4584 if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) { 4585 return fastEmitInst_rr(ARM::UDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4586 } 4587 return 0; 4588} 4589 4590unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4591 switch (VT.SimpleTy) { 4592 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4593 default: return 0; 4594 } 4595} 4596 4597// FastEmit functions for ISD::UMAX. 4598 4599unsigned fastEmit_ISD_UMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4600 if (RetVT.SimpleTy != MVT::v8i8) 4601 return 0; 4602 if ((Subtarget->hasNEON())) { 4603 return fastEmitInst_rr(ARM::VMAXuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4604 } 4605 return 0; 4606} 4607 4608unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4609 if (RetVT.SimpleTy != MVT::v16i8) 4610 return 0; 4611 if ((Subtarget->hasNEON())) { 4612 return fastEmitInst_rr(ARM::VMAXuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4613 } 4614 return 0; 4615} 4616 4617unsigned fastEmit_ISD_UMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4618 if (RetVT.SimpleTy != MVT::v4i16) 4619 return 0; 4620 if ((Subtarget->hasNEON())) { 4621 return fastEmitInst_rr(ARM::VMAXuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4622 } 4623 return 0; 4624} 4625 4626unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4627 if (RetVT.SimpleTy != MVT::v8i16) 4628 return 0; 4629 if ((Subtarget->hasNEON())) { 4630 return fastEmitInst_rr(ARM::VMAXuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4631 } 4632 return 0; 4633} 4634 4635unsigned fastEmit_ISD_UMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4636 if (RetVT.SimpleTy != MVT::v2i32) 4637 return 0; 4638 if ((Subtarget->hasNEON())) { 4639 return fastEmitInst_rr(ARM::VMAXuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4640 } 4641 return 0; 4642} 4643 4644unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4645 if (RetVT.SimpleTy != MVT::v4i32) 4646 return 0; 4647 if ((Subtarget->hasNEON())) { 4648 return fastEmitInst_rr(ARM::VMAXuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4649 } 4650 return 0; 4651} 4652 4653unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4654 switch (VT.SimpleTy) { 4655 case MVT::v8i8: return fastEmit_ISD_UMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4656 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4657 case MVT::v4i16: return fastEmit_ISD_UMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4658 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4659 case MVT::v2i32: return fastEmit_ISD_UMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4660 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4661 default: return 0; 4662 } 4663} 4664 4665// FastEmit functions for ISD::UMIN. 4666 4667unsigned fastEmit_ISD_UMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4668 if (RetVT.SimpleTy != MVT::v8i8) 4669 return 0; 4670 if ((Subtarget->hasNEON())) { 4671 return fastEmitInst_rr(ARM::VMINuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4672 } 4673 return 0; 4674} 4675 4676unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4677 if (RetVT.SimpleTy != MVT::v16i8) 4678 return 0; 4679 if ((Subtarget->hasNEON())) { 4680 return fastEmitInst_rr(ARM::VMINuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4681 } 4682 return 0; 4683} 4684 4685unsigned fastEmit_ISD_UMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4686 if (RetVT.SimpleTy != MVT::v4i16) 4687 return 0; 4688 if ((Subtarget->hasNEON())) { 4689 return fastEmitInst_rr(ARM::VMINuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4690 } 4691 return 0; 4692} 4693 4694unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4695 if (RetVT.SimpleTy != MVT::v8i16) 4696 return 0; 4697 if ((Subtarget->hasNEON())) { 4698 return fastEmitInst_rr(ARM::VMINuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4699 } 4700 return 0; 4701} 4702 4703unsigned fastEmit_ISD_UMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4704 if (RetVT.SimpleTy != MVT::v2i32) 4705 return 0; 4706 if ((Subtarget->hasNEON())) { 4707 return fastEmitInst_rr(ARM::VMINuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4708 } 4709 return 0; 4710} 4711 4712unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4713 if (RetVT.SimpleTy != MVT::v4i32) 4714 return 0; 4715 if ((Subtarget->hasNEON())) { 4716 return fastEmitInst_rr(ARM::VMINuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4717 } 4718 return 0; 4719} 4720 4721unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4722 switch (VT.SimpleTy) { 4723 case MVT::v8i8: return fastEmit_ISD_UMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4724 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4725 case MVT::v4i16: return fastEmit_ISD_UMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4726 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4727 case MVT::v2i32: return fastEmit_ISD_UMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4728 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4729 default: return 0; 4730 } 4731} 4732 4733// FastEmit functions for ISD::XOR. 4734 4735unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4736 if (RetVT.SimpleTy != MVT::i32) 4737 return 0; 4738 if ((Subtarget->isThumb2())) { 4739 return fastEmitInst_rr(ARM::t2EORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4740 } 4741 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4742 return fastEmitInst_rr(ARM::tEOR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4743 } 4744 if ((!Subtarget->isThumb())) { 4745 return fastEmitInst_rr(ARM::EORrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4746 } 4747 return 0; 4748} 4749 4750unsigned fastEmit_ISD_XOR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4751 if (RetVT.SimpleTy != MVT::v2i32) 4752 return 0; 4753 if ((Subtarget->hasNEON())) { 4754 return fastEmitInst_rr(ARM::VEORd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4755 } 4756 return 0; 4757} 4758 4759unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4760 if (RetVT.SimpleTy != MVT::v4i32) 4761 return 0; 4762 if ((Subtarget->hasNEON())) { 4763 return fastEmitInst_rr(ARM::VEORq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4764 } 4765 return 0; 4766} 4767 4768unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4769 switch (VT.SimpleTy) { 4770 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4771 case MVT::v2i32: return fastEmit_ISD_XOR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4772 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4773 default: return 0; 4774 } 4775} 4776 4777// Top-level FastEmit function. 4778 4779unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override { 4780 switch (Opcode) { 4781 case ARMISD::CMP: return fastEmit_ARMISD_CMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4782 case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4783 case ARMISD::EH_SJLJ_LONGJMP: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4784 case ARMISD::EH_SJLJ_SETJMP: return fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4785 case ARMISD::SMULWB: return fastEmit_ARMISD_SMULWB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4786 case ARMISD::SMULWT: return fastEmit_ARMISD_SMULWT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4787 case ARMISD::VCEQ: return fastEmit_ARMISD_VCEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4788 case ARMISD::VCGE: return fastEmit_ARMISD_VCGE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4789 case ARMISD::VCGEU: return fastEmit_ARMISD_VCGEU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4790 case ARMISD::VCGT: return fastEmit_ARMISD_VCGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4791 case ARMISD::VCGTU: return fastEmit_ARMISD_VCGTU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4792 case ARMISD::VMOVDRR: return fastEmit_ARMISD_VMOVDRR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4793 case ARMISD::VMULLs: return fastEmit_ARMISD_VMULLs_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4794 case ARMISD::VMULLu: return fastEmit_ARMISD_VMULLu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4795 case ARMISD::VTBL1: return fastEmit_ARMISD_VTBL1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4796 case ARMISD::VTST: return fastEmit_ARMISD_VTST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4797 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4798 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4799 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4800 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4801 case ISD::FMAXNAN: return fastEmit_ISD_FMAXNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4802 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4803 case ISD::FMINNAN: return fastEmit_ISD_FMINNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4804 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4805 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4806 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4807 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4808 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4809 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4810 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4811 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4812 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4813 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4814 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4815 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4816 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4817 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4818 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4819 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4820 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4821 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4822 default: return 0; 4823 } 4824} 4825 4826// FastEmit functions for ARMISD::PIC_ADD. 4827 4828unsigned fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4829 if (RetVT.SimpleTy != MVT::i32) 4830 return 0; 4831 if ((Subtarget->isThumb())) { 4832 return fastEmitInst_ri(ARM::tPICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 4833 } 4834 if ((!Subtarget->isThumb())) { 4835 return fastEmitInst_ri(ARM::PICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 4836 } 4837 return 0; 4838} 4839 4840unsigned fastEmit_ARMISD_PIC_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4841 switch (VT.SimpleTy) { 4842 case MVT::i32: return fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); 4843 default: return 0; 4844 } 4845} 4846 4847// FastEmit functions for ARMISD::VDUPLANE. 4848 4849unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4850 if (RetVT.SimpleTy != MVT::v8i8) 4851 return 0; 4852 if ((Subtarget->hasNEON())) { 4853 return fastEmitInst_ri(ARM::VDUPLN8d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 4854 } 4855 return 0; 4856} 4857 4858unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4859 if (RetVT.SimpleTy != MVT::v4i16) 4860 return 0; 4861 if ((Subtarget->hasNEON())) { 4862 return fastEmitInst_ri(ARM::VDUPLN16d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 4863 } 4864 return 0; 4865} 4866 4867unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4868 if (RetVT.SimpleTy != MVT::v2i32) 4869 return 0; 4870 if ((Subtarget->hasNEON())) { 4871 return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 4872 } 4873 return 0; 4874} 4875 4876unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4877 return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 4878} 4879 4880unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4881 return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 4882} 4883 4884unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4885switch (RetVT.SimpleTy) { 4886 case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(Op0, Op0IsKill, imm1); 4887 case MVT::v4f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(Op0, Op0IsKill, imm1); 4888 default: return 0; 4889} 4890} 4891 4892unsigned fastEmit_ARMISD_VDUPLANE_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4893 switch (VT.SimpleTy) { 4894 case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 4895 case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 4896 case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 4897 case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(RetVT, Op0, Op0IsKill, imm1); 4898 default: return 0; 4899 } 4900} 4901 4902// FastEmit functions for ARMISD::VGETLANEs. 4903 4904unsigned fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4905 if (RetVT.SimpleTy != MVT::i32) 4906 return 0; 4907 if ((Subtarget->hasNEON())) { 4908 return fastEmitInst_ri(ARM::VGETLNs8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 4909 } 4910 return 0; 4911} 4912 4913unsigned fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4914 if (RetVT.SimpleTy != MVT::i32) 4915 return 0; 4916 if ((Subtarget->hasNEON())) { 4917 return fastEmitInst_ri(ARM::VGETLNs16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 4918 } 4919 return 0; 4920} 4921 4922unsigned fastEmit_ARMISD_VGETLANEs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4923 switch (VT.SimpleTy) { 4924 case MVT::v8i8: return fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 4925 case MVT::v4i16: return fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 4926 default: return 0; 4927 } 4928} 4929 4930// FastEmit functions for ARMISD::VGETLANEu. 4931 4932unsigned fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4933 if (RetVT.SimpleTy != MVT::i32) 4934 return 0; 4935 if ((Subtarget->hasNEON())) { 4936 return fastEmitInst_ri(ARM::VGETLNu8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 4937 } 4938 return 0; 4939} 4940 4941unsigned fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4942 if (RetVT.SimpleTy != MVT::i32) 4943 return 0; 4944 if ((Subtarget->hasNEON())) { 4945 return fastEmitInst_ri(ARM::VGETLNu16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 4946 } 4947 return 0; 4948} 4949 4950unsigned fastEmit_ARMISD_VGETLANEu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4951 switch (VT.SimpleTy) { 4952 case MVT::v8i8: return fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 4953 case MVT::v4i16: return fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 4954 default: return 0; 4955 } 4956} 4957 4958// FastEmit functions for ARMISD::VQSHLs. 4959 4960unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4961 if (RetVT.SimpleTy != MVT::v8i8) 4962 return 0; 4963 if ((Subtarget->hasNEON())) { 4964 return fastEmitInst_ri(ARM::VQSHLsiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 4965 } 4966 return 0; 4967} 4968 4969unsigned fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4970 if (RetVT.SimpleTy != MVT::v16i8) 4971 return 0; 4972 if ((Subtarget->hasNEON())) { 4973 return fastEmitInst_ri(ARM::VQSHLsiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 4974 } 4975 return 0; 4976} 4977 4978unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4979 if (RetVT.SimpleTy != MVT::v4i16) 4980 return 0; 4981 if ((Subtarget->hasNEON())) { 4982 return fastEmitInst_ri(ARM::VQSHLsiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 4983 } 4984 return 0; 4985} 4986 4987unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4988 if (RetVT.SimpleTy != MVT::v8i16) 4989 return 0; 4990 if ((Subtarget->hasNEON())) { 4991 return fastEmitInst_ri(ARM::VQSHLsiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 4992 } 4993 return 0; 4994} 4995 4996unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 4997 if (RetVT.SimpleTy != MVT::v2i32) 4998 return 0; 4999 if ((Subtarget->hasNEON())) { 5000 return fastEmitInst_ri(ARM::VQSHLsiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5001 } 5002 return 0; 5003} 5004 5005unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5006 if (RetVT.SimpleTy != MVT::v4i32) 5007 return 0; 5008 if ((Subtarget->hasNEON())) { 5009 return fastEmitInst_ri(ARM::VQSHLsiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5010 } 5011 return 0; 5012} 5013 5014unsigned fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5015 if (RetVT.SimpleTy != MVT::v1i64) 5016 return 0; 5017 if ((Subtarget->hasNEON())) { 5018 return fastEmitInst_ri(ARM::VQSHLsiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5019 } 5020 return 0; 5021} 5022 5023unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5024 if (RetVT.SimpleTy != MVT::v2i64) 5025 return 0; 5026 if ((Subtarget->hasNEON())) { 5027 return fastEmitInst_ri(ARM::VQSHLsiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5028 } 5029 return 0; 5030} 5031 5032unsigned fastEmit_ARMISD_VQSHLs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5033 switch (VT.SimpleTy) { 5034 case MVT::v8i8: return fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5035 case MVT::v16i8: return fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5036 case MVT::v4i16: return fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5037 case MVT::v8i16: return fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5038 case MVT::v2i32: return fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5039 case MVT::v4i32: return fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5040 case MVT::v1i64: return fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5041 case MVT::v2i64: return fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5042 default: return 0; 5043 } 5044} 5045 5046// FastEmit functions for ARMISD::VQSHLsu. 5047 5048unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5049 if (RetVT.SimpleTy != MVT::v8i8) 5050 return 0; 5051 if ((Subtarget->hasNEON())) { 5052 return fastEmitInst_ri(ARM::VQSHLsuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5053 } 5054 return 0; 5055} 5056 5057unsigned fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5058 if (RetVT.SimpleTy != MVT::v16i8) 5059 return 0; 5060 if ((Subtarget->hasNEON())) { 5061 return fastEmitInst_ri(ARM::VQSHLsuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5062 } 5063 return 0; 5064} 5065 5066unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5067 if (RetVT.SimpleTy != MVT::v4i16) 5068 return 0; 5069 if ((Subtarget->hasNEON())) { 5070 return fastEmitInst_ri(ARM::VQSHLsuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5071 } 5072 return 0; 5073} 5074 5075unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5076 if (RetVT.SimpleTy != MVT::v8i16) 5077 return 0; 5078 if ((Subtarget->hasNEON())) { 5079 return fastEmitInst_ri(ARM::VQSHLsuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5080 } 5081 return 0; 5082} 5083 5084unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5085 if (RetVT.SimpleTy != MVT::v2i32) 5086 return 0; 5087 if ((Subtarget->hasNEON())) { 5088 return fastEmitInst_ri(ARM::VQSHLsuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5089 } 5090 return 0; 5091} 5092 5093unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5094 if (RetVT.SimpleTy != MVT::v4i32) 5095 return 0; 5096 if ((Subtarget->hasNEON())) { 5097 return fastEmitInst_ri(ARM::VQSHLsuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5098 } 5099 return 0; 5100} 5101 5102unsigned fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5103 if (RetVT.SimpleTy != MVT::v1i64) 5104 return 0; 5105 if ((Subtarget->hasNEON())) { 5106 return fastEmitInst_ri(ARM::VQSHLsuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5107 } 5108 return 0; 5109} 5110 5111unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5112 if (RetVT.SimpleTy != MVT::v2i64) 5113 return 0; 5114 if ((Subtarget->hasNEON())) { 5115 return fastEmitInst_ri(ARM::VQSHLsuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5116 } 5117 return 0; 5118} 5119 5120unsigned fastEmit_ARMISD_VQSHLsu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5121 switch (VT.SimpleTy) { 5122 case MVT::v8i8: return fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5123 case MVT::v16i8: return fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5124 case MVT::v4i16: return fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5125 case MVT::v8i16: return fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5126 case MVT::v2i32: return fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5127 case MVT::v4i32: return fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5128 case MVT::v1i64: return fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5129 case MVT::v2i64: return fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5130 default: return 0; 5131 } 5132} 5133 5134// FastEmit functions for ARMISD::VQSHLu. 5135 5136unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5137 if (RetVT.SimpleTy != MVT::v8i8) 5138 return 0; 5139 if ((Subtarget->hasNEON())) { 5140 return fastEmitInst_ri(ARM::VQSHLuiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5141 } 5142 return 0; 5143} 5144 5145unsigned fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5146 if (RetVT.SimpleTy != MVT::v16i8) 5147 return 0; 5148 if ((Subtarget->hasNEON())) { 5149 return fastEmitInst_ri(ARM::VQSHLuiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5150 } 5151 return 0; 5152} 5153 5154unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5155 if (RetVT.SimpleTy != MVT::v4i16) 5156 return 0; 5157 if ((Subtarget->hasNEON())) { 5158 return fastEmitInst_ri(ARM::VQSHLuiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5159 } 5160 return 0; 5161} 5162 5163unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5164 if (RetVT.SimpleTy != MVT::v8i16) 5165 return 0; 5166 if ((Subtarget->hasNEON())) { 5167 return fastEmitInst_ri(ARM::VQSHLuiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5168 } 5169 return 0; 5170} 5171 5172unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5173 if (RetVT.SimpleTy != MVT::v2i32) 5174 return 0; 5175 if ((Subtarget->hasNEON())) { 5176 return fastEmitInst_ri(ARM::VQSHLuiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5177 } 5178 return 0; 5179} 5180 5181unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5182 if (RetVT.SimpleTy != MVT::v4i32) 5183 return 0; 5184 if ((Subtarget->hasNEON())) { 5185 return fastEmitInst_ri(ARM::VQSHLuiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5186 } 5187 return 0; 5188} 5189 5190unsigned fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5191 if (RetVT.SimpleTy != MVT::v1i64) 5192 return 0; 5193 if ((Subtarget->hasNEON())) { 5194 return fastEmitInst_ri(ARM::VQSHLuiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5195 } 5196 return 0; 5197} 5198 5199unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5200 if (RetVT.SimpleTy != MVT::v2i64) 5201 return 0; 5202 if ((Subtarget->hasNEON())) { 5203 return fastEmitInst_ri(ARM::VQSHLuiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5204 } 5205 return 0; 5206} 5207 5208unsigned fastEmit_ARMISD_VQSHLu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5209 switch (VT.SimpleTy) { 5210 case MVT::v8i8: return fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5211 case MVT::v16i8: return fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5212 case MVT::v4i16: return fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5213 case MVT::v8i16: return fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5214 case MVT::v2i32: return fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5215 case MVT::v4i32: return fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5216 case MVT::v1i64: return fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5217 case MVT::v2i64: return fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5218 default: return 0; 5219 } 5220} 5221 5222// FastEmit functions for ARMISD::VRSHRs. 5223 5224unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5225 if (RetVT.SimpleTy != MVT::v8i8) 5226 return 0; 5227 if ((Subtarget->hasNEON())) { 5228 return fastEmitInst_ri(ARM::VRSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5229 } 5230 return 0; 5231} 5232 5233unsigned fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5234 if (RetVT.SimpleTy != MVT::v16i8) 5235 return 0; 5236 if ((Subtarget->hasNEON())) { 5237 return fastEmitInst_ri(ARM::VRSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5238 } 5239 return 0; 5240} 5241 5242unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5243 if (RetVT.SimpleTy != MVT::v4i16) 5244 return 0; 5245 if ((Subtarget->hasNEON())) { 5246 return fastEmitInst_ri(ARM::VRSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5247 } 5248 return 0; 5249} 5250 5251unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5252 if (RetVT.SimpleTy != MVT::v8i16) 5253 return 0; 5254 if ((Subtarget->hasNEON())) { 5255 return fastEmitInst_ri(ARM::VRSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5256 } 5257 return 0; 5258} 5259 5260unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5261 if (RetVT.SimpleTy != MVT::v2i32) 5262 return 0; 5263 if ((Subtarget->hasNEON())) { 5264 return fastEmitInst_ri(ARM::VRSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5265 } 5266 return 0; 5267} 5268 5269unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5270 if (RetVT.SimpleTy != MVT::v4i32) 5271 return 0; 5272 if ((Subtarget->hasNEON())) { 5273 return fastEmitInst_ri(ARM::VRSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5274 } 5275 return 0; 5276} 5277 5278unsigned fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5279 if (RetVT.SimpleTy != MVT::v1i64) 5280 return 0; 5281 if ((Subtarget->hasNEON())) { 5282 return fastEmitInst_ri(ARM::VRSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5283 } 5284 return 0; 5285} 5286 5287unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5288 if (RetVT.SimpleTy != MVT::v2i64) 5289 return 0; 5290 if ((Subtarget->hasNEON())) { 5291 return fastEmitInst_ri(ARM::VRSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5292 } 5293 return 0; 5294} 5295 5296unsigned fastEmit_ARMISD_VRSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5297 switch (VT.SimpleTy) { 5298 case MVT::v8i8: return fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5299 case MVT::v16i8: return fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5300 case MVT::v4i16: return fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5301 case MVT::v8i16: return fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5302 case MVT::v2i32: return fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5303 case MVT::v4i32: return fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5304 case MVT::v1i64: return fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5305 case MVT::v2i64: return fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5306 default: return 0; 5307 } 5308} 5309 5310// FastEmit functions for ARMISD::VRSHRu. 5311 5312unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5313 if (RetVT.SimpleTy != MVT::v8i8) 5314 return 0; 5315 if ((Subtarget->hasNEON())) { 5316 return fastEmitInst_ri(ARM::VRSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5317 } 5318 return 0; 5319} 5320 5321unsigned fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5322 if (RetVT.SimpleTy != MVT::v16i8) 5323 return 0; 5324 if ((Subtarget->hasNEON())) { 5325 return fastEmitInst_ri(ARM::VRSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5326 } 5327 return 0; 5328} 5329 5330unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5331 if (RetVT.SimpleTy != MVT::v4i16) 5332 return 0; 5333 if ((Subtarget->hasNEON())) { 5334 return fastEmitInst_ri(ARM::VRSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5335 } 5336 return 0; 5337} 5338 5339unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5340 if (RetVT.SimpleTy != MVT::v8i16) 5341 return 0; 5342 if ((Subtarget->hasNEON())) { 5343 return fastEmitInst_ri(ARM::VRSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5344 } 5345 return 0; 5346} 5347 5348unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5349 if (RetVT.SimpleTy != MVT::v2i32) 5350 return 0; 5351 if ((Subtarget->hasNEON())) { 5352 return fastEmitInst_ri(ARM::VRSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5353 } 5354 return 0; 5355} 5356 5357unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5358 if (RetVT.SimpleTy != MVT::v4i32) 5359 return 0; 5360 if ((Subtarget->hasNEON())) { 5361 return fastEmitInst_ri(ARM::VRSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5362 } 5363 return 0; 5364} 5365 5366unsigned fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5367 if (RetVT.SimpleTy != MVT::v1i64) 5368 return 0; 5369 if ((Subtarget->hasNEON())) { 5370 return fastEmitInst_ri(ARM::VRSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5371 } 5372 return 0; 5373} 5374 5375unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5376 if (RetVT.SimpleTy != MVT::v2i64) 5377 return 0; 5378 if ((Subtarget->hasNEON())) { 5379 return fastEmitInst_ri(ARM::VRSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5380 } 5381 return 0; 5382} 5383 5384unsigned fastEmit_ARMISD_VRSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5385 switch (VT.SimpleTy) { 5386 case MVT::v8i8: return fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5387 case MVT::v16i8: return fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5388 case MVT::v4i16: return fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5389 case MVT::v8i16: return fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5390 case MVT::v2i32: return fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5391 case MVT::v4i32: return fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5392 case MVT::v1i64: return fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5393 case MVT::v2i64: return fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5394 default: return 0; 5395 } 5396} 5397 5398// FastEmit functions for ARMISD::VSHL. 5399 5400unsigned fastEmit_ARMISD_VSHL_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5401 if (RetVT.SimpleTy != MVT::v8i8) 5402 return 0; 5403 if ((Subtarget->hasNEON())) { 5404 return fastEmitInst_ri(ARM::VSHLiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5405 } 5406 return 0; 5407} 5408 5409unsigned fastEmit_ARMISD_VSHL_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5410 if (RetVT.SimpleTy != MVT::v16i8) 5411 return 0; 5412 if ((Subtarget->hasNEON())) { 5413 return fastEmitInst_ri(ARM::VSHLiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5414 } 5415 return 0; 5416} 5417 5418unsigned fastEmit_ARMISD_VSHL_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5419 if (RetVT.SimpleTy != MVT::v4i16) 5420 return 0; 5421 if ((Subtarget->hasNEON())) { 5422 return fastEmitInst_ri(ARM::VSHLiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5423 } 5424 return 0; 5425} 5426 5427unsigned fastEmit_ARMISD_VSHL_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5428 if (RetVT.SimpleTy != MVT::v8i16) 5429 return 0; 5430 if ((Subtarget->hasNEON())) { 5431 return fastEmitInst_ri(ARM::VSHLiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5432 } 5433 return 0; 5434} 5435 5436unsigned fastEmit_ARMISD_VSHL_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5437 if (RetVT.SimpleTy != MVT::v2i32) 5438 return 0; 5439 if ((Subtarget->hasNEON())) { 5440 return fastEmitInst_ri(ARM::VSHLiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5441 } 5442 return 0; 5443} 5444 5445unsigned fastEmit_ARMISD_VSHL_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5446 if (RetVT.SimpleTy != MVT::v4i32) 5447 return 0; 5448 if ((Subtarget->hasNEON())) { 5449 return fastEmitInst_ri(ARM::VSHLiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5450 } 5451 return 0; 5452} 5453 5454unsigned fastEmit_ARMISD_VSHL_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5455 if (RetVT.SimpleTy != MVT::v1i64) 5456 return 0; 5457 if ((Subtarget->hasNEON())) { 5458 return fastEmitInst_ri(ARM::VSHLiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5459 } 5460 return 0; 5461} 5462 5463unsigned fastEmit_ARMISD_VSHL_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5464 if (RetVT.SimpleTy != MVT::v2i64) 5465 return 0; 5466 if ((Subtarget->hasNEON())) { 5467 return fastEmitInst_ri(ARM::VSHLiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5468 } 5469 return 0; 5470} 5471 5472unsigned fastEmit_ARMISD_VSHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5473 switch (VT.SimpleTy) { 5474 case MVT::v8i8: return fastEmit_ARMISD_VSHL_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5475 case MVT::v16i8: return fastEmit_ARMISD_VSHL_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5476 case MVT::v4i16: return fastEmit_ARMISD_VSHL_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5477 case MVT::v8i16: return fastEmit_ARMISD_VSHL_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5478 case MVT::v2i32: return fastEmit_ARMISD_VSHL_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5479 case MVT::v4i32: return fastEmit_ARMISD_VSHL_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5480 case MVT::v1i64: return fastEmit_ARMISD_VSHL_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5481 case MVT::v2i64: return fastEmit_ARMISD_VSHL_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5482 default: return 0; 5483 } 5484} 5485 5486// FastEmit functions for ARMISD::VSHRs. 5487 5488unsigned fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5489 if (RetVT.SimpleTy != MVT::v8i8) 5490 return 0; 5491 if ((Subtarget->hasNEON())) { 5492 return fastEmitInst_ri(ARM::VSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5493 } 5494 return 0; 5495} 5496 5497unsigned fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5498 if (RetVT.SimpleTy != MVT::v16i8) 5499 return 0; 5500 if ((Subtarget->hasNEON())) { 5501 return fastEmitInst_ri(ARM::VSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5502 } 5503 return 0; 5504} 5505 5506unsigned fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5507 if (RetVT.SimpleTy != MVT::v4i16) 5508 return 0; 5509 if ((Subtarget->hasNEON())) { 5510 return fastEmitInst_ri(ARM::VSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5511 } 5512 return 0; 5513} 5514 5515unsigned fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5516 if (RetVT.SimpleTy != MVT::v8i16) 5517 return 0; 5518 if ((Subtarget->hasNEON())) { 5519 return fastEmitInst_ri(ARM::VSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5520 } 5521 return 0; 5522} 5523 5524unsigned fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5525 if (RetVT.SimpleTy != MVT::v2i32) 5526 return 0; 5527 if ((Subtarget->hasNEON())) { 5528 return fastEmitInst_ri(ARM::VSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5529 } 5530 return 0; 5531} 5532 5533unsigned fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5534 if (RetVT.SimpleTy != MVT::v4i32) 5535 return 0; 5536 if ((Subtarget->hasNEON())) { 5537 return fastEmitInst_ri(ARM::VSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5538 } 5539 return 0; 5540} 5541 5542unsigned fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5543 if (RetVT.SimpleTy != MVT::v1i64) 5544 return 0; 5545 if ((Subtarget->hasNEON())) { 5546 return fastEmitInst_ri(ARM::VSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5547 } 5548 return 0; 5549} 5550 5551unsigned fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5552 if (RetVT.SimpleTy != MVT::v2i64) 5553 return 0; 5554 if ((Subtarget->hasNEON())) { 5555 return fastEmitInst_ri(ARM::VSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5556 } 5557 return 0; 5558} 5559 5560unsigned fastEmit_ARMISD_VSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5561 switch (VT.SimpleTy) { 5562 case MVT::v8i8: return fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5563 case MVT::v16i8: return fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5564 case MVT::v4i16: return fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5565 case MVT::v8i16: return fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5566 case MVT::v2i32: return fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5567 case MVT::v4i32: return fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5568 case MVT::v1i64: return fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5569 case MVT::v2i64: return fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5570 default: return 0; 5571 } 5572} 5573 5574// FastEmit functions for ARMISD::VSHRu. 5575 5576unsigned fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5577 if (RetVT.SimpleTy != MVT::v8i8) 5578 return 0; 5579 if ((Subtarget->hasNEON())) { 5580 return fastEmitInst_ri(ARM::VSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5581 } 5582 return 0; 5583} 5584 5585unsigned fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5586 if (RetVT.SimpleTy != MVT::v16i8) 5587 return 0; 5588 if ((Subtarget->hasNEON())) { 5589 return fastEmitInst_ri(ARM::VSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5590 } 5591 return 0; 5592} 5593 5594unsigned fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5595 if (RetVT.SimpleTy != MVT::v4i16) 5596 return 0; 5597 if ((Subtarget->hasNEON())) { 5598 return fastEmitInst_ri(ARM::VSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5599 } 5600 return 0; 5601} 5602 5603unsigned fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5604 if (RetVT.SimpleTy != MVT::v8i16) 5605 return 0; 5606 if ((Subtarget->hasNEON())) { 5607 return fastEmitInst_ri(ARM::VSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5608 } 5609 return 0; 5610} 5611 5612unsigned fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5613 if (RetVT.SimpleTy != MVT::v2i32) 5614 return 0; 5615 if ((Subtarget->hasNEON())) { 5616 return fastEmitInst_ri(ARM::VSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5617 } 5618 return 0; 5619} 5620 5621unsigned fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5622 if (RetVT.SimpleTy != MVT::v4i32) 5623 return 0; 5624 if ((Subtarget->hasNEON())) { 5625 return fastEmitInst_ri(ARM::VSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5626 } 5627 return 0; 5628} 5629 5630unsigned fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5631 if (RetVT.SimpleTy != MVT::v1i64) 5632 return 0; 5633 if ((Subtarget->hasNEON())) { 5634 return fastEmitInst_ri(ARM::VSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5635 } 5636 return 0; 5637} 5638 5639unsigned fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5640 if (RetVT.SimpleTy != MVT::v2i64) 5641 return 0; 5642 if ((Subtarget->hasNEON())) { 5643 return fastEmitInst_ri(ARM::VSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5644 } 5645 return 0; 5646} 5647 5648unsigned fastEmit_ARMISD_VSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5649 switch (VT.SimpleTy) { 5650 case MVT::v8i8: return fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5651 case MVT::v16i8: return fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5652 case MVT::v4i16: return fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5653 case MVT::v8i16: return fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5654 case MVT::v2i32: return fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5655 case MVT::v4i32: return fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5656 case MVT::v1i64: return fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5657 case MVT::v2i64: return fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5658 default: return 0; 5659 } 5660} 5661 5662// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 5663 5664unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5665 if (RetVT.SimpleTy != MVT::i32) 5666 return 0; 5667 if ((!Subtarget->hasSlowVGETLNi32()) && (Subtarget->hasVFP2())) { 5668 return fastEmitInst_ri(ARM::VGETLNi32, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5669 } 5670 return 0; 5671} 5672 5673unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5674 switch (VT.SimpleTy) { 5675 case MVT::v2i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5676 default: return 0; 5677 } 5678} 5679 5680// FastEmit functions for ISD::SHL. 5681 5682unsigned fastEmit_ISD_SHL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5683 if (RetVT.SimpleTy != MVT::i32) 5684 return 0; 5685 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 5686 return fastEmitInst_ri(ARM::tLSLri, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 5687 } 5688 return 0; 5689} 5690 5691unsigned fastEmit_ISD_SHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5692 switch (VT.SimpleTy) { 5693 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); 5694 default: return 0; 5695 } 5696} 5697 5698// Top-level FastEmit function. 5699 5700unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override { 5701 if (VT == MVT::i32 && Predicate_mod_imm(imm1)) 5702 if (unsigned Reg = fastEmit_ri_Predicate_mod_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5703 return Reg; 5704 5705 if (VT == MVT::i32 && Predicate_imm0_7(imm1)) 5706 if (unsigned Reg = fastEmit_ri_Predicate_imm0_7(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5707 return Reg; 5708 5709 if (VT == MVT::i32 && Predicate_imm8_255(imm1)) 5710 if (unsigned Reg = fastEmit_ri_Predicate_imm8_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5711 return Reg; 5712 5713 if (VT == MVT::i32 && Predicate_imm0_255(imm1)) 5714 if (unsigned Reg = fastEmit_ri_Predicate_imm0_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5715 return Reg; 5716 5717 if (VT == MVT::i32 && Predicate_t2_so_imm(imm1)) 5718 if (unsigned Reg = fastEmit_ri_Predicate_t2_so_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5719 return Reg; 5720 5721 if (VT == MVT::i32 && Predicate_imm0_4095(imm1)) 5722 if (unsigned Reg = fastEmit_ri_Predicate_imm0_4095(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5723 return Reg; 5724 5725 if (VT == MVT::i32 && Predicate_imm1_31(imm1)) 5726 if (unsigned Reg = fastEmit_ri_Predicate_imm1_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5727 return Reg; 5728 5729 if (VT == MVT::i32 && Predicate_imm0_31(imm1)) 5730 if (unsigned Reg = fastEmit_ri_Predicate_imm0_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5731 return Reg; 5732 5733 if (VT == MVT::i32 && Predicate_shr_imm8(imm1)) 5734 if (unsigned Reg = fastEmit_ri_Predicate_shr_imm8(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5735 return Reg; 5736 5737 if (VT == MVT::i32 && Predicate_shr_imm16(imm1)) 5738 if (unsigned Reg = fastEmit_ri_Predicate_shr_imm16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5739 return Reg; 5740 5741 if (VT == MVT::i32 && Predicate_shr_imm32(imm1)) 5742 if (unsigned Reg = fastEmit_ri_Predicate_shr_imm32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5743 return Reg; 5744 5745 if (VT == MVT::i32 && Predicate_VectorIndex32(imm1)) 5746 if (unsigned Reg = fastEmit_ri_Predicate_VectorIndex32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 5747 return Reg; 5748 5749 switch (Opcode) { 5750 case ARMISD::PIC_ADD: return fastEmit_ARMISD_PIC_ADD_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5751 case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5752 case ARMISD::VGETLANEs: return fastEmit_ARMISD_VGETLANEs_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5753 case ARMISD::VGETLANEu: return fastEmit_ARMISD_VGETLANEu_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5754 case ARMISD::VQSHLs: return fastEmit_ARMISD_VQSHLs_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5755 case ARMISD::VQSHLsu: return fastEmit_ARMISD_VQSHLsu_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5756 case ARMISD::VQSHLu: return fastEmit_ARMISD_VQSHLu_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5757 case ARMISD::VRSHRs: return fastEmit_ARMISD_VRSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5758 case ARMISD::VRSHRu: return fastEmit_ARMISD_VRSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5759 case ARMISD::VSHL: return fastEmit_ARMISD_VSHL_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5760 case ARMISD::VSHRs: return fastEmit_ARMISD_VSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5761 case ARMISD::VSHRu: return fastEmit_ARMISD_VSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5762 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5763 case ISD::SHL: return fastEmit_ISD_SHL_ri(VT, RetVT, Op0, Op0IsKill, imm1); 5764 default: return 0; 5765 } 5766} 5767 5768// FastEmit functions for ARMISD::CMN. 5769 5770unsigned fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5771 if (RetVT.SimpleTy != MVT::isVoid) 5772 return 0; 5773 if ((!Subtarget->isThumb())) { 5774 return fastEmitInst_ri(ARM::CMNri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5775 } 5776 return 0; 5777} 5778 5779unsigned fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5780 switch (VT.SimpleTy) { 5781 case MVT::i32: return fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 5782 default: return 0; 5783 } 5784} 5785 5786// FastEmit functions for ARMISD::CMP. 5787 5788unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5789 if (RetVT.SimpleTy != MVT::isVoid) 5790 return 0; 5791 if ((!Subtarget->isThumb())) { 5792 return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5793 } 5794 return 0; 5795} 5796 5797unsigned fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5798 switch (VT.SimpleTy) { 5799 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 5800 default: return 0; 5801 } 5802} 5803 5804// FastEmit functions for ARMISD::CMPZ. 5805 5806unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5807 if (RetVT.SimpleTy != MVT::isVoid) 5808 return 0; 5809 if ((!Subtarget->isThumb())) { 5810 return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5811 } 5812 return 0; 5813} 5814 5815unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5816 switch (VT.SimpleTy) { 5817 case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 5818 default: return 0; 5819 } 5820} 5821 5822// FastEmit functions for ISD::ADD. 5823 5824unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5825 if (RetVT.SimpleTy != MVT::i32) 5826 return 0; 5827 if ((!Subtarget->isThumb())) { 5828 return fastEmitInst_ri(ARM::ADDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5829 } 5830 return 0; 5831} 5832 5833unsigned fastEmit_ISD_ADD_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5834 switch (VT.SimpleTy) { 5835 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 5836 default: return 0; 5837 } 5838} 5839 5840// FastEmit functions for ISD::AND. 5841 5842unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5843 if (RetVT.SimpleTy != MVT::i32) 5844 return 0; 5845 if ((!Subtarget->isThumb())) { 5846 return fastEmitInst_ri(ARM::ANDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5847 } 5848 return 0; 5849} 5850 5851unsigned fastEmit_ISD_AND_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5852 switch (VT.SimpleTy) { 5853 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 5854 default: return 0; 5855 } 5856} 5857 5858// FastEmit functions for ISD::OR. 5859 5860unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5861 if (RetVT.SimpleTy != MVT::i32) 5862 return 0; 5863 if ((!Subtarget->isThumb())) { 5864 return fastEmitInst_ri(ARM::ORRri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5865 } 5866 return 0; 5867} 5868 5869unsigned fastEmit_ISD_OR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5870 switch (VT.SimpleTy) { 5871 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 5872 default: return 0; 5873 } 5874} 5875 5876// FastEmit functions for ISD::SUB. 5877 5878unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5879 if (RetVT.SimpleTy != MVT::i32) 5880 return 0; 5881 if ((!Subtarget->isThumb())) { 5882 return fastEmitInst_ri(ARM::SUBri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5883 } 5884 return 0; 5885} 5886 5887unsigned fastEmit_ISD_SUB_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5888 switch (VT.SimpleTy) { 5889 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 5890 default: return 0; 5891 } 5892} 5893 5894// FastEmit functions for ISD::XOR. 5895 5896unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5897 if (RetVT.SimpleTy != MVT::i32) 5898 return 0; 5899 if ((!Subtarget->isThumb())) { 5900 return fastEmitInst_ri(ARM::EORri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5901 } 5902 return 0; 5903} 5904 5905unsigned fastEmit_ISD_XOR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5906 switch (VT.SimpleTy) { 5907 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 5908 default: return 0; 5909 } 5910} 5911 5912// Top-level FastEmit function. 5913 5914unsigned fastEmit_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5915 switch (Opcode) { 5916 case ARMISD::CMN: return fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 5917 case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 5918 case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 5919 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 5920 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 5921 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 5922 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 5923 case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 5924 default: return 0; 5925 } 5926} 5927 5928// FastEmit functions for ISD::ADD. 5929 5930unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5931 if (RetVT.SimpleTy != MVT::i32) 5932 return 0; 5933 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 5934 return fastEmitInst_ri(ARM::tADDi3, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 5935 } 5936 return 0; 5937} 5938 5939unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5940 switch (VT.SimpleTy) { 5941 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1); 5942 default: return 0; 5943 } 5944} 5945 5946// Top-level FastEmit function. 5947 5948unsigned fastEmit_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5949 switch (Opcode) { 5950 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1); 5951 default: return 0; 5952 } 5953} 5954 5955// FastEmit functions for ISD::ADD. 5956 5957unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5958 if (RetVT.SimpleTy != MVT::i32) 5959 return 0; 5960 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 5961 return fastEmitInst_ri(ARM::tADDi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 5962 } 5963 return 0; 5964} 5965 5966unsigned fastEmit_ISD_ADD_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5967 switch (VT.SimpleTy) { 5968 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(RetVT, Op0, Op0IsKill, imm1); 5969 default: return 0; 5970 } 5971} 5972 5973// Top-level FastEmit function. 5974 5975unsigned fastEmit_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5976 switch (Opcode) { 5977 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm8_255(VT, RetVT, Op0, Op0IsKill, imm1); 5978 default: return 0; 5979 } 5980} 5981 5982// FastEmit functions for ARMISD::CMP. 5983 5984unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5985 if (RetVT.SimpleTy != MVT::isVoid) 5986 return 0; 5987 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 5988 return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 5989 } 5990 return 0; 5991} 5992 5993unsigned fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5994 switch (VT.SimpleTy) { 5995 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1); 5996 default: return 0; 5997 } 5998} 5999 6000// FastEmit functions for ARMISD::CMPZ. 6001 6002unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6003 if (RetVT.SimpleTy != MVT::isVoid) 6004 return 0; 6005 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 6006 return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 6007 } 6008 return 0; 6009} 6010 6011unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6012 switch (VT.SimpleTy) { 6013 case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1); 6014 default: return 0; 6015 } 6016} 6017 6018// Top-level FastEmit function. 6019 6020unsigned fastEmit_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6021 switch (Opcode) { 6022 case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1); 6023 case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1); 6024 default: return 0; 6025 } 6026} 6027 6028// FastEmit functions for ARMISD::CMP. 6029 6030unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6031 if (RetVT.SimpleTy != MVT::isVoid) 6032 return 0; 6033 if ((Subtarget->isThumb2())) { 6034 return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1); 6035 } 6036 return 0; 6037} 6038 6039unsigned fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6040 switch (VT.SimpleTy) { 6041 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6042 default: return 0; 6043 } 6044} 6045 6046// FastEmit functions for ARMISD::CMPZ. 6047 6048unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6049 if (RetVT.SimpleTy != MVT::isVoid) 6050 return 0; 6051 if ((Subtarget->isThumb2())) { 6052 return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1); 6053 } 6054 return 0; 6055} 6056 6057unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6058 switch (VT.SimpleTy) { 6059 case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6060 default: return 0; 6061 } 6062} 6063 6064// FastEmit functions for ISD::ADD. 6065 6066unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6067 if (RetVT.SimpleTy != MVT::i32) 6068 return 0; 6069 if ((Subtarget->isThumb2())) { 6070 return fastEmitInst_ri(ARM::t2ADDri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1); 6071 } 6072 return 0; 6073} 6074 6075unsigned fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6076 switch (VT.SimpleTy) { 6077 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6078 default: return 0; 6079 } 6080} 6081 6082// FastEmit functions for ISD::AND. 6083 6084unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6085 if (RetVT.SimpleTy != MVT::i32) 6086 return 0; 6087 if ((Subtarget->isThumb2())) { 6088 return fastEmitInst_ri(ARM::t2ANDri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 6089 } 6090 return 0; 6091} 6092 6093unsigned fastEmit_ISD_AND_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6094 switch (VT.SimpleTy) { 6095 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6096 default: return 0; 6097 } 6098} 6099 6100// FastEmit functions for ISD::OR. 6101 6102unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6103 if (RetVT.SimpleTy != MVT::i32) 6104 return 0; 6105 if ((Subtarget->isThumb2())) { 6106 return fastEmitInst_ri(ARM::t2ORRri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 6107 } 6108 return 0; 6109} 6110 6111unsigned fastEmit_ISD_OR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6112 switch (VT.SimpleTy) { 6113 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6114 default: return 0; 6115 } 6116} 6117 6118// FastEmit functions for ISD::SUB. 6119 6120unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6121 if (RetVT.SimpleTy != MVT::i32) 6122 return 0; 6123 if ((Subtarget->isThumb2())) { 6124 return fastEmitInst_ri(ARM::t2SUBri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1); 6125 } 6126 return 0; 6127} 6128 6129unsigned fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6130 switch (VT.SimpleTy) { 6131 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6132 default: return 0; 6133 } 6134} 6135 6136// FastEmit functions for ISD::XOR. 6137 6138unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6139 if (RetVT.SimpleTy != MVT::i32) 6140 return 0; 6141 if ((Subtarget->isThumb2())) { 6142 return fastEmitInst_ri(ARM::t2EORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 6143 } 6144 return 0; 6145} 6146 6147unsigned fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6148 switch (VT.SimpleTy) { 6149 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6150 default: return 0; 6151 } 6152} 6153 6154// Top-level FastEmit function. 6155 6156unsigned fastEmit_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6157 switch (Opcode) { 6158 case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6159 case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6160 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6161 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6162 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6163 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6164 case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6165 default: return 0; 6166 } 6167} 6168 6169// FastEmit functions for ISD::ADD. 6170 6171unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6172 if (RetVT.SimpleTy != MVT::i32) 6173 return 0; 6174 if ((Subtarget->isThumb2())) { 6175 return fastEmitInst_ri(ARM::t2ADDri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1); 6176 } 6177 return 0; 6178} 6179 6180unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6181 switch (VT.SimpleTy) { 6182 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1); 6183 default: return 0; 6184 } 6185} 6186 6187// FastEmit functions for ISD::SUB. 6188 6189unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6190 if (RetVT.SimpleTy != MVT::i32) 6191 return 0; 6192 if ((Subtarget->isThumb2())) { 6193 return fastEmitInst_ri(ARM::t2SUBri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1); 6194 } 6195 return 0; 6196} 6197 6198unsigned fastEmit_ISD_SUB_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6199 switch (VT.SimpleTy) { 6200 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1); 6201 default: return 0; 6202 } 6203} 6204 6205// Top-level FastEmit function. 6206 6207unsigned fastEmit_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6208 switch (Opcode) { 6209 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1); 6210 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1); 6211 default: return 0; 6212 } 6213} 6214 6215// FastEmit functions for ISD::SHL. 6216 6217unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6218 if (RetVT.SimpleTy != MVT::i32) 6219 return 0; 6220 if ((Subtarget->isThumb2())) { 6221 return fastEmitInst_ri(ARM::t2LSLri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 6222 } 6223 return 0; 6224} 6225 6226unsigned fastEmit_ISD_SHL_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6227 switch (VT.SimpleTy) { 6228 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(RetVT, Op0, Op0IsKill, imm1); 6229 default: return 0; 6230 } 6231} 6232 6233// Top-level FastEmit function. 6234 6235unsigned fastEmit_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6236 switch (Opcode) { 6237 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_imm1_31(VT, RetVT, Op0, Op0IsKill, imm1); 6238 default: return 0; 6239 } 6240} 6241 6242// FastEmit functions for ISD::ROTR. 6243 6244unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6245 if (RetVT.SimpleTy != MVT::i32) 6246 return 0; 6247 if ((Subtarget->isThumb2())) { 6248 return fastEmitInst_ri(ARM::t2RORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 6249 } 6250 return 0; 6251} 6252 6253unsigned fastEmit_ISD_ROTR_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6254 switch (VT.SimpleTy) { 6255 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(RetVT, Op0, Op0IsKill, imm1); 6256 default: return 0; 6257 } 6258} 6259 6260// Top-level FastEmit function. 6261 6262unsigned fastEmit_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6263 switch (Opcode) { 6264 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1); 6265 default: return 0; 6266 } 6267} 6268 6269// FastEmit functions for ARMISD::VQRSHRNs. 6270 6271unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6272 if (RetVT.SimpleTy != MVT::v8i8) 6273 return 0; 6274 if ((Subtarget->hasNEON())) { 6275 return fastEmitInst_ri(ARM::VQRSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6276 } 6277 return 0; 6278} 6279 6280unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6281 switch (VT.SimpleTy) { 6282 case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 6283 default: return 0; 6284 } 6285} 6286 6287// FastEmit functions for ARMISD::VQRSHRNsu. 6288 6289unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6290 if (RetVT.SimpleTy != MVT::v8i8) 6291 return 0; 6292 if ((Subtarget->hasNEON())) { 6293 return fastEmitInst_ri(ARM::VQRSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6294 } 6295 return 0; 6296} 6297 6298unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6299 switch (VT.SimpleTy) { 6300 case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 6301 default: return 0; 6302 } 6303} 6304 6305// FastEmit functions for ARMISD::VQRSHRNu. 6306 6307unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6308 if (RetVT.SimpleTy != MVT::v8i8) 6309 return 0; 6310 if ((Subtarget->hasNEON())) { 6311 return fastEmitInst_ri(ARM::VQRSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6312 } 6313 return 0; 6314} 6315 6316unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6317 switch (VT.SimpleTy) { 6318 case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 6319 default: return 0; 6320 } 6321} 6322 6323// FastEmit functions for ARMISD::VQSHRNs. 6324 6325unsigned fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6326 if (RetVT.SimpleTy != MVT::v8i8) 6327 return 0; 6328 if ((Subtarget->hasNEON())) { 6329 return fastEmitInst_ri(ARM::VQSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6330 } 6331 return 0; 6332} 6333 6334unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6335 switch (VT.SimpleTy) { 6336 case MVT::v8i16: return fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 6337 default: return 0; 6338 } 6339} 6340 6341// FastEmit functions for ARMISD::VQSHRNsu. 6342 6343unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6344 if (RetVT.SimpleTy != MVT::v8i8) 6345 return 0; 6346 if ((Subtarget->hasNEON())) { 6347 return fastEmitInst_ri(ARM::VQSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6348 } 6349 return 0; 6350} 6351 6352unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6353 switch (VT.SimpleTy) { 6354 case MVT::v8i16: return fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 6355 default: return 0; 6356 } 6357} 6358 6359// FastEmit functions for ARMISD::VQSHRNu. 6360 6361unsigned fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6362 if (RetVT.SimpleTy != MVT::v8i8) 6363 return 0; 6364 if ((Subtarget->hasNEON())) { 6365 return fastEmitInst_ri(ARM::VQSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6366 } 6367 return 0; 6368} 6369 6370unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6371 switch (VT.SimpleTy) { 6372 case MVT::v8i16: return fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 6373 default: return 0; 6374 } 6375} 6376 6377// FastEmit functions for ARMISD::VRSHRN. 6378 6379unsigned fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6380 if (RetVT.SimpleTy != MVT::v8i8) 6381 return 0; 6382 if ((Subtarget->hasNEON())) { 6383 return fastEmitInst_ri(ARM::VRSHRNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6384 } 6385 return 0; 6386} 6387 6388unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6389 switch (VT.SimpleTy) { 6390 case MVT::v8i16: return fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 6391 default: return 0; 6392 } 6393} 6394 6395// Top-level FastEmit function. 6396 6397unsigned fastEmit_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6398 switch (Opcode) { 6399 case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 6400 case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 6401 case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 6402 case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 6403 case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 6404 case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 6405 case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 6406 default: return 0; 6407 } 6408} 6409 6410// FastEmit functions for ARMISD::VQRSHRNs. 6411 6412unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6413 if (RetVT.SimpleTy != MVT::v4i16) 6414 return 0; 6415 if ((Subtarget->hasNEON())) { 6416 return fastEmitInst_ri(ARM::VQRSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6417 } 6418 return 0; 6419} 6420 6421unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6422 switch (VT.SimpleTy) { 6423 case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 6424 default: return 0; 6425 } 6426} 6427 6428// FastEmit functions for ARMISD::VQRSHRNsu. 6429 6430unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6431 if (RetVT.SimpleTy != MVT::v4i16) 6432 return 0; 6433 if ((Subtarget->hasNEON())) { 6434 return fastEmitInst_ri(ARM::VQRSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6435 } 6436 return 0; 6437} 6438 6439unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6440 switch (VT.SimpleTy) { 6441 case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 6442 default: return 0; 6443 } 6444} 6445 6446// FastEmit functions for ARMISD::VQRSHRNu. 6447 6448unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6449 if (RetVT.SimpleTy != MVT::v4i16) 6450 return 0; 6451 if ((Subtarget->hasNEON())) { 6452 return fastEmitInst_ri(ARM::VQRSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6453 } 6454 return 0; 6455} 6456 6457unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6458 switch (VT.SimpleTy) { 6459 case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 6460 default: return 0; 6461 } 6462} 6463 6464// FastEmit functions for ARMISD::VQSHRNs. 6465 6466unsigned fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6467 if (RetVT.SimpleTy != MVT::v4i16) 6468 return 0; 6469 if ((Subtarget->hasNEON())) { 6470 return fastEmitInst_ri(ARM::VQSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6471 } 6472 return 0; 6473} 6474 6475unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6476 switch (VT.SimpleTy) { 6477 case MVT::v4i32: return fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 6478 default: return 0; 6479 } 6480} 6481 6482// FastEmit functions for ARMISD::VQSHRNsu. 6483 6484unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6485 if (RetVT.SimpleTy != MVT::v4i16) 6486 return 0; 6487 if ((Subtarget->hasNEON())) { 6488 return fastEmitInst_ri(ARM::VQSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6489 } 6490 return 0; 6491} 6492 6493unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6494 switch (VT.SimpleTy) { 6495 case MVT::v4i32: return fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 6496 default: return 0; 6497 } 6498} 6499 6500// FastEmit functions for ARMISD::VQSHRNu. 6501 6502unsigned fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6503 if (RetVT.SimpleTy != MVT::v4i16) 6504 return 0; 6505 if ((Subtarget->hasNEON())) { 6506 return fastEmitInst_ri(ARM::VQSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6507 } 6508 return 0; 6509} 6510 6511unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6512 switch (VT.SimpleTy) { 6513 case MVT::v4i32: return fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 6514 default: return 0; 6515 } 6516} 6517 6518// FastEmit functions for ARMISD::VRSHRN. 6519 6520unsigned fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6521 if (RetVT.SimpleTy != MVT::v4i16) 6522 return 0; 6523 if ((Subtarget->hasNEON())) { 6524 return fastEmitInst_ri(ARM::VRSHRNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6525 } 6526 return 0; 6527} 6528 6529unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6530 switch (VT.SimpleTy) { 6531 case MVT::v4i32: return fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 6532 default: return 0; 6533 } 6534} 6535 6536// Top-level FastEmit function. 6537 6538unsigned fastEmit_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6539 switch (Opcode) { 6540 case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 6541 case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 6542 case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 6543 case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 6544 case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 6545 case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 6546 case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 6547 default: return 0; 6548 } 6549} 6550 6551// FastEmit functions for ARMISD::VQRSHRNs. 6552 6553unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6554 if (RetVT.SimpleTy != MVT::v2i32) 6555 return 0; 6556 if ((Subtarget->hasNEON())) { 6557 return fastEmitInst_ri(ARM::VQRSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6558 } 6559 return 0; 6560} 6561 6562unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6563 switch (VT.SimpleTy) { 6564 case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 6565 default: return 0; 6566 } 6567} 6568 6569// FastEmit functions for ARMISD::VQRSHRNsu. 6570 6571unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6572 if (RetVT.SimpleTy != MVT::v2i32) 6573 return 0; 6574 if ((Subtarget->hasNEON())) { 6575 return fastEmitInst_ri(ARM::VQRSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6576 } 6577 return 0; 6578} 6579 6580unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6581 switch (VT.SimpleTy) { 6582 case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 6583 default: return 0; 6584 } 6585} 6586 6587// FastEmit functions for ARMISD::VQRSHRNu. 6588 6589unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6590 if (RetVT.SimpleTy != MVT::v2i32) 6591 return 0; 6592 if ((Subtarget->hasNEON())) { 6593 return fastEmitInst_ri(ARM::VQRSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6594 } 6595 return 0; 6596} 6597 6598unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6599 switch (VT.SimpleTy) { 6600 case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 6601 default: return 0; 6602 } 6603} 6604 6605// FastEmit functions for ARMISD::VQSHRNs. 6606 6607unsigned fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6608 if (RetVT.SimpleTy != MVT::v2i32) 6609 return 0; 6610 if ((Subtarget->hasNEON())) { 6611 return fastEmitInst_ri(ARM::VQSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6612 } 6613 return 0; 6614} 6615 6616unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6617 switch (VT.SimpleTy) { 6618 case MVT::v2i64: return fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 6619 default: return 0; 6620 } 6621} 6622 6623// FastEmit functions for ARMISD::VQSHRNsu. 6624 6625unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6626 if (RetVT.SimpleTy != MVT::v2i32) 6627 return 0; 6628 if ((Subtarget->hasNEON())) { 6629 return fastEmitInst_ri(ARM::VQSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6630 } 6631 return 0; 6632} 6633 6634unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6635 switch (VT.SimpleTy) { 6636 case MVT::v2i64: return fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 6637 default: return 0; 6638 } 6639} 6640 6641// FastEmit functions for ARMISD::VQSHRNu. 6642 6643unsigned fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6644 if (RetVT.SimpleTy != MVT::v2i32) 6645 return 0; 6646 if ((Subtarget->hasNEON())) { 6647 return fastEmitInst_ri(ARM::VQSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6648 } 6649 return 0; 6650} 6651 6652unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6653 switch (VT.SimpleTy) { 6654 case MVT::v2i64: return fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 6655 default: return 0; 6656 } 6657} 6658 6659// FastEmit functions for ARMISD::VRSHRN. 6660 6661unsigned fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6662 if (RetVT.SimpleTy != MVT::v2i32) 6663 return 0; 6664 if ((Subtarget->hasNEON())) { 6665 return fastEmitInst_ri(ARM::VRSHRNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6666 } 6667 return 0; 6668} 6669 6670unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6671 switch (VT.SimpleTy) { 6672 case MVT::v2i64: return fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 6673 default: return 0; 6674 } 6675} 6676 6677// Top-level FastEmit function. 6678 6679unsigned fastEmit_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6680 switch (Opcode) { 6681 case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 6682 case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 6683 case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 6684 case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 6685 case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 6686 case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 6687 case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 6688 default: return 0; 6689 } 6690} 6691 6692// FastEmit functions for ARMISD::VDUPLANE. 6693 6694unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6695 if (RetVT.SimpleTy != MVT::v16i8) 6696 return 0; 6697 if ((Subtarget->hasNEON())) { 6698 return fastEmitInst_ri(ARM::VDUPLN8q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6699 } 6700 return 0; 6701} 6702 6703unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6704 if (RetVT.SimpleTy != MVT::v8i16) 6705 return 0; 6706 if ((Subtarget->hasNEON())) { 6707 return fastEmitInst_ri(ARM::VDUPLN16q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6708 } 6709 return 0; 6710} 6711 6712unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6713 if (RetVT.SimpleTy != MVT::v4i32) 6714 return 0; 6715 if ((Subtarget->hasNEON())) { 6716 return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6717 } 6718 return 0; 6719} 6720 6721unsigned fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6722 switch (VT.SimpleTy) { 6723 case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1); 6724 case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1); 6725 case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1); 6726 default: return 0; 6727 } 6728} 6729 6730// Top-level FastEmit function. 6731 6732unsigned fastEmit_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6733 switch (Opcode) { 6734 case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(VT, RetVT, Op0, Op0IsKill, imm1); 6735 default: return 0; 6736 } 6737} 6738 6739// FastEmit functions for ISD::Constant. 6740 6741unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) { 6742 if (RetVT.SimpleTy != MVT::i32) 6743 return 0; 6744 if ((Subtarget->isThumb()) && (Subtarget->useMovt(*MF))) { 6745 return fastEmitInst_i(ARM::t2MOVi32imm, &ARM::rGPRRegClass, imm0); 6746 } 6747 return 0; 6748} 6749 6750unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) { 6751 switch (VT.SimpleTy) { 6752 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0); 6753 default: return 0; 6754 } 6755} 6756 6757// Top-level FastEmit function. 6758 6759unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override { 6760 switch (Opcode) { 6761 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0); 6762 default: return 0; 6763 } 6764} 6765 6766