1 /** @file 2 * 3 * Copyright (c) 2011-2013, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #ifndef __AARCH64_MMU_H_ 16 #define __AARCH64_MMU_H_ 17 18 // 19 // Memory Attribute Indirection register Definitions 20 // 21 #define MAIR_ATTR_DEVICE_MEMORY 0x0ULL 22 #define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL 23 #define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL 24 #define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL 25 26 #define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8)) 27 28 // 29 // Long-descriptor Translation Table format 30 // 31 32 // Return the smallest offset from the table level. 33 // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0 34 #define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9)) 35 36 #define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level)) 37 38 // Get the associated entry in the given Translation Table 39 #define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \ 40 ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64))) 41 42 // Return the smallest address granularity from the table level. 43 // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0 44 #define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel)) 45 46 #define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \ 47 ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64)))) 48 49 // There are 512 entries per table when 4K Granularity 50 #define TT_ENTRY_COUNT 512 51 #define TT_ALIGNMENT_BLOCK_ENTRY BIT12 52 #define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12 53 54 #define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12) 55 #define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12) 56 57 #define TT_TYPE_MASK 0x3 58 #define TT_TYPE_TABLE_ENTRY 0x3 59 #define TT_TYPE_BLOCK_ENTRY 0x1 60 #define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3 61 62 #define TT_ATTR_INDX_MASK (0x7 << 2) 63 #define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2) 64 #define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2) 65 #define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2) 66 #define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2) 67 68 #define TT_AP_MASK (0x3UL << 6) 69 #define TT_AP_NO_RW (0x0UL << 6) 70 #define TT_AP_RW_RW (0x1UL << 6) 71 #define TT_AP_NO_RO (0x2UL << 6) 72 #define TT_AP_RO_RO (0x3UL << 6) 73 74 #define TT_NS BIT5 75 #define TT_AF BIT10 76 77 #define TT_SH_NON_SHAREABLE (0x0 << 8) 78 #define TT_SH_OUTER_SHAREABLE (0x2 << 8) 79 #define TT_SH_INNER_SHAREABLE (0x3 << 8) 80 #define TT_SH_MASK (0x3 << 8) 81 82 #define TT_PXN_MASK BIT53 83 #define TT_UXN_MASK BIT54 // EL1&0 84 #define TT_XN_MASK BIT54 // EL2 / EL3 85 86 #define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2)) 87 88 #define TT_TABLE_PXN BIT59 89 #define TT_TABLE_UXN BIT60 // EL1&0 90 #define TT_TABLE_XN BIT60 // EL2 / EL3 91 #define TT_TABLE_NS BIT63 92 93 #define TT_TABLE_AP_MASK (BIT62 | BIT61) 94 #define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61) 95 #define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61) 96 #define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61) 97 98 // 99 // Translation Control Register 100 // 101 #define TCR_T0SZ_MASK 0x3FUL 102 103 #define TCR_PS_4GB (0UL << 16) 104 #define TCR_PS_64GB (1UL << 16) 105 #define TCR_PS_1TB (2UL << 16) 106 #define TCR_PS_4TB (3UL << 16) 107 #define TCR_PS_16TB (4UL << 16) 108 #define TCR_PS_256TB (5UL << 16) 109 110 #define TCR_TG0_4KB (0UL << 14) 111 #define TCR_TG1_4KB (2UL << 30) 112 113 #define TCR_IPS_4GB (0ULL << 32) 114 #define TCR_IPS_64GB (1ULL << 32) 115 #define TCR_IPS_1TB (2ULL << 32) 116 #define TCR_IPS_4TB (3ULL << 32) 117 #define TCR_IPS_16TB (4ULL << 32) 118 #define TCR_IPS_256TB (5ULL << 32) 119 120 #define TCR_EPD1 (1UL << 23) 121 122 #define TTBR_ASID_FIELD (48) 123 #define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD) 124 #define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits 125 126 #define TCR_EL1_T0SZ_FIELD (0) 127 #define TCR_EL1_EPD0_FIELD (7) 128 #define TCR_EL1_IRGN0_FIELD (8) 129 #define TCR_EL1_ORGN0_FIELD (10) 130 #define TCR_EL1_SH0_FIELD (12) 131 #define TCR_EL1_TG0_FIELD (14) 132 #define TCR_EL1_T1SZ_FIELD (16) 133 #define TCR_EL1_A1_FIELD (22) 134 #define TCR_EL1_EPD1_FIELD (23) 135 #define TCR_EL1_IRGN1_FIELD (24) 136 #define TCR_EL1_ORGN1_FIELD (26) 137 #define TCR_EL1_SH1_FIELD (28) 138 #define TCR_EL1_TG1_FIELD (30) 139 #define TCR_EL1_IPS_FIELD (32) 140 #define TCR_EL1_AS_FIELD (36) 141 #define TCR_EL1_TBI0_FIELD (37) 142 #define TCR_EL1_TBI1_FIELD (38) 143 #define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD) 144 #define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD) 145 #define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD) 146 #define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD) 147 #define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD) 148 #define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD) 149 #define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD) 150 #define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD) 151 #define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD) 152 #define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD) 153 #define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD) 154 #define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD) 155 #define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD) 156 #define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD) 157 #define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD) 158 #define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD) 159 #define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD) 160 161 162 #define TCR_EL23_T0SZ_FIELD (0) 163 #define TCR_EL23_IRGN0_FIELD (8) 164 #define TCR_EL23_ORGN0_FIELD (10) 165 #define TCR_EL23_SH0_FIELD (12) 166 #define TCR_EL23_TG0_FIELD (14) 167 #define TCR_EL23_PS_FIELD (16) 168 #define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD) 169 #define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD) 170 #define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD) 171 #define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD) 172 #define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD) 173 #define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD) 174 175 176 #define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10) 177 #define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10) 178 #define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10) 179 #define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10) 180 181 #define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8) 182 #define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8) 183 #define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8) 184 #define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8) 185 186 #define TCR_SH_NON_SHAREABLE (0x0UL << 12) 187 #define TCR_SH_OUTER_SHAREABLE (0x2UL << 12) 188 #define TCR_SH_INNER_SHAREABLE (0x3UL << 12) 189 190 #define TCR_PASZ_32BITS_4GB (0x0UL) 191 #define TCR_PASZ_36BITS_64GB (0x1UL) 192 #define TCR_PASZ_40BITS_1TB (0x2UL) 193 #define TCR_PASZ_42BITS_4TB (0x3UL) 194 #define TCR_PASZ_44BITS_16TB (0x4UL) 195 #define TCR_PASZ_48BITS_256TB (0x5UL) 196 197 // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit 198 // Virtual address range for 512GB of virtual space sets T*SZ to 25 199 #define INPUT_ADDRESS_SIZE_TO_TxSZ(a) (64 - a) 200 201 // Uses LPAE Page Table format 202 203 #endif // __AARCH64_MMU_H_ 204 205