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1/** @file
2*
3*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
4*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
5*  Copyright (c) 2016, Linaro Limited. All rights reserved.
6*
7*  This program and the accompanying materials
8*  are licensed and made available under the terms and conditions of the BSD License
9*  which accompanies this distribution.  The full text of the license may be found at
10*  http://opensource.org/licenses/bsd-license.php
11*
12*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14*
15*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
16*
17**/
18
19//#include "ArmPlatform.h"
20Scope(_SB)
21{
22  // PCIe Root bus
23  Device (PCI0)
24  {
25    Name (_HID, "HISI0080") // PCI Express Root Bridge
26    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
27    Name(_SEG, 0) // Segment of this Root complex
28    Name(_BBN, 0) // Base Bus Number
29    Name(_CCA, 1)
30    Method (_CRS, 0, Serialized) { // Root complex resources
31      Name (RBUF, ResourceTemplate () {
32        WordBusNumber ( // Bus numbers assigned to this root
33          ResourceProducer, MinFixed, MaxFixed, PosDecode,
34          0, // AddressGranularity
35          0x0, // AddressMinimum - Minimum Bus Number
36          0x1f, // AddressMaximum - Maximum Bus Number
37          0, // AddressTranslation - Set to 0
38          0x20 // RangeLength - Number of Busses
39        )
40        QWordMemory ( // 64-bit BAR Windows
41          ResourceProducer,
42          PosDecode,
43          MinFixed,
44          MaxFixed,
45          Cacheable,
46          ReadWrite,
47          0x0, // Granularity
48          0xb2000000, // Min Base Address pci address
49          0xb7feffff, // Max Base Address
50          0x0, // Translate
51          0x5ff0000 // Length
52        )
53        QWordIO (
54          ResourceProducer,
55          MinFixed,
56          MaxFixed,
57          PosDecode,
58          EntireRange,
59          0x0, // Granularity
60          0x0, // Min Base Address
61          0xffff, // Max Base Address
62          0xb7ff0000, // Translate
63          0x10000 // Length
64        )
65      }) // Name(RBUF)
66      Return (RBUF)
67    } // Method(_CRS)
68
69    Device (RES0)
70    {
71      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
72      Name (_CRS, ResourceTemplate (){
73        Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)
74      })
75    }
76
77    OperationRegion(SCTR, SystemMemory, 0xa009131c, 4)
78    Field(SCTR, AnyAcc, NoLock, Preserve) {
79      LSTA, 32,
80    }
81    Method(_DSM, 0x4, Serialized) {
82      If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
83        switch(ToInteger(Arg2))
84        {
85          // Function 0: Return LinkStatus
86          case(0) {
87              Store (0, Local0)
88              Store (LSTA, Local0)
89              Return (Local0)
90          }
91          default {
92          }
93        }
94      }
95      // If not one of the function identifiers we recognize, then return a buffer
96      // with bit 0 set to 0 indicating no functions supported.
97      return(Buffer(){0})
98    }
99  } // Device(PCI0)
100
101  // PCIe Root bus
102  Device (PCI1)
103  {
104    Name (_HID, "HISI0080") // PCI Express Root Bridge
105    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
106    Name(_SEG, 1) // Segment of this Root complex
107    Name(_BBN, 0xe0) // Base Bus Number
108    Name(_CCA, 1)
109    Method (_CRS, 0, Serialized) { // Root complex resources
110      Name (RBUF, ResourceTemplate () {
111        WordBusNumber ( // Bus numbers assigned to this root
112          ResourceProducer, MinFixed, MaxFixed, PosDecode,
113          0, // AddressGranularity
114          0xe0, // AddressMinimum - Minimum Bus Number
115          0xff, // AddressMaximum - Maximum Bus Number
116          0,   // AddressTranslation - Set to 0
117          0x20 // RangeLength - Number of Busses
118        )
119        QWordMemory ( // 64-bit BAR Windows
120          ResourceProducer,
121          PosDecode,
122          MinFixed,
123          MaxFixed,
124          Cacheable,
125          ReadWrite,
126          0x0, // Granularity
127          0xb8000000, // Min Base Address pci address
128          0xbdfeffff, // Max Base Address
129          0x0, // Translate
130          0x5ff0000 // Length
131        )
132        QWordIO (
133          ResourceProducer,
134          MinFixed,
135          MaxFixed,
136          PosDecode,
137          EntireRange,
138          0x0, // Granularity
139          0x0, // Min Base Address
140          0xffff, // Max Base Address
141          0xbdff0000, // Translate
142          0x10000 // Length
143        )
144      }) // Name(RBUF)
145      Return (RBUF)
146    } // Method(_CRS)
147
148    Device (RES1)
149    {
150      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
151      Name (_CRS, ResourceTemplate (){
152        Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)
153      })
154    }
155
156    OperationRegion(SCTR, SystemMemory, 0xa020131c, 4)
157    Field(SCTR, AnyAcc, NoLock, Preserve) {
158      LSTA, 32,
159    }
160    Method(_DSM, 0x4, Serialized) {
161      If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
162
163        switch(ToInteger(Arg2))
164        {
165          // Function 0: Return LinkStatus
166          case(0) {
167              Store (0, Local0)
168              Store (LSTA, Local0)
169              Return (Local0)
170          }
171          default {
172          }
173        }
174      }
175      // If not one of the function identifiers we recognize, then return a buffer
176      // with bit 0 set to 0 indicating no functions supported.
177      return(Buffer(){0})
178    }
179  } // Device(PCI1)
180
181  // PCIe Root bus
182  Device (PCI2)
183  {
184    Name (_HID, "HISI0080") // PCI Express Root Bridge
185    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
186    Name(_SEG, 2) // Segment of this Root complex
187    Name(_BBN, 0x80) // Base Bus Number
188    Name(_CCA, 1)
189    Method (_CRS, 0, Serialized) { // Root complex resources
190      Name (RBUF, ResourceTemplate () {
191        WordBusNumber ( // Bus numbers assigned to this root
192          ResourceProducer, MinFixed, MaxFixed, PosDecode,
193          0, // AddressGranularity
194          0x80, // AddressMinimum - Minimum Bus Number
195          0x9f, // AddressMaximum - Maximum Bus Number
196          0, // AddressTranslation - Set to 0
197          0x20 // RangeLength - Number of Busses
198        )
199        QWordMemory ( // 64-bit BAR Windows
200          ResourceProducer,
201          PosDecode,
202          MinFixed,
203          MaxFixed,
204          Cacheable,
205          ReadWrite,
206          0x0, // Granularity
207          0xaa000000, // Min Base Address
208          0xaffeffff, // Max Base Address
209          0x0, // Translate
210          0x5ff0000 // Length
211        )
212        QWordIO (
213          ResourceProducer,
214          MinFixed,
215          MaxFixed,
216          PosDecode,
217          EntireRange,
218          0x0, // Granularity
219          0x0, // Min Base Address
220          0xffff, // Max Base Address
221          0xafff0000, // Translate
222          0x10000 // Length
223        )
224      }) // Name(RBUF)
225      Return (RBUF)
226    } // Method(_CRS)
227
228    Device (RES2)
229    {
230      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
231      Name (_CRS, ResourceTemplate (){
232        Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)
233      })
234    }
235
236    OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4)
237    Field(SCTR, AnyAcc, NoLock, Preserve) {
238      LSTA, 32,
239    }
240    Method(_DSM, 0x4, Serialized) {
241      If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949")))
242      {
243        switch(ToInteger(Arg2))
244        {
245          // Function 0: Return LinkStatus
246          case(0) {
247              Store (0, Local0)
248              Store (LSTA, Local0)
249              Return (Local0)
250          }
251          default {
252          }
253        }
254      }
255      // If not one of the function identifiers we recognize, then return a buffer
256      // with bit 0 set to 0 indicating no functions supported.
257      return(Buffer(){0})
258    }
259  } // Device(PCI2)
260}
261
262