1 /** @file
2 *
3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
4 * Copyright (c) 2016, Linaro Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16
17 #include <Uefi.h>
18 #include <PiPei.h>
19 #include <Library/DebugLib.h>
20 #include <Library/PcdLib.h>
21 #include <Library/IoLib.h>
22 #include <Library/CacheMaintenanceLib.h>
23
24 #include <PlatformArch.h>
25 #include <Library/PlatformSysCtrlLib.h>
26
27 #include <Library/OemMiscLib.h>
28 #include <Library/OemAddressMapLib.h>
29 #include <Library/ArmLib.h>
30
31 #define PERI_SUBCTRL_BASE (0x40000000)
32 #define MDIO_SUBCTRL_BASE (0x60000000)
33 #define PCIE2_SUBCTRL_BASE (0xA0000000)
34 #define PCIE0_SUBCTRL_BASE (0xB0000000)
35 #define ALG_BASE (0xD0000000)
36
37 #define SC_BROADCAST_EN_REG (0x16220)
38 #define SC_BROADCAST_SCL1_ADDR0_REG (0x16230)
39 #define SC_BROADCAST_SCL1_ADDR1_REG (0x16234)
40 #define SC_BROADCAST_SCL2_ADDR0_REG (0x16238)
41 #define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C)
42 #define SC_BROADCAST_SCL3_ADDR0_REG (0x16240)
43 #define SC_BROADCAST_SCL3_ADDR1_REG (0x16244)
44 #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000)
45 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010)
46 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014)
47 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018)
48 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C)
49 #define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200)
50 #define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0)
51 #define SC_TM_CLKEN0_REG (0x2050)
52
53 #define SC_TM_CLKEN0_REG_VALUE (0x3)
54 #define SC_BROADCAST_EN_REG_VALUE (0x7)
55 #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0)
56 #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260)
57 #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260)
58 #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400)
59 #define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7)
60 #define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0)
61 #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27)
62 #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F)
63 #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77)
64 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033)
65 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c)
66 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d)
67 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035)
68 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e)
69
PlatformTimerStart(VOID)70 VOID PlatformTimerStart (VOID)
71 {
72 // Timer0 clock enable
73 MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE);
74 }
75
QResetAp(VOID)76 void QResetAp(VOID)
77 {
78 MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
79 (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
80 ArmDataSynchronizationBarrier ();
81 ArmInstructionSynchronizationBarrier ();
82
83 //SCCL A
84 if (!PcdGet64 (PcdTrustedFirmwareEnable))
85 {
86 StartupAp();
87 }
88 }
89
90
91 EFI_STATUS
92 EFIAPI
EarlyConfigEntry(IN EFI_PEI_FILE_HANDLE FileHandle,IN CONST EFI_PEI_SERVICES ** PeiServices)93 EarlyConfigEntry (
94 IN EFI_PEI_FILE_HANDLE FileHandle,
95 IN CONST EFI_PEI_SERVICES **PeiServices
96 )
97 {
98 DEBUG((EFI_D_INFO,"SMMU CONFIG........."));
99 (VOID)SmmuConfigForOS();
100 DEBUG((EFI_D_INFO,"Done\n"));
101
102
103 DEBUG((EFI_D_INFO,"AP CONFIG........."));
104 (VOID)QResetAp();
105 DEBUG((EFI_D_INFO,"Done\n"));
106
107 DEBUG((EFI_D_INFO,"MN CONFIG........."));
108 (VOID)MN_CONFIG();
109 DEBUG((EFI_D_INFO,"Done\n"));
110
111 if(OemIsMpBoot())
112 {
113 DEBUG((EFI_D_INFO,"Event Broadcast CONFIG........."));
114 //EVENT broadcast
115 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
116 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
117 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
118 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
119 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
120 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
121 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
122
123 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
124 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
125 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
126 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
127 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
128 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
129 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
130
131 MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
132 MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
133 MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
134 MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
135 MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
136 MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
137 MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
138
139 MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
140 MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
141 MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
142 MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
143 MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
144 MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
145 MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
146
147 DEBUG((EFI_D_INFO,"Done\n"));
148 }
149
150 DEBUG((EFI_D_INFO,"PCIE RAM Address CONFIG........."));
151
152 if(OemIsMpBoot())
153 {
154 MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0);
155 MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
156 MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1);
157 MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0);
158 MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1);
159 }
160
161 else
162 {
163 MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_REMAP_CTRL_REG, PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0);
164 MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2);
165 MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0);
166 MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
167 MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0);
168 }
169
170 DEBUG((EFI_D_INFO,"Done\n"));
171
172 MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_REG_VALUE);
173
174 DEBUG((EFI_D_INFO,"Timer CONFIG........."));
175 PlatformTimerStart ();
176 DEBUG((EFI_D_INFO,"Done\n"));
177
178 return EFI_SUCCESS;
179 }
180
181