1 /** @file 2 Public include file for I/O APIC library. 3 4 I/O APIC library assumes I/O APIC is enabled. It does not 5 handles cases where I/O APIC is disabled. 6 7 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR> 8 This program and the accompanying materials 9 are licensed and made available under the terms and conditions of the BSD License 10 which accompanies this distribution. The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php 12 13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 15 16 **/ 17 #ifndef __IO_APIC_LIB_H__ 18 #define __IO_APIC_LIB_H__ 19 20 /** 21 Read a 32-bit I/O APIC register. 22 23 If Index is >= 0x100, then ASSERT(). 24 25 @param Index Specifies the I/O APIC register to read. 26 27 @return The 32-bit value read from the I/O APIC register specified by Index. 28 **/ 29 UINT32 30 EFIAPI 31 IoApicRead ( 32 IN UINTN Index 33 ); 34 35 /** 36 Write a 32-bit I/O APIC register. 37 38 If Index is >= 0x100, then ASSERT(). 39 40 @param Index Specifies the I/O APIC register to write. 41 @param Value Specifies the value to write to the I/O APIC register specified by Index. 42 43 @return The 32-bit value written to I/O APIC register specified by Index. 44 **/ 45 UINT32 46 EFIAPI 47 IoApicWrite ( 48 IN UINTN Index, 49 IN UINT32 Value 50 ); 51 52 /** 53 Set the interrupt mask of an I/O APIC interrupt. 54 55 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 56 57 @param Irq Specifies the I/O APIC interrupt to enable or disable. 58 @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq. 59 If FALSE, then disable the I/O APIC interrupt specified by Irq. 60 **/ 61 VOID 62 EFIAPI 63 IoApicEnableInterrupt ( 64 IN UINTN Irq, 65 IN BOOLEAN Enable 66 ); 67 68 /** 69 Configures an I/O APIC interrupt. 70 71 Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical 72 mode to the Local APIC of the currntly executing CPU. The default state of the 73 entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must 74 be used to enable(unmask) the I/O APIC Interrupt. 75 76 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 77 If Vector >= 0x100, then ASSERT(). 78 If DeliveryMode is not supported, then ASSERT(). 79 80 @param Irq Specifies the I/O APIC interrupt to initialize. 81 @param Vector The 8-bit interrupt vector associated with the I/O APIC 82 Interrupt. Must be in the range 0x10..0xFE. 83 @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC 84 interrupt is handled. The only supported values are: 85 0: IO_APIC_DELIVERY_MODE_FIXED 86 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY 87 2: IO_APIC_DELIVERY_MODE_SMI 88 4: IO_APIC_DELIVERY_MODE_NMI 89 5: IO_APIC_DELIVERY_MODE_INIT 90 7: IO_APIC_DELIVERY_MODE_EXTINT 91 @param LevelTriggered TRUE specifies a level triggered interrupt. 92 FALSE specifies an edge triggered interrupt. 93 @param AssertionLevel TRUE specified an active high interrupt. 94 FALSE specifies an active low interrupt. 95 **/ 96 VOID 97 EFIAPI 98 IoApicConfigureInterrupt ( 99 IN UINTN Irq, 100 IN UINTN Vector, 101 IN UINTN DeliveryMode, 102 IN BOOLEAN LevelTriggered, 103 IN BOOLEAN AssertionLevel 104 ); 105 #endif 106