1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Global Instruction Selector for the Mips target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_GLOBALISEL_PREDICATE_BITSET 10const unsigned MAX_SUBTARGET_PREDICATES = 41; 11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; 12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET 13 14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL 15 mutable MatcherState State; 16 typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; 17 typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const; 18 const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo; 19 static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; 20 static MipsInstructionSelector::CustomRendererFn CustomRenderers[]; 21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; 22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; 23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; 24 const int64_t *getMatchTable() const override; 25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override; 26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL 27 28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT 29, State(0), 30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) 31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT 32 33#ifdef GET_GLOBALISEL_IMPL 34// Bits for subtarget features that participate in instruction matching. 35enum SubtargetFeatureBits : uint8_t { 36 Feature_HasMips2Bit = 7, 37 Feature_HasMips3Bit = 16, 38 Feature_HasMips4_32Bit = 26, 39 Feature_NotMips4_32Bit = 27, 40 Feature_HasMips4_32r2Bit = 17, 41 Feature_HasMips32Bit = 3, 42 Feature_HasMips32r2Bit = 6, 43 Feature_HasMips32r6Bit = 28, 44 Feature_NotMips32r6Bit = 4, 45 Feature_IsGP64bitBit = 21, 46 Feature_IsPTR64bitBit = 23, 47 Feature_HasMips64Bit = 24, 48 Feature_HasMips64r2Bit = 22, 49 Feature_HasMips64r6Bit = 29, 50 Feature_NotMips64r6Bit = 5, 51 Feature_InMips16ModeBit = 30, 52 Feature_NotInMips16ModeBit = 0, 53 Feature_HasCnMipsBit = 25, 54 Feature_NotCnMipsBit = 8, 55 Feature_IsN64Bit = 37, 56 Feature_RelocNotPICBit = 9, 57 Feature_RelocPICBit = 36, 58 Feature_NoNaNsFPMathBit = 20, 59 Feature_HasStdEncBit = 1, 60 Feature_NotDSPBit = 11, 61 Feature_InMicroMipsBit = 34, 62 Feature_NotInMicroMipsBit = 2, 63 Feature_IsLEBit = 39, 64 Feature_IsBEBit = 40, 65 Feature_IsNotNaClBit = 18, 66 Feature_HasEVABit = 35, 67 Feature_HasMSABit = 33, 68 Feature_HasMadd4Bit = 19, 69 Feature_UseIndirectJumpsHazardBit = 12, 70 Feature_NoIndirectJumpGuardsBit = 10, 71 Feature_AllowFPOpFusionBit = 38, 72 Feature_IsFP64bitBit = 15, 73 Feature_NotFP64bitBit = 14, 74 Feature_IsNotSoftFloatBit = 13, 75 Feature_HasDSPBit = 31, 76 Feature_HasDSPR2Bit = 32, 77}; 78 79PredicateBitset MipsInstructionSelector:: 80computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const { 81 PredicateBitset Features; 82 if (Subtarget->hasMips2()) 83 Features[Feature_HasMips2Bit] = 1; 84 if (Subtarget->hasMips3()) 85 Features[Feature_HasMips3Bit] = 1; 86 if (Subtarget->hasMips4_32()) 87 Features[Feature_HasMips4_32Bit] = 1; 88 if (!Subtarget->hasMips4_32()) 89 Features[Feature_NotMips4_32Bit] = 1; 90 if (Subtarget->hasMips4_32r2()) 91 Features[Feature_HasMips4_32r2Bit] = 1; 92 if (Subtarget->hasMips32()) 93 Features[Feature_HasMips32Bit] = 1; 94 if (Subtarget->hasMips32r2()) 95 Features[Feature_HasMips32r2Bit] = 1; 96 if (Subtarget->hasMips32r6()) 97 Features[Feature_HasMips32r6Bit] = 1; 98 if (!Subtarget->hasMips32r6()) 99 Features[Feature_NotMips32r6Bit] = 1; 100 if (Subtarget->isGP64bit()) 101 Features[Feature_IsGP64bitBit] = 1; 102 if (Subtarget->isABI_N64()) 103 Features[Feature_IsPTR64bitBit] = 1; 104 if (Subtarget->hasMips64()) 105 Features[Feature_HasMips64Bit] = 1; 106 if (Subtarget->hasMips64r2()) 107 Features[Feature_HasMips64r2Bit] = 1; 108 if (Subtarget->hasMips64r6()) 109 Features[Feature_HasMips64r6Bit] = 1; 110 if (!Subtarget->hasMips64r6()) 111 Features[Feature_NotMips64r6Bit] = 1; 112 if (Subtarget->inMips16Mode()) 113 Features[Feature_InMips16ModeBit] = 1; 114 if (!Subtarget->inMips16Mode()) 115 Features[Feature_NotInMips16ModeBit] = 1; 116 if (Subtarget->hasCnMips()) 117 Features[Feature_HasCnMipsBit] = 1; 118 if (!Subtarget->hasCnMips()) 119 Features[Feature_NotCnMipsBit] = 1; 120 if (Subtarget->isABI_N64()) 121 Features[Feature_IsN64Bit] = 1; 122 if (!TM.isPositionIndependent()) 123 Features[Feature_RelocNotPICBit] = 1; 124 if (TM.isPositionIndependent()) 125 Features[Feature_RelocPICBit] = 1; 126 if (TM.Options.NoNaNsFPMath) 127 Features[Feature_NoNaNsFPMathBit] = 1; 128 if (Subtarget->hasStandardEncoding()) 129 Features[Feature_HasStdEncBit] = 1; 130 if (!Subtarget->hasDSP()) 131 Features[Feature_NotDSPBit] = 1; 132 if (Subtarget->inMicroMipsMode()) 133 Features[Feature_InMicroMipsBit] = 1; 134 if (!Subtarget->inMicroMipsMode()) 135 Features[Feature_NotInMicroMipsBit] = 1; 136 if (Subtarget->isLittle()) 137 Features[Feature_IsLEBit] = 1; 138 if (!Subtarget->isLittle()) 139 Features[Feature_IsBEBit] = 1; 140 if (!Subtarget->isTargetNaCl()) 141 Features[Feature_IsNotNaClBit] = 1; 142 if (Subtarget->hasEVA()) 143 Features[Feature_HasEVABit] = 1; 144 if (Subtarget->hasMSA()) 145 Features[Feature_HasMSABit] = 1; 146 if (!Subtarget->disableMadd4()) 147 Features[Feature_HasMadd4Bit] = 1; 148 if (Subtarget->useIndirectJumpsHazard()) 149 Features[Feature_UseIndirectJumpsHazardBit] = 1; 150 if (!Subtarget->useIndirectJumpsHazard()) 151 Features[Feature_NoIndirectJumpGuardsBit] = 1; 152 if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) 153 Features[Feature_AllowFPOpFusionBit] = 1; 154 if (Subtarget->isFP64bit()) 155 Features[Feature_IsFP64bitBit] = 1; 156 if (!Subtarget->isFP64bit()) 157 Features[Feature_NotFP64bitBit] = 1; 158 if (!Subtarget->useSoftFloat()) 159 Features[Feature_IsNotSoftFloatBit] = 1; 160 if (Subtarget->hasDSP()) 161 Features[Feature_HasDSPBit] = 1; 162 if (Subtarget->hasDSPR2()) 163 Features[Feature_HasDSPR2Bit] = 1; 164 return Features; 165} 166 167PredicateBitset MipsInstructionSelector:: 168computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const { 169 PredicateBitset Features; 170 return Features; 171} 172 173// LLT Objects. 174enum { 175 GILLT_s16, 176 GILLT_s32, 177 GILLT_s64, 178 GILLT_v2s16, 179 GILLT_v2s64, 180 GILLT_v4s8, 181 GILLT_v4s32, 182 GILLT_v8s16, 183 GILLT_v16s8, 184}; 185const static size_t NumTypeObjects = 9; 186const static LLT TypeObjects[] = { 187 LLT::scalar(16), 188 LLT::scalar(32), 189 LLT::scalar(64), 190 LLT::vector(2, 16), 191 LLT::vector(2, 64), 192 LLT::vector(4, 8), 193 LLT::vector(4, 32), 194 LLT::vector(8, 16), 195 LLT::vector(16, 8), 196}; 197 198// Feature bitsets. 199enum { 200 GIFBS_Invalid, 201 GIFBS_HasCnMips, 202 GIFBS_HasDSP, 203 GIFBS_HasDSPR2, 204 GIFBS_HasMSA, 205 GIFBS_InMicroMips, 206 GIFBS_InMips16Mode, 207 GIFBS_IsFP64bit, 208 GIFBS_NotFP64bit, 209 GIFBS_HasDSP_InMicroMips, 210 GIFBS_HasDSP_NotInMicroMips, 211 GIFBS_HasDSPR2_InMicroMips, 212 GIFBS_HasMSA_HasStdEnc, 213 GIFBS_HasMSA_IsBE, 214 GIFBS_HasMSA_IsLE, 215 GIFBS_HasMips32r6_InMicroMips, 216 GIFBS_HasMips64r2_HasStdEnc, 217 GIFBS_HasMips64r6_HasStdEnc, 218 GIFBS_HasStdEnc_IsNotSoftFloat, 219 GIFBS_HasStdEnc_NotInMicroMips, 220 GIFBS_HasStdEnc_NotMips4_32, 221 GIFBS_InMicroMips_IsFP64bit, 222 GIFBS_InMicroMips_IsNotSoftFloat, 223 GIFBS_InMicroMips_NotFP64bit, 224 GIFBS_InMicroMips_NotMips32r6, 225 GIFBS_IsGP64bit_NotInMips16Mode, 226 GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, 227 GIFBS_HasMSA_HasMips64_HasStdEnc, 228 GIFBS_HasMips3_HasStdEnc_IsGP64bit, 229 GIFBS_HasMips3_HasStdEnc_NotInMicroMips, 230 GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, 231 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, 232 GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, 233 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, 234 GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips, 235 GIFBS_HasStdEnc_IsFP64bit_NotMips4_32, 236 GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 237 GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips, 238 GIFBS_HasStdEnc_NotFP64bit_NotMips4_32, 239 GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC, 240 GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, 241 GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, 242 GIFBS_InMicroMips_NotFP64bit_NotMips32r6, 243 GIFBS_InMicroMips_NotMips32r6_RelocNotPIC, 244 GIFBS_InMicroMips_NotMips32r6_RelocPIC, 245 GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 246 GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 247 GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, 248 GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips, 249 GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, 250 GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, 251 GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, 252 GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, 253 GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6, 254 GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 255 GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 256 GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 257 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, 258 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, 259 GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6, 260 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, 261 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, 262 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 263 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 264}; 265const static PredicateBitset FeatureBitsets[] { 266 {}, // GIFBS_Invalid 267 {Feature_HasCnMipsBit, }, 268 {Feature_HasDSPBit, }, 269 {Feature_HasDSPR2Bit, }, 270 {Feature_HasMSABit, }, 271 {Feature_InMicroMipsBit, }, 272 {Feature_InMips16ModeBit, }, 273 {Feature_IsFP64bitBit, }, 274 {Feature_NotFP64bitBit, }, 275 {Feature_HasDSPBit, Feature_InMicroMipsBit, }, 276 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, 277 {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, }, 278 {Feature_HasMSABit, Feature_HasStdEncBit, }, 279 {Feature_HasMSABit, Feature_IsBEBit, }, 280 {Feature_HasMSABit, Feature_IsLEBit, }, 281 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, }, 282 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, }, 283 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, }, 284 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, 285 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, 286 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, 287 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, }, 288 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, 289 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, }, 290 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, 291 {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, }, 292 {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, }, 293 {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, }, 294 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, }, 295 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, 296 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, 297 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, 298 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, 299 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, 300 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, }, 301 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, }, 302 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 303 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, }, 304 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, }, 305 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, }, 306 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, 307 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, }, 308 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, }, 309 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, }, 310 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, }, 311 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 312 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 313 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 314 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, 315 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 316 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, }, 317 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 318 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 319 {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, }, 320 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 321 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 322 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 323 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 324 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 325 {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, }, 326 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 327 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 328 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 329 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 330}; 331 332// ComplexPattern predicates. 333enum { 334 GICP_Invalid, 335}; 336// See constructor for table contents 337 338// PatFrag predicates. 339enum { 340 GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1, 341 GIPFP_I64_Predicate_immSExt10, 342 GIPFP_I64_Predicate_immSExt6, 343 GIPFP_I64_Predicate_immSExtAddiur2, 344 GIPFP_I64_Predicate_immSExtAddius5, 345 GIPFP_I64_Predicate_immZExt1, 346 GIPFP_I64_Predicate_immZExt10, 347 GIPFP_I64_Predicate_immZExt1Ptr, 348 GIPFP_I64_Predicate_immZExt2, 349 GIPFP_I64_Predicate_immZExt2Lsa, 350 GIPFP_I64_Predicate_immZExt2Ptr, 351 GIPFP_I64_Predicate_immZExt2Shift, 352 GIPFP_I64_Predicate_immZExt3, 353 GIPFP_I64_Predicate_immZExt3Ptr, 354 GIPFP_I64_Predicate_immZExt4, 355 GIPFP_I64_Predicate_immZExt4Ptr, 356 GIPFP_I64_Predicate_immZExt5, 357 GIPFP_I64_Predicate_immZExt5_64, 358 GIPFP_I64_Predicate_immZExt6, 359 GIPFP_I64_Predicate_immZExt8, 360 GIPFP_I64_Predicate_immZExtAndi16, 361 GIPFP_I64_Predicate_immi32Cst15, 362 GIPFP_I64_Predicate_immi32Cst31, 363 GIPFP_I64_Predicate_immi32Cst7, 364}; 365bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { 366 switch (PredicateID) { 367 case GIPFP_I64_Predicate_immLi16: { 368 return Imm >= -1 && Imm <= 126; 369 llvm_unreachable("ImmediateCode should have returned"); 370 return false; 371 } 372 case GIPFP_I64_Predicate_immSExt10: { 373 return isInt<10>(Imm); 374 llvm_unreachable("ImmediateCode should have returned"); 375 return false; 376 } 377 case GIPFP_I64_Predicate_immSExt6: { 378 return isInt<6>(Imm); 379 llvm_unreachable("ImmediateCode should have returned"); 380 return false; 381 } 382 case GIPFP_I64_Predicate_immSExtAddiur2: { 383 return Imm == 1 || Imm == -1 || 384 ((Imm % 4 == 0) && 385 Imm < 28 && Imm > 0); 386 llvm_unreachable("ImmediateCode should have returned"); 387 return false; 388 } 389 case GIPFP_I64_Predicate_immSExtAddius5: { 390 return Imm >= -8 && Imm <= 7; 391 llvm_unreachable("ImmediateCode should have returned"); 392 return false; 393 } 394 case GIPFP_I64_Predicate_immZExt1: { 395 return isUInt<1>(Imm); 396 llvm_unreachable("ImmediateCode should have returned"); 397 return false; 398 } 399 case GIPFP_I64_Predicate_immZExt10: { 400 return isUInt<10>(Imm); 401 llvm_unreachable("ImmediateCode should have returned"); 402 return false; 403 } 404 case GIPFP_I64_Predicate_immZExt1Ptr: { 405 return isUInt<1>(Imm); 406 llvm_unreachable("ImmediateCode should have returned"); 407 return false; 408 } 409 case GIPFP_I64_Predicate_immZExt2: { 410 return isUInt<2>(Imm); 411 llvm_unreachable("ImmediateCode should have returned"); 412 return false; 413 } 414 case GIPFP_I64_Predicate_immZExt2Lsa: { 415 return isUInt<2>(Imm - 1); 416 llvm_unreachable("ImmediateCode should have returned"); 417 return false; 418 } 419 case GIPFP_I64_Predicate_immZExt2Ptr: { 420 return isUInt<2>(Imm); 421 llvm_unreachable("ImmediateCode should have returned"); 422 return false; 423 } 424 case GIPFP_I64_Predicate_immZExt2Shift: { 425 return Imm >= 1 && Imm <= 8; 426 llvm_unreachable("ImmediateCode should have returned"); 427 return false; 428 } 429 case GIPFP_I64_Predicate_immZExt3: { 430 return isUInt<3>(Imm); 431 llvm_unreachable("ImmediateCode should have returned"); 432 return false; 433 } 434 case GIPFP_I64_Predicate_immZExt3Ptr: { 435 return isUInt<3>(Imm); 436 llvm_unreachable("ImmediateCode should have returned"); 437 return false; 438 } 439 case GIPFP_I64_Predicate_immZExt4: { 440 return isUInt<4>(Imm); 441 llvm_unreachable("ImmediateCode should have returned"); 442 return false; 443 } 444 case GIPFP_I64_Predicate_immZExt4Ptr: { 445 return isUInt<4>(Imm); 446 llvm_unreachable("ImmediateCode should have returned"); 447 return false; 448 } 449 case GIPFP_I64_Predicate_immZExt5: { 450 return Imm == (Imm & 0x1f); 451 llvm_unreachable("ImmediateCode should have returned"); 452 return false; 453 } 454 case GIPFP_I64_Predicate_immZExt5_64: { 455 return Imm == (Imm & 0x1f); 456 llvm_unreachable("ImmediateCode should have returned"); 457 return false; 458 } 459 case GIPFP_I64_Predicate_immZExt6: { 460 return Imm == (Imm & 0x3f); 461 llvm_unreachable("ImmediateCode should have returned"); 462 return false; 463 } 464 case GIPFP_I64_Predicate_immZExt8: { 465 return isUInt<8>(Imm); 466 llvm_unreachable("ImmediateCode should have returned"); 467 return false; 468 } 469 case GIPFP_I64_Predicate_immZExtAndi16: { 470 return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || 471 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || 472 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 ); 473 llvm_unreachable("ImmediateCode should have returned"); 474 return false; 475 } 476 case GIPFP_I64_Predicate_immi32Cst15: { 477 return isUInt<32>(Imm) && Imm == 15; 478 llvm_unreachable("ImmediateCode should have returned"); 479 return false; 480 } 481 case GIPFP_I64_Predicate_immi32Cst31: { 482 return isUInt<32>(Imm) && Imm == 31; 483 llvm_unreachable("ImmediateCode should have returned"); 484 return false; 485 } 486 case GIPFP_I64_Predicate_immi32Cst7: { 487 return isUInt<32>(Imm) && Imm == 7; 488 llvm_unreachable("ImmediateCode should have returned"); 489 return false; 490 } 491 } 492 llvm_unreachable("Unknown predicate"); 493 return false; 494} 495bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { 496 llvm_unreachable("Unknown predicate"); 497 return false; 498} 499bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { 500 llvm_unreachable("Unknown predicate"); 501 return false; 502} 503bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const { 504 const MachineFunction &MF = *MI.getParent()->getParent(); 505 const MachineRegisterInfo &MRI = MF.getRegInfo(); 506 (void)MRI; 507 llvm_unreachable("Unknown predicate"); 508 return false; 509} 510 511MipsInstructionSelector::ComplexMatcherMemFn 512MipsInstructionSelector::ComplexPredicateFns[] = { 513 nullptr, // GICP_Invalid 514}; 515 516// Custom renderers. 517enum { 518 GICR_Invalid, 519}; 520MipsInstructionSelector::CustomRendererFn 521MipsInstructionSelector::CustomRenderers[] = { 522 nullptr, // GICP_Invalid 523}; 524 525bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { 526 MachineFunction &MF = *I.getParent()->getParent(); 527 MachineRegisterInfo &MRI = MF.getRegInfo(); 528 // FIXME: This should be computed on a per-function basis rather than per-insn. 529 AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF); 530 const PredicateBitset AvailableFeatures = getAvailableFeatures(); 531 NewMIVector OutMIs; 532 State.MIs.clear(); 533 State.MIs.push_back(&I); 534 535 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { 536 return true; 537 } 538 539 return false; 540} 541 542const int64_t *MipsInstructionSelector::getMatchTable() const { 543 constexpr static int64_t MatchTable0[] = { 544 GIM_SwitchOpcode, /*MI*/0, /*[*/34, 124, /*)*//*default:*//*Label 40*/ 37669, 545 /*TargetOpcode::G_ADD*//*Label 0*/ 95, 546 /*TargetOpcode::G_SUB*//*Label 1*/ 1272, 547 /*TargetOpcode::G_MUL*//*Label 2*/ 1884, 548 /*TargetOpcode::G_SDIV*//*Label 3*/ 2260, 549 /*TargetOpcode::G_UDIV*//*Label 4*/ 2481, 550 /*TargetOpcode::G_SREM*//*Label 5*/ 2702, 551 /*TargetOpcode::G_UREM*//*Label 6*/ 2923, 552 /*TargetOpcode::G_AND*//*Label 7*/ 3144, 553 /*TargetOpcode::G_OR*//*Label 8*/ 3588, 554 /*TargetOpcode::G_XOR*//*Label 9*/ 3890, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 555 /*TargetOpcode::G_BITCAST*//*Label 10*/ 4684, 556 /*TargetOpcode::G_LOAD*//*Label 11*/ 8337, 557 /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 8403, 558 /*TargetOpcode::G_ZEXTLOAD*//*Label 13*/ 8469, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 559 /*TargetOpcode::G_INTRINSIC*//*Label 14*/ 8535, 560 /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 25046, 0, 561 /*TargetOpcode::G_TRUNC*//*Label 16*/ 29970, 562 /*TargetOpcode::G_CONSTANT*//*Label 17*/ 30027, 0, 0, 0, 563 /*TargetOpcode::G_SEXT*//*Label 18*/ 30087, 564 /*TargetOpcode::G_ZEXT*//*Label 19*/ 30115, 565 /*TargetOpcode::G_SHL*//*Label 20*/ 30200, 566 /*TargetOpcode::G_LSHR*//*Label 21*/ 30724, 567 /*TargetOpcode::G_ASHR*//*Label 22*/ 31248, 0, 0, 568 /*TargetOpcode::G_SELECT*//*Label 23*/ 31729, 0, 0, 0, 0, 0, 0, 0, 0, 569 /*TargetOpcode::G_FADD*//*Label 24*/ 33183, 570 /*TargetOpcode::G_FSUB*//*Label 25*/ 34062, 571 /*TargetOpcode::G_FMUL*//*Label 26*/ 34638, 572 /*TargetOpcode::G_FMA*//*Label 27*/ 35075, 573 /*TargetOpcode::G_FDIV*//*Label 28*/ 35165, 0, 0, 0, 574 /*TargetOpcode::G_FEXP2*//*Label 29*/ 35416, 0, 575 /*TargetOpcode::G_FLOG2*//*Label 30*/ 35474, 576 /*TargetOpcode::G_FNEG*//*Label 31*/ 35532, 577 /*TargetOpcode::G_FPEXT*//*Label 32*/ 36828, 578 /*TargetOpcode::G_FPTRUNC*//*Label 33*/ 36977, 579 /*TargetOpcode::G_FPTOSI*//*Label 34*/ 37105, 580 /*TargetOpcode::G_FPTOUI*//*Label 35*/ 37163, 581 /*TargetOpcode::G_SITOFP*//*Label 36*/ 37221, 582 /*TargetOpcode::G_UITOFP*//*Label 37*/ 37374, 0, 0, 0, 583 /*TargetOpcode::G_BR*//*Label 38*/ 37432, 0, 0, 0, 584 /*TargetOpcode::G_BSWAP*//*Label 39*/ 37517, 585 // Label 0: @95 586 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 49*/ 1271, 587 /*GILLT_s32*//*Label 41*/ 109, 588 /*GILLT_s64*//*Label 42*/ 458, 589 /*GILLT_v2s16*//*Label 43*/ 621, 590 /*GILLT_v2s64*//*Label 44*/ 648, 591 /*GILLT_v4s8*//*Label 45*/ 797, 592 /*GILLT_v4s32*//*Label 46*/ 824, 593 /*GILLT_v8s16*//*Label 47*/ 973, 594 /*GILLT_v16s8*//*Label 48*/ 1122, 595 // Label 41: @109 596 GIM_Try, /*On fail goto*//*Label 50*/ 457, 597 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 598 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 599 GIM_Try, /*On fail goto*//*Label 51*/ 187, // Rule ID 2290 // 600 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 602 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 603 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 604 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 605 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 606 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 607 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 608 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 609 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa, 610 // MIs[2] Operand 1 611 // No operand predicates 612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 613 GIM_CheckIsSafeToFold, /*InsnID*/1, 614 GIM_CheckIsSafeToFold, /*InsnID*/2, 615 // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa) 616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA, 617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs 619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 620 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa 621 GIR_EraseFromParent, /*InsnID*/0, 622 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 623 // GIR_Coverage, 2290, 624 GIR_Done, 625 // Label 51: @187 626 GIM_Try, /*On fail goto*//*Label 52*/ 255, // Rule ID 802 // 627 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 630 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 631 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 632 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 633 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 634 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 635 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 636 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 637 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa, 638 // MIs[2] Operand 1 639 // No operand predicates 640 GIM_CheckIsSafeToFold, /*InsnID*/1, 641 GIM_CheckIsSafeToFold, /*InsnID*/2, 642 // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa) 643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA, 644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs 646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 647 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa 648 GIR_EraseFromParent, /*InsnID*/0, 649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 650 // GIR_Coverage, 802, 651 GIR_Done, 652 // Label 52: @255 653 GIM_Try, /*On fail goto*//*Label 53*/ 298, // Rule ID 2066 // 654 GIM_CheckFeatures, GIFBS_InMicroMips, 655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 657 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 658 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 659 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2, 660 // MIs[1] Operand 1 661 // No operand predicates 662 GIM_CheckIsSafeToFold, /*InsnID*/1, 663 // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) 664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM, 665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 667 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 668 GIR_EraseFromParent, /*InsnID*/0, 669 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 670 // GIR_Coverage, 2066, 671 GIR_Done, 672 // Label 53: @298 673 GIM_Try, /*On fail goto*//*Label 54*/ 341, // Rule ID 2067 // 674 GIM_CheckFeatures, GIFBS_InMicroMips, 675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 677 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 678 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 679 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5, 680 // MIs[1] Operand 1 681 // No operand predicates 682 GIM_CheckIsSafeToFold, /*InsnID*/1, 683 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) 684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM, 685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 687 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 688 GIR_EraseFromParent, /*InsnID*/0, 689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 690 // GIR_Coverage, 2067, 691 GIR_Done, 692 // Label 54: @341 693 GIM_Try, /*On fail goto*//*Label 55*/ 364, // Rule ID 1165 // 694 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, 698 // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) 699 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6, 700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 701 // GIR_Coverage, 1165, 702 GIR_Done, 703 // Label 55: @364 704 GIM_Try, /*On fail goto*//*Label 56*/ 387, // Rule ID 34 // 705 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 709 // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 710 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu, 711 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 712 // GIR_Coverage, 34, 713 GIR_Done, 714 // Label 56: @387 715 GIM_Try, /*On fail goto*//*Label 57*/ 410, // Rule ID 1028 // 716 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, 720 // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) 721 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM, 722 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 723 // GIR_Coverage, 1028, 724 GIR_Done, 725 // Label 57: @410 726 GIM_Try, /*On fail goto*//*Label 58*/ 433, // Rule ID 1040 // 727 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 731 // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 732 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM, 733 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 734 // GIR_Coverage, 1040, 735 GIR_Done, 736 // Label 58: @433 737 GIM_Try, /*On fail goto*//*Label 59*/ 456, // Rule ID 1735 // 738 GIM_CheckFeatures, GIFBS_InMips16Mode, 739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 742 // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) 743 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16, 744 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 745 // GIR_Coverage, 1735, 746 GIR_Done, 747 // Label 59: @456 748 GIM_Reject, 749 // Label 50: @457 750 GIM_Reject, 751 // Label 42: @458 752 GIM_Try, /*On fail goto*//*Label 60*/ 620, 753 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 754 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 756 GIM_Try, /*On fail goto*//*Label 61*/ 536, // Rule ID 2291 // 757 GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc, 758 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 759 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 760 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 761 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 762 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 763 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 764 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 765 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa, 766 // MIs[2] Operand 1 767 // No operand predicates 768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 769 GIM_CheckIsSafeToFold, /*InsnID*/1, 770 GIM_CheckIsSafeToFold, /*InsnID*/2, 771 // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa) 772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA, 773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs 775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 776 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa 777 GIR_EraseFromParent, /*InsnID*/0, 778 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 779 // GIR_Coverage, 2291, 780 GIR_Done, 781 // Label 61: @536 782 GIM_Try, /*On fail goto*//*Label 62*/ 600, // Rule ID 803 // 783 GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc, 784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 785 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 786 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 787 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 788 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 789 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 790 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 791 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 792 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa, 793 // MIs[2] Operand 1 794 // No operand predicates 795 GIM_CheckIsSafeToFold, /*InsnID*/1, 796 GIM_CheckIsSafeToFold, /*InsnID*/2, 797 // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa) 798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA, 799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs 801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 802 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa 803 GIR_EraseFromParent, /*InsnID*/0, 804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 805 // GIR_Coverage, 803, 806 GIR_Done, 807 // Label 62: @600 808 GIM_Try, /*On fail goto*//*Label 63*/ 619, // Rule ID 180 // 809 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, 810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 812 // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 813 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu, 814 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 815 // GIR_Coverage, 180, 816 GIR_Done, 817 // Label 63: @619 818 GIM_Reject, 819 // Label 60: @620 820 GIM_Reject, 821 // Label 43: @621 822 GIM_Try, /*On fail goto*//*Label 64*/ 647, // Rule ID 1834 // 823 GIM_CheckFeatures, GIFBS_HasDSP, 824 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 825 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 827 // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) 828 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH, 829 GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, 830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 831 // GIR_Coverage, 1834, 832 GIR_Done, 833 // Label 64: @647 834 GIM_Reject, 835 // Label 44: @648 836 GIM_Try, /*On fail goto*//*Label 65*/ 796, 837 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 838 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 840 GIM_Try, /*On fail goto*//*Label 66*/ 719, // Rule ID 2295 // 841 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 842 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 843 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 844 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 845 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 846 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 847 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 849 GIM_CheckIsSafeToFold, /*InsnID*/1, 850 // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 851 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D, 852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 853 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 856 GIR_EraseFromParent, /*InsnID*/0, 857 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 858 // GIR_Coverage, 2295, 859 GIR_Done, 860 // Label 66: @719 861 GIM_Try, /*On fail goto*//*Label 67*/ 776, // Rule ID 811 // 862 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 864 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 865 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 866 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 867 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 868 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 869 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 870 GIM_CheckIsSafeToFold, /*InsnID*/1, 871 // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D, 873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in 875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 877 GIR_EraseFromParent, /*InsnID*/0, 878 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 879 // GIR_Coverage, 811, 880 GIR_Done, 881 // Label 67: @776 882 GIM_Try, /*On fail goto*//*Label 68*/ 795, // Rule ID 478 // 883 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 886 // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 887 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D, 888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 889 // GIR_Coverage, 478, 890 GIR_Done, 891 // Label 68: @795 892 GIM_Reject, 893 // Label 65: @796 894 GIM_Reject, 895 // Label 45: @797 896 GIM_Try, /*On fail goto*//*Label 69*/ 823, // Rule ID 1840 // 897 GIM_CheckFeatures, GIFBS_HasDSP, 898 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 899 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 901 // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) 902 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB, 903 GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, 904 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 905 // GIR_Coverage, 1840, 906 GIR_Done, 907 // Label 69: @823 908 GIM_Reject, 909 // Label 46: @824 910 GIM_Try, /*On fail goto*//*Label 70*/ 972, 911 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 912 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 914 GIM_Try, /*On fail goto*//*Label 71*/ 895, // Rule ID 2294 // 915 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 916 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 917 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 918 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 919 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 920 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 921 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 923 GIM_CheckIsSafeToFold, /*InsnID*/1, 924 // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W, 926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 930 GIR_EraseFromParent, /*InsnID*/0, 931 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 932 // GIR_Coverage, 2294, 933 GIR_Done, 934 // Label 71: @895 935 GIM_Try, /*On fail goto*//*Label 72*/ 952, // Rule ID 810 // 936 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 938 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 939 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 940 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 941 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 942 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 943 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 944 GIM_CheckIsSafeToFold, /*InsnID*/1, 945 // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W, 947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in 949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 950 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 951 GIR_EraseFromParent, /*InsnID*/0, 952 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 953 // GIR_Coverage, 810, 954 GIR_Done, 955 // Label 72: @952 956 GIM_Try, /*On fail goto*//*Label 73*/ 971, // Rule ID 477 // 957 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 960 // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 961 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W, 962 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 963 // GIR_Coverage, 477, 964 GIR_Done, 965 // Label 73: @971 966 GIM_Reject, 967 // Label 70: @972 968 GIM_Reject, 969 // Label 47: @973 970 GIM_Try, /*On fail goto*//*Label 74*/ 1121, 971 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 972 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 974 GIM_Try, /*On fail goto*//*Label 75*/ 1044, // Rule ID 2293 // 975 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 976 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 977 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 978 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 979 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 980 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 981 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 983 GIM_CheckIsSafeToFold, /*InsnID*/1, 984 // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H, 986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 990 GIR_EraseFromParent, /*InsnID*/0, 991 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 992 // GIR_Coverage, 2293, 993 GIR_Done, 994 // Label 75: @1044 995 GIM_Try, /*On fail goto*//*Label 76*/ 1101, // Rule ID 809 // 996 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 998 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 999 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1000 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 1001 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 1002 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 1003 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 1004 GIM_CheckIsSafeToFold, /*InsnID*/1, 1005 // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 1006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H, 1007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 1008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in 1009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 1010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 1011 GIR_EraseFromParent, /*InsnID*/0, 1012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1013 // GIR_Coverage, 809, 1014 GIR_Done, 1015 // Label 76: @1101 1016 GIM_Try, /*On fail goto*//*Label 77*/ 1120, // Rule ID 476 // 1017 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 1019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 1020 // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 1021 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H, 1022 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1023 // GIR_Coverage, 476, 1024 GIR_Done, 1025 // Label 77: @1120 1026 GIM_Reject, 1027 // Label 74: @1121 1028 GIM_Reject, 1029 // Label 48: @1122 1030 GIM_Try, /*On fail goto*//*Label 78*/ 1270, 1031 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 1032 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 1033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 1034 GIM_Try, /*On fail goto*//*Label 79*/ 1193, // Rule ID 2292 // 1035 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1036 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1037 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1038 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, 1039 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 1040 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1041 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1043 GIM_CheckIsSafeToFold, /*InsnID*/1, 1044 // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B, 1046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 1047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 1048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 1049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 1050 GIR_EraseFromParent, /*InsnID*/0, 1051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1052 // GIR_Coverage, 2292, 1053 GIR_Done, 1054 // Label 79: @1193 1055 GIM_Try, /*On fail goto*//*Label 80*/ 1250, // Rule ID 808 // 1056 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1058 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1059 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1060 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, 1061 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 1062 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1063 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1064 GIM_CheckIsSafeToFold, /*InsnID*/1, 1065 // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B, 1067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 1068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in 1069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 1070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 1071 GIR_EraseFromParent, /*InsnID*/0, 1072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1073 // GIR_Coverage, 808, 1074 GIR_Done, 1075 // Label 80: @1250 1076 GIM_Try, /*On fail goto*//*Label 81*/ 1269, // Rule ID 475 // 1077 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1080 // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1081 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B, 1082 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1083 // GIR_Coverage, 475, 1084 GIR_Done, 1085 // Label 81: @1269 1086 GIM_Reject, 1087 // Label 78: @1270 1088 GIM_Reject, 1089 // Label 49: @1271 1090 GIM_Reject, 1091 // Label 1: @1272 1092 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 90*/ 1883, 1093 /*GILLT_s32*//*Label 82*/ 1286, 1094 /*GILLT_s64*//*Label 83*/ 1445, 1095 /*GILLT_v2s16*//*Label 84*/ 1477, 1096 /*GILLT_v2s64*//*Label 85*/ 1504, 1097 /*GILLT_v4s8*//*Label 86*/ 1592, 1098 /*GILLT_v4s32*//*Label 87*/ 1619, 1099 /*GILLT_v8s16*//*Label 88*/ 1707, 1100 /*GILLT_v16s8*//*Label 89*/ 1795, 1101 // Label 82: @1286 1102 GIM_Try, /*On fail goto*//*Label 91*/ 1444, 1103 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1104 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1105 GIM_Try, /*On fail goto*//*Label 92*/ 1328, // Rule ID 1734 // 1106 GIM_CheckFeatures, GIFBS_InMips16Mode, 1107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 1108 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, 1109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 1110 // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r) 1111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16, 1112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx 1113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r 1114 GIR_EraseFromParent, /*InsnID*/0, 1115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1116 // GIR_Coverage, 1734, 1117 GIR_Done, 1118 // Label 92: @1328 1119 GIM_Try, /*On fail goto*//*Label 93*/ 1351, // Rule ID 1167 // 1120 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 1121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 1122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 1123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, 1124 // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) 1125 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6, 1126 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1127 // GIR_Coverage, 1167, 1128 GIR_Done, 1129 // Label 93: @1351 1130 GIM_Try, /*On fail goto*//*Label 94*/ 1374, // Rule ID 35 // 1131 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 1132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1135 // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1136 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu, 1137 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1138 // GIR_Coverage, 35, 1139 GIR_Done, 1140 // Label 94: @1374 1141 GIM_Try, /*On fail goto*//*Label 95*/ 1397, // Rule ID 1032 // 1142 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 1143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 1144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 1145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, 1146 // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) 1147 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM, 1148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1149 // GIR_Coverage, 1032, 1150 GIR_Done, 1151 // Label 95: @1397 1152 GIM_Try, /*On fail goto*//*Label 96*/ 1420, // Rule ID 1041 // 1153 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 1154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1157 // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1158 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM, 1159 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1160 // GIR_Coverage, 1041, 1161 GIR_Done, 1162 // Label 96: @1420 1163 GIM_Try, /*On fail goto*//*Label 97*/ 1443, // Rule ID 1739 // 1164 GIM_CheckFeatures, GIFBS_InMips16Mode, 1165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 1166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 1167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 1168 // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) 1169 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16, 1170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1171 // GIR_Coverage, 1739, 1172 GIR_Done, 1173 // Label 97: @1443 1174 GIM_Reject, 1175 // Label 91: @1444 1176 GIM_Reject, 1177 // Label 83: @1445 1178 GIM_Try, /*On fail goto*//*Label 98*/ 1476, // Rule ID 181 // 1179 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, 1180 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1181 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 1183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 1184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 1185 // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 1186 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu, 1187 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1188 // GIR_Coverage, 181, 1189 GIR_Done, 1190 // Label 98: @1476 1191 GIM_Reject, 1192 // Label 84: @1477 1193 GIM_Try, /*On fail goto*//*Label 99*/ 1503, // Rule ID 1836 // 1194 GIM_CheckFeatures, GIFBS_HasDSP, 1195 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 1196 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 1197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 1198 // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) 1199 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH, 1200 GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, 1201 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1202 // GIR_Coverage, 1836, 1203 GIR_Done, 1204 // Label 99: @1503 1205 GIM_Reject, 1206 // Label 85: @1504 1207 GIM_Try, /*On fail goto*//*Label 100*/ 1591, 1208 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1209 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 1211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 1212 GIM_Try, /*On fail goto*//*Label 101*/ 1575, // Rule ID 867 // 1213 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1214 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1215 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1216 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 1217 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 1218 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 1219 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 1220 GIM_CheckIsSafeToFold, /*InsnID*/1, 1221 // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 1222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D, 1223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 1224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in 1225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 1226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 1227 GIR_EraseFromParent, /*InsnID*/0, 1228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1229 // GIR_Coverage, 867, 1230 GIR_Done, 1231 // Label 101: @1575 1232 GIM_Try, /*On fail goto*//*Label 102*/ 1590, // Rule ID 996 // 1233 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 1235 // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 1236 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D, 1237 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1238 // GIR_Coverage, 996, 1239 GIR_Done, 1240 // Label 102: @1590 1241 GIM_Reject, 1242 // Label 100: @1591 1243 GIM_Reject, 1244 // Label 86: @1592 1245 GIM_Try, /*On fail goto*//*Label 103*/ 1618, // Rule ID 1842 // 1246 GIM_CheckFeatures, GIFBS_HasDSP, 1247 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 1248 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 1249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 1250 // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) 1251 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB, 1252 GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, 1253 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1254 // GIR_Coverage, 1842, 1255 GIR_Done, 1256 // Label 103: @1618 1257 GIM_Reject, 1258 // Label 87: @1619 1259 GIM_Try, /*On fail goto*//*Label 104*/ 1706, 1260 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1261 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 1263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 1264 GIM_Try, /*On fail goto*//*Label 105*/ 1690, // Rule ID 866 // 1265 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1266 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1267 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1268 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1269 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1270 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 1271 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 1272 GIM_CheckIsSafeToFold, /*InsnID*/1, 1273 // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 1274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W, 1275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 1276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in 1277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 1278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 1279 GIR_EraseFromParent, /*InsnID*/0, 1280 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1281 // GIR_Coverage, 866, 1282 GIR_Done, 1283 // Label 105: @1690 1284 GIM_Try, /*On fail goto*//*Label 106*/ 1705, // Rule ID 995 // 1285 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 1287 // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 1288 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W, 1289 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1290 // GIR_Coverage, 995, 1291 GIR_Done, 1292 // Label 106: @1705 1293 GIM_Reject, 1294 // Label 104: @1706 1295 GIM_Reject, 1296 // Label 88: @1707 1297 GIM_Try, /*On fail goto*//*Label 107*/ 1794, 1298 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 1299 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 1300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 1301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 1302 GIM_Try, /*On fail goto*//*Label 108*/ 1778, // Rule ID 865 // 1303 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1304 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1305 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1306 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 1307 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 1308 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 1309 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 1310 GIM_CheckIsSafeToFold, /*InsnID*/1, 1311 // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 1312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H, 1313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 1314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in 1315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 1316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 1317 GIR_EraseFromParent, /*InsnID*/0, 1318 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1319 // GIR_Coverage, 865, 1320 GIR_Done, 1321 // Label 108: @1778 1322 GIM_Try, /*On fail goto*//*Label 109*/ 1793, // Rule ID 994 // 1323 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 1325 // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 1326 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H, 1327 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1328 // GIR_Coverage, 994, 1329 GIR_Done, 1330 // Label 109: @1793 1331 GIM_Reject, 1332 // Label 107: @1794 1333 GIM_Reject, 1334 // Label 89: @1795 1335 GIM_Try, /*On fail goto*//*Label 110*/ 1882, 1336 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 1337 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 1338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 1339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1340 GIM_Try, /*On fail goto*//*Label 111*/ 1866, // Rule ID 864 // 1341 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1342 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1343 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1344 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, 1345 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 1346 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1347 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1348 GIM_CheckIsSafeToFold, /*InsnID*/1, 1349 // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B, 1351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 1352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in 1353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 1354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 1355 GIR_EraseFromParent, /*InsnID*/0, 1356 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1357 // GIR_Coverage, 864, 1358 GIR_Done, 1359 // Label 111: @1866 1360 GIM_Try, /*On fail goto*//*Label 112*/ 1881, // Rule ID 993 // 1361 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1363 // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1364 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B, 1365 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1366 // GIR_Coverage, 993, 1367 GIR_Done, 1368 // Label 112: @1881 1369 GIM_Reject, 1370 // Label 110: @1882 1371 GIM_Reject, 1372 // Label 90: @1883 1373 GIM_Reject, 1374 // Label 2: @1884 1375 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 120*/ 2259, 1376 /*GILLT_s32*//*Label 113*/ 1898, 1377 /*GILLT_s64*//*Label 114*/ 2043, 1378 /*GILLT_v2s16*//*Label 115*/ 2104, 1379 /*GILLT_v2s64*//*Label 116*/ 2131, 0, 1380 /*GILLT_v4s32*//*Label 117*/ 2163, 1381 /*GILLT_v8s16*//*Label 118*/ 2195, 1382 /*GILLT_v16s8*//*Label 119*/ 2227, 1383 // Label 113: @1898 1384 GIM_Try, /*On fail goto*//*Label 121*/ 2042, 1385 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1386 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1387 GIM_Try, /*On fail goto*//*Label 122*/ 1937, // Rule ID 36 // 1388 GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, 1389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1392 // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL, 1394 GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, 1395 GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, 1396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1397 // GIR_Coverage, 36, 1398 GIR_Done, 1399 // Label 122: @1937 1400 GIM_Try, /*On fail goto*//*Label 123*/ 1960, // Rule ID 304 // 1401 GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, 1402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1405 // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1406 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6, 1407 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1408 // GIR_Coverage, 304, 1409 GIR_Done, 1410 // Label 123: @1960 1411 GIM_Try, /*On fail goto*//*Label 124*/ 1989, // Rule ID 1042 // 1412 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 1413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1416 // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1417 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM, 1418 GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, 1419 GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, 1420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1421 // GIR_Coverage, 1042, 1422 GIR_Done, 1423 // Label 124: @1989 1424 GIM_Try, /*On fail goto*//*Label 125*/ 2012, // Rule ID 1136 // 1425 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 1426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1429 // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1430 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6, 1431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1432 // GIR_Coverage, 1136, 1433 GIR_Done, 1434 // Label 125: @2012 1435 GIM_Try, /*On fail goto*//*Label 126*/ 2041, // Rule ID 1737 // 1436 GIM_CheckFeatures, GIFBS_InMips16Mode, 1437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 1438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 1439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 1440 // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) 1441 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16, 1442 GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, 1443 GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, 1444 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1445 // GIR_Coverage, 1737, 1446 GIR_Done, 1447 // Label 126: @2041 1448 GIM_Reject, 1449 // Label 121: @2042 1450 GIM_Reject, 1451 // Label 114: @2043 1452 GIM_Try, /*On fail goto*//*Label 127*/ 2103, 1453 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1454 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 1456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 1457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 1458 GIM_Try, /*On fail goto*//*Label 128*/ 2091, // Rule ID 246 // 1459 GIM_CheckFeatures, GIFBS_HasCnMips, 1460 // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 1461 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL, 1462 GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, 1463 GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, 1464 GIR_AddImplicitDef, /*InsnID*/0, Mips::P0, 1465 GIR_AddImplicitDef, /*InsnID*/0, Mips::P1, 1466 GIR_AddImplicitDef, /*InsnID*/0, Mips::P2, 1467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1468 // GIR_Coverage, 246, 1469 GIR_Done, 1470 // Label 128: @2091 1471 GIM_Try, /*On fail goto*//*Label 129*/ 2102, // Rule ID 319 // 1472 GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, 1473 // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 1474 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6, 1475 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1476 // GIR_Coverage, 319, 1477 GIR_Done, 1478 // Label 129: @2102 1479 GIM_Reject, 1480 // Label 127: @2103 1481 GIM_Reject, 1482 // Label 115: @2104 1483 GIM_Try, /*On fail goto*//*Label 130*/ 2130, // Rule ID 1838 // 1484 GIM_CheckFeatures, GIFBS_HasDSPR2, 1485 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 1486 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 1487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 1488 // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) 1489 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH, 1490 GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21, 1491 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1492 // GIR_Coverage, 1838, 1493 GIR_Done, 1494 // Label 130: @2130 1495 GIM_Reject, 1496 // Label 116: @2131 1497 GIM_Try, /*On fail goto*//*Label 131*/ 2162, // Rule ID 875 // 1498 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1499 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1500 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 1502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 1503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 1504 // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 1505 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D, 1506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1507 // GIR_Coverage, 875, 1508 GIR_Done, 1509 // Label 131: @2162 1510 GIM_Reject, 1511 // Label 117: @2163 1512 GIM_Try, /*On fail goto*//*Label 132*/ 2194, // Rule ID 874 // 1513 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1514 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1515 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 1517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 1518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 1519 // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 1520 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W, 1521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1522 // GIR_Coverage, 874, 1523 GIR_Done, 1524 // Label 132: @2194 1525 GIM_Reject, 1526 // Label 118: @2195 1527 GIM_Try, /*On fail goto*//*Label 133*/ 2226, // Rule ID 873 // 1528 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1529 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 1530 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 1531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 1532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 1533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 1534 // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 1535 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H, 1536 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1537 // GIR_Coverage, 873, 1538 GIR_Done, 1539 // Label 133: @2226 1540 GIM_Reject, 1541 // Label 119: @2227 1542 GIM_Try, /*On fail goto*//*Label 134*/ 2258, // Rule ID 872 // 1543 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1544 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 1545 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 1546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 1547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1549 // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1550 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B, 1551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1552 // GIR_Coverage, 872, 1553 GIR_Done, 1554 // Label 134: @2258 1555 GIM_Reject, 1556 // Label 120: @2259 1557 GIM_Reject, 1558 // Label 3: @2260 1559 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 141*/ 2480, 1560 /*GILLT_s32*//*Label 135*/ 2274, 1561 /*GILLT_s64*//*Label 136*/ 2320, 0, 1562 /*GILLT_v2s64*//*Label 137*/ 2352, 0, 1563 /*GILLT_v4s32*//*Label 138*/ 2384, 1564 /*GILLT_v8s16*//*Label 139*/ 2416, 1565 /*GILLT_v16s8*//*Label 140*/ 2448, 1566 // Label 135: @2274 1567 GIM_Try, /*On fail goto*//*Label 142*/ 2319, 1568 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1569 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1573 GIM_Try, /*On fail goto*//*Label 143*/ 2307, // Rule ID 298 // 1574 GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, 1575 // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1576 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV, 1577 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1578 // GIR_Coverage, 298, 1579 GIR_Done, 1580 // Label 143: @2307 1581 GIM_Try, /*On fail goto*//*Label 144*/ 2318, // Rule ID 1129 // 1582 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 1583 // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1584 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6, 1585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1586 // GIR_Coverage, 1129, 1587 GIR_Done, 1588 // Label 144: @2318 1589 GIM_Reject, 1590 // Label 142: @2319 1591 GIM_Reject, 1592 // Label 136: @2320 1593 GIM_Try, /*On fail goto*//*Label 145*/ 2351, // Rule ID 313 // 1594 GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, 1595 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1596 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 1598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 1599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 1600 // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 1601 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV, 1602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1603 // GIR_Coverage, 313, 1604 GIR_Done, 1605 // Label 145: @2351 1606 GIM_Reject, 1607 // Label 137: @2352 1608 GIM_Try, /*On fail goto*//*Label 146*/ 2383, // Rule ID 615 // 1609 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1610 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1611 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 1613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 1614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 1615 // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 1616 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D, 1617 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1618 // GIR_Coverage, 615, 1619 GIR_Done, 1620 // Label 146: @2383 1621 GIM_Reject, 1622 // Label 138: @2384 1623 GIM_Try, /*On fail goto*//*Label 147*/ 2415, // Rule ID 614 // 1624 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1625 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1626 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 1628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 1629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 1630 // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 1631 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W, 1632 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1633 // GIR_Coverage, 614, 1634 GIR_Done, 1635 // Label 147: @2415 1636 GIM_Reject, 1637 // Label 139: @2416 1638 GIM_Try, /*On fail goto*//*Label 148*/ 2447, // Rule ID 613 // 1639 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1640 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 1641 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 1642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 1643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 1644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 1645 // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 1646 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H, 1647 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1648 // GIR_Coverage, 613, 1649 GIR_Done, 1650 // Label 148: @2447 1651 GIM_Reject, 1652 // Label 140: @2448 1653 GIM_Try, /*On fail goto*//*Label 149*/ 2479, // Rule ID 612 // 1654 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1655 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 1656 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 1657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 1658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1660 // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1661 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B, 1662 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1663 // GIR_Coverage, 612, 1664 GIR_Done, 1665 // Label 149: @2479 1666 GIM_Reject, 1667 // Label 141: @2480 1668 GIM_Reject, 1669 // Label 4: @2481 1670 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 156*/ 2701, 1671 /*GILLT_s32*//*Label 150*/ 2495, 1672 /*GILLT_s64*//*Label 151*/ 2541, 0, 1673 /*GILLT_v2s64*//*Label 152*/ 2573, 0, 1674 /*GILLT_v4s32*//*Label 153*/ 2605, 1675 /*GILLT_v8s16*//*Label 154*/ 2637, 1676 /*GILLT_v16s8*//*Label 155*/ 2669, 1677 // Label 150: @2495 1678 GIM_Try, /*On fail goto*//*Label 157*/ 2540, 1679 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1680 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1684 GIM_Try, /*On fail goto*//*Label 158*/ 2528, // Rule ID 299 // 1685 GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, 1686 // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1687 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU, 1688 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1689 // GIR_Coverage, 299, 1690 GIR_Done, 1691 // Label 158: @2528 1692 GIM_Try, /*On fail goto*//*Label 159*/ 2539, // Rule ID 1130 // 1693 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 1694 // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1695 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6, 1696 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1697 // GIR_Coverage, 1130, 1698 GIR_Done, 1699 // Label 159: @2539 1700 GIM_Reject, 1701 // Label 157: @2540 1702 GIM_Reject, 1703 // Label 151: @2541 1704 GIM_Try, /*On fail goto*//*Label 160*/ 2572, // Rule ID 314 // 1705 GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, 1706 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1707 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 1709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 1710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 1711 // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 1712 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU, 1713 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1714 // GIR_Coverage, 314, 1715 GIR_Done, 1716 // Label 160: @2572 1717 GIM_Reject, 1718 // Label 152: @2573 1719 GIM_Try, /*On fail goto*//*Label 161*/ 2604, // Rule ID 619 // 1720 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1721 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1722 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 1724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 1725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 1726 // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 1727 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D, 1728 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1729 // GIR_Coverage, 619, 1730 GIR_Done, 1731 // Label 161: @2604 1732 GIM_Reject, 1733 // Label 153: @2605 1734 GIM_Try, /*On fail goto*//*Label 162*/ 2636, // Rule ID 618 // 1735 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1736 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1737 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 1739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 1740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 1741 // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 1742 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W, 1743 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1744 // GIR_Coverage, 618, 1745 GIR_Done, 1746 // Label 162: @2636 1747 GIM_Reject, 1748 // Label 154: @2637 1749 GIM_Try, /*On fail goto*//*Label 163*/ 2668, // Rule ID 617 // 1750 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1751 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 1752 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 1753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 1754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 1755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 1756 // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 1757 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H, 1758 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1759 // GIR_Coverage, 617, 1760 GIR_Done, 1761 // Label 163: @2668 1762 GIM_Reject, 1763 // Label 155: @2669 1764 GIM_Try, /*On fail goto*//*Label 164*/ 2700, // Rule ID 616 // 1765 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1766 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 1767 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 1768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 1769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1771 // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1772 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B, 1773 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1774 // GIR_Coverage, 616, 1775 GIR_Done, 1776 // Label 164: @2700 1777 GIM_Reject, 1778 // Label 156: @2701 1779 GIM_Reject, 1780 // Label 5: @2702 1781 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 171*/ 2922, 1782 /*GILLT_s32*//*Label 165*/ 2716, 1783 /*GILLT_s64*//*Label 166*/ 2762, 0, 1784 /*GILLT_v2s64*//*Label 167*/ 2794, 0, 1785 /*GILLT_v4s32*//*Label 168*/ 2826, 1786 /*GILLT_v8s16*//*Label 169*/ 2858, 1787 /*GILLT_v16s8*//*Label 170*/ 2890, 1788 // Label 165: @2716 1789 GIM_Try, /*On fail goto*//*Label 172*/ 2761, 1790 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1791 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1795 GIM_Try, /*On fail goto*//*Label 173*/ 2749, // Rule ID 300 // 1796 GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, 1797 // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1798 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD, 1799 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1800 // GIR_Coverage, 300, 1801 GIR_Done, 1802 // Label 173: @2749 1803 GIM_Try, /*On fail goto*//*Label 174*/ 2760, // Rule ID 1134 // 1804 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 1805 // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1806 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6, 1807 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1808 // GIR_Coverage, 1134, 1809 GIR_Done, 1810 // Label 174: @2760 1811 GIM_Reject, 1812 // Label 172: @2761 1813 GIM_Reject, 1814 // Label 166: @2762 1815 GIM_Try, /*On fail goto*//*Label 175*/ 2793, // Rule ID 315 // 1816 GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, 1817 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1818 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 1820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 1821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 1822 // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 1823 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD, 1824 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1825 // GIR_Coverage, 315, 1826 GIR_Done, 1827 // Label 175: @2793 1828 GIM_Reject, 1829 // Label 167: @2794 1830 GIM_Try, /*On fail goto*//*Label 176*/ 2825, // Rule ID 855 // 1831 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1832 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1833 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 1835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 1836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 1837 // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 1838 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D, 1839 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1840 // GIR_Coverage, 855, 1841 GIR_Done, 1842 // Label 176: @2825 1843 GIM_Reject, 1844 // Label 168: @2826 1845 GIM_Try, /*On fail goto*//*Label 177*/ 2857, // Rule ID 854 // 1846 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1847 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1848 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 1850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 1851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 1852 // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 1853 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W, 1854 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1855 // GIR_Coverage, 854, 1856 GIR_Done, 1857 // Label 177: @2857 1858 GIM_Reject, 1859 // Label 169: @2858 1860 GIM_Try, /*On fail goto*//*Label 178*/ 2889, // Rule ID 853 // 1861 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1862 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 1863 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 1864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 1865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 1866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 1867 // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 1868 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H, 1869 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1870 // GIR_Coverage, 853, 1871 GIR_Done, 1872 // Label 178: @2889 1873 GIM_Reject, 1874 // Label 170: @2890 1875 GIM_Try, /*On fail goto*//*Label 179*/ 2921, // Rule ID 852 // 1876 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1877 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 1878 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 1879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 1880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1882 // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1883 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B, 1884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1885 // GIR_Coverage, 852, 1886 GIR_Done, 1887 // Label 179: @2921 1888 GIM_Reject, 1889 // Label 171: @2922 1890 GIM_Reject, 1891 // Label 6: @2923 1892 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 186*/ 3143, 1893 /*GILLT_s32*//*Label 180*/ 2937, 1894 /*GILLT_s64*//*Label 181*/ 2983, 0, 1895 /*GILLT_v2s64*//*Label 182*/ 3015, 0, 1896 /*GILLT_v4s32*//*Label 183*/ 3047, 1897 /*GILLT_v8s16*//*Label 184*/ 3079, 1898 /*GILLT_v16s8*//*Label 185*/ 3111, 1899 // Label 180: @2937 1900 GIM_Try, /*On fail goto*//*Label 187*/ 2982, 1901 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1902 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 1904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 1905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 1906 GIM_Try, /*On fail goto*//*Label 188*/ 2970, // Rule ID 301 // 1907 GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, 1908 // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1909 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU, 1910 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1911 // GIR_Coverage, 301, 1912 GIR_Done, 1913 // Label 188: @2970 1914 GIM_Try, /*On fail goto*//*Label 189*/ 2981, // Rule ID 1135 // 1915 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 1916 // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 1917 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6, 1918 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1919 // GIR_Coverage, 1135, 1920 GIR_Done, 1921 // Label 189: @2981 1922 GIM_Reject, 1923 // Label 187: @2982 1924 GIM_Reject, 1925 // Label 181: @2983 1926 GIM_Try, /*On fail goto*//*Label 190*/ 3014, // Rule ID 316 // 1927 GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, 1928 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1929 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 1931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 1932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 1933 // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 1934 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU, 1935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1936 // GIR_Coverage, 316, 1937 GIR_Done, 1938 // Label 190: @3014 1939 GIM_Reject, 1940 // Label 182: @3015 1941 GIM_Try, /*On fail goto*//*Label 191*/ 3046, // Rule ID 859 // 1942 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1943 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1944 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 1946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 1947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 1948 // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 1949 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D, 1950 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1951 // GIR_Coverage, 859, 1952 GIR_Done, 1953 // Label 191: @3046 1954 GIM_Reject, 1955 // Label 183: @3047 1956 GIM_Try, /*On fail goto*//*Label 192*/ 3078, // Rule ID 858 // 1957 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1958 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1959 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 1961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 1962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 1963 // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 1964 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W, 1965 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1966 // GIR_Coverage, 858, 1967 GIR_Done, 1968 // Label 192: @3078 1969 GIM_Reject, 1970 // Label 184: @3079 1971 GIM_Try, /*On fail goto*//*Label 193*/ 3110, // Rule ID 857 // 1972 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1973 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 1974 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 1975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 1976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 1977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 1978 // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 1979 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H, 1980 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1981 // GIR_Coverage, 857, 1982 GIR_Done, 1983 // Label 193: @3110 1984 GIM_Reject, 1985 // Label 185: @3111 1986 GIM_Try, /*On fail goto*//*Label 194*/ 3142, // Rule ID 856 // 1987 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 1988 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 1989 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 1990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 1991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 1992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 1993 // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 1994 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B, 1995 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1996 // GIR_Coverage, 856, 1997 GIR_Done, 1998 // Label 194: @3142 1999 GIM_Reject, 2000 // Label 186: @3143 2001 GIM_Reject, 2002 // Label 7: @3144 2003 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 201*/ 3587, 2004 /*GILLT_s32*//*Label 195*/ 3158, 2005 /*GILLT_s64*//*Label 196*/ 3371, 0, 2006 /*GILLT_v2s64*//*Label 197*/ 3459, 0, 2007 /*GILLT_v4s32*//*Label 198*/ 3491, 2008 /*GILLT_v8s16*//*Label 199*/ 3523, 2009 /*GILLT_v16s8*//*Label 200*/ 3555, 2010 // Label 195: @3158 2011 GIM_Try, /*On fail goto*//*Label 202*/ 3370, 2012 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2013 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2014 GIM_Try, /*On fail goto*//*Label 203*/ 3211, // Rule ID 2069 // 2015 GIM_CheckFeatures, GIFBS_InMicroMips, 2016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 2017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 2018 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2019 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2020 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16, 2021 // MIs[1] Operand 1 2022 // No operand predicates 2023 GIM_CheckIsSafeToFold, /*InsnID*/1, 2024 // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) 2025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM, 2026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2028 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 2029 GIR_EraseFromParent, /*InsnID*/0, 2030 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2031 // GIR_Coverage, 2069, 2032 GIR_Done, 2033 // Label 203: @3211 2034 GIM_Try, /*On fail goto*//*Label 204*/ 3254, // Rule ID 2221 // 2035 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 2036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 2037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 2038 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2039 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2040 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16, 2041 // MIs[1] Operand 1 2042 // No operand predicates 2043 GIM_CheckIsSafeToFold, /*InsnID*/1, 2044 // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) 2045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6, 2046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2048 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 2049 GIR_EraseFromParent, /*InsnID*/0, 2050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2051 // GIR_Coverage, 2221, 2052 GIR_Done, 2053 // Label 204: @3254 2054 GIM_Try, /*On fail goto*//*Label 205*/ 3277, // Rule ID 39 // 2055 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 2056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2059 // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2060 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND, 2061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2062 // GIR_Coverage, 39, 2063 GIR_Done, 2064 // Label 205: @3277 2065 GIM_Try, /*On fail goto*//*Label 206*/ 3300, // Rule ID 1029 // 2066 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 2067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 2068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 2069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, 2070 // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) 2071 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM, 2072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2073 // GIR_Coverage, 1029, 2074 GIR_Done, 2075 // Label 206: @3300 2076 GIM_Try, /*On fail goto*//*Label 207*/ 3323, // Rule ID 1045 // 2077 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 2078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2081 // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2082 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM, 2083 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2084 // GIR_Coverage, 1045, 2085 GIR_Done, 2086 // Label 207: @3323 2087 GIM_Try, /*On fail goto*//*Label 208*/ 3346, // Rule ID 1127 // 2088 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 2089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2092 // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2093 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6, 2094 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2095 // GIR_Coverage, 1127, 2096 GIR_Done, 2097 // Label 208: @3346 2098 GIM_Try, /*On fail goto*//*Label 209*/ 3369, // Rule ID 1736 // 2099 GIM_CheckFeatures, GIFBS_InMips16Mode, 2100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 2101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 2102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 2103 // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) 2104 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16, 2105 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2106 // GIR_Coverage, 1736, 2107 GIR_Done, 2108 // Label 209: @3369 2109 GIM_Reject, 2110 // Label 202: @3370 2111 GIM_Reject, 2112 // Label 196: @3371 2113 GIM_Try, /*On fail goto*//*Label 210*/ 3458, 2114 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 2115 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 2116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 2117 GIM_Try, /*On fail goto*//*Label 211*/ 3438, // Rule ID 241 // 2118 GIM_CheckFeatures, GIFBS_HasCnMips, 2119 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2120 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2121 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2122 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2123 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 2124 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 2125 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, 2126 GIM_CheckIsSafeToFold, /*InsnID*/1, 2127 // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 2128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu, 2129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs 2131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt 2132 GIR_EraseFromParent, /*InsnID*/0, 2133 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2134 // GIR_Coverage, 241, 2135 GIR_Done, 2136 // Label 211: @3438 2137 GIM_Try, /*On fail goto*//*Label 212*/ 3457, // Rule ID 184 // 2138 GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, 2139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 2140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 2141 // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 2142 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64, 2143 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2144 // GIR_Coverage, 184, 2145 GIR_Done, 2146 // Label 212: @3457 2147 GIM_Reject, 2148 // Label 210: @3458 2149 GIM_Reject, 2150 // Label 197: @3459 2151 GIM_Try, /*On fail goto*//*Label 213*/ 3490, // Rule ID 486 // 2152 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2153 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 2154 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 2155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 2157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 2158 // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 2159 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO, 2160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2161 // GIR_Coverage, 486, 2162 GIR_Done, 2163 // Label 213: @3490 2164 GIM_Reject, 2165 // Label 198: @3491 2166 GIM_Try, /*On fail goto*//*Label 214*/ 3522, // Rule ID 485 // 2167 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2168 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2169 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 2170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 2171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 2172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 2173 // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 2174 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO, 2175 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2176 // GIR_Coverage, 485, 2177 GIR_Done, 2178 // Label 214: @3522 2179 GIM_Reject, 2180 // Label 199: @3523 2181 GIM_Try, /*On fail goto*//*Label 215*/ 3554, // Rule ID 484 // 2182 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2183 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2184 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 2185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 2186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 2187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 2188 // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 2189 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO, 2190 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2191 // GIR_Coverage, 484, 2192 GIR_Done, 2193 // Label 215: @3554 2194 GIM_Reject, 2195 // Label 200: @3555 2196 GIM_Try, /*On fail goto*//*Label 216*/ 3586, // Rule ID 483 // 2197 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2198 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2199 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 2200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 2201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 2202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 2203 // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 2204 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V, 2205 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2206 // GIR_Coverage, 483, 2207 GIR_Done, 2208 // Label 216: @3586 2209 GIM_Reject, 2210 // Label 201: @3587 2211 GIM_Reject, 2212 // Label 8: @3588 2213 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 223*/ 3889, 2214 /*GILLT_s32*//*Label 217*/ 3602, 2215 /*GILLT_s64*//*Label 218*/ 3729, 0, 2216 /*GILLT_v2s64*//*Label 219*/ 3761, 0, 2217 /*GILLT_v4s32*//*Label 220*/ 3793, 2218 /*GILLT_v8s16*//*Label 221*/ 3825, 2219 /*GILLT_v16s8*//*Label 222*/ 3857, 2220 // Label 217: @3602 2221 GIM_Try, /*On fail goto*//*Label 224*/ 3728, 2222 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2223 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2224 GIM_Try, /*On fail goto*//*Label 225*/ 3635, // Rule ID 40 // 2225 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 2226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2229 // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2230 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR, 2231 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2232 // GIR_Coverage, 40, 2233 GIR_Done, 2234 // Label 225: @3635 2235 GIM_Try, /*On fail goto*//*Label 226*/ 3658, // Rule ID 1031 // 2236 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 2237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 2238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 2239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, 2240 // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) 2241 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM, 2242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2243 // GIR_Coverage, 1031, 2244 GIR_Done, 2245 // Label 226: @3658 2246 GIM_Try, /*On fail goto*//*Label 227*/ 3681, // Rule ID 1046 // 2247 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 2248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2251 // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2252 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM, 2253 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2254 // GIR_Coverage, 1046, 2255 GIR_Done, 2256 // Label 227: @3681 2257 GIM_Try, /*On fail goto*//*Label 228*/ 3704, // Rule ID 1140 // 2258 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 2259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2262 // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2263 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6, 2264 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2265 // GIR_Coverage, 1140, 2266 GIR_Done, 2267 // Label 228: @3704 2268 GIM_Try, /*On fail goto*//*Label 229*/ 3727, // Rule ID 1738 // 2269 GIM_CheckFeatures, GIFBS_InMips16Mode, 2270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 2271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 2272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 2273 // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) 2274 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16, 2275 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2276 // GIR_Coverage, 1738, 2277 GIR_Done, 2278 // Label 229: @3727 2279 GIM_Reject, 2280 // Label 224: @3728 2281 GIM_Reject, 2282 // Label 218: @3729 2283 GIM_Try, /*On fail goto*//*Label 230*/ 3760, // Rule ID 185 // 2284 GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, 2285 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 2286 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 2287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 2288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 2289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 2290 // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 2291 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64, 2292 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2293 // GIR_Coverage, 185, 2294 GIR_Done, 2295 // Label 230: @3760 2296 GIM_Reject, 2297 // Label 219: @3761 2298 GIM_Try, /*On fail goto*//*Label 231*/ 3792, // Rule ID 892 // 2299 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2300 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 2301 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 2302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 2304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 2305 // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 2306 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO, 2307 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2308 // GIR_Coverage, 892, 2309 GIR_Done, 2310 // Label 231: @3792 2311 GIM_Reject, 2312 // Label 220: @3793 2313 GIM_Try, /*On fail goto*//*Label 232*/ 3824, // Rule ID 891 // 2314 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2315 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2316 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 2317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 2318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 2319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 2320 // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 2321 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO, 2322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2323 // GIR_Coverage, 891, 2324 GIR_Done, 2325 // Label 232: @3824 2326 GIM_Reject, 2327 // Label 221: @3825 2328 GIM_Try, /*On fail goto*//*Label 233*/ 3856, // Rule ID 890 // 2329 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2330 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2331 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 2332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 2333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 2334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 2335 // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 2336 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO, 2337 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2338 // GIR_Coverage, 890, 2339 GIR_Done, 2340 // Label 233: @3856 2341 GIM_Reject, 2342 // Label 222: @3857 2343 GIM_Try, /*On fail goto*//*Label 234*/ 3888, // Rule ID 889 // 2344 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2345 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2346 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 2347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 2348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 2349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 2350 // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 2351 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V, 2352 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2353 // GIR_Coverage, 889, 2354 GIR_Done, 2355 // Label 234: @3888 2356 GIM_Reject, 2357 // Label 223: @3889 2358 GIM_Reject, 2359 // Label 9: @3890 2360 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 241*/ 4683, 2361 /*GILLT_s32*//*Label 235*/ 3904, 2362 /*GILLT_s64*//*Label 236*/ 4467, 0, 2363 /*GILLT_v2s64*//*Label 237*/ 4555, 0, 2364 /*GILLT_v4s32*//*Label 238*/ 4587, 2365 /*GILLT_v8s16*//*Label 239*/ 4619, 2366 /*GILLT_v16s8*//*Label 240*/ 4651, 2367 // Label 235: @3904 2368 GIM_Try, /*On fail goto*//*Label 242*/ 4466, 2369 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2370 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2371 GIM_Try, /*On fail goto*//*Label 243*/ 3971, // Rule ID 42 // 2372 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 2373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2374 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2375 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, 2376 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2377 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2378 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2379 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2380 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2381 GIM_CheckIsSafeToFold, /*InsnID*/1, 2382 // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, 2384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs 2386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt 2387 GIR_EraseFromParent, /*InsnID*/0, 2388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2389 // GIR_Coverage, 42, 2390 GIR_Done, 2391 // Label 243: @3971 2392 GIM_Try, /*On fail goto*//*Label 244*/ 4028, // Rule ID 1048 // 2393 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 2394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2395 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2396 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, 2397 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2398 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2399 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2400 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2401 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2402 GIM_CheckIsSafeToFold, /*InsnID*/1, 2403 // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2404 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM, 2405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs 2407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt 2408 GIR_EraseFromParent, /*InsnID*/0, 2409 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2410 // GIR_Coverage, 1048, 2411 GIR_Done, 2412 // Label 244: @4028 2413 GIM_Try, /*On fail goto*//*Label 245*/ 4085, // Rule ID 1139 // 2414 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 2415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2416 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2417 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, 2418 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2419 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2420 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2421 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2422 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2423 GIM_CheckIsSafeToFold, /*InsnID*/1, 2424 // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2425 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, 2426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs 2428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt 2429 GIR_EraseFromParent, /*InsnID*/0, 2430 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2431 // GIR_Coverage, 1139, 2432 GIR_Done, 2433 // Label 245: @4085 2434 GIM_Try, /*On fail goto*//*Label 246*/ 4117, // Rule ID 1166 // 2435 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 2436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 2437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 2438 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2439 // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs) 2440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6, 2441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 2442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 2443 GIR_EraseFromParent, /*InsnID*/0, 2444 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2445 // GIR_Coverage, 1166, 2446 GIR_Done, 2447 // Label 246: @4117 2448 GIM_Try, /*On fail goto*//*Label 247*/ 4149, // Rule ID 1030 // 2449 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 2450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 2451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 2452 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2453 // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs) 2454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM, 2455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 2456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 2457 GIR_EraseFromParent, /*InsnID*/0, 2458 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2459 // GIR_Coverage, 1030, 2460 GIR_Done, 2461 // Label 247: @4149 2462 GIM_Try, /*On fail goto*//*Label 248*/ 4184, // Rule ID 1353 // 2463 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 2464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2466 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2467 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] }) 2468 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, 2469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 2471 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, 2472 GIR_EraseFromParent, /*InsnID*/0, 2473 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2474 // GIR_Coverage, 1353, 2475 GIR_Done, 2476 // Label 248: @4184 2477 GIM_Try, /*On fail goto*//*Label 249*/ 4216, // Rule ID 1733 // 2478 GIM_CheckFeatures, GIFBS_InMips16Mode, 2479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 2480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 2481 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2482 // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r) 2483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16, 2484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx 2485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r 2486 GIR_EraseFromParent, /*InsnID*/0, 2487 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2488 // GIR_Coverage, 1733, 2489 GIR_Done, 2490 // Label 249: @4216 2491 GIM_Try, /*On fail goto*//*Label 250*/ 4248, // Rule ID 2064 // 2492 GIM_CheckFeatures, GIFBS_InMicroMips, 2493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 2494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 2495 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2496 // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in) 2497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM, 2498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 2499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 2500 GIR_EraseFromParent, /*InsnID*/0, 2501 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2502 // GIR_Coverage, 2064, 2503 GIR_Done, 2504 // Label 250: @4248 2505 GIM_Try, /*On fail goto*//*Label 251*/ 4283, // Rule ID 2065 // 2506 GIM_CheckFeatures, GIFBS_InMicroMips, 2507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2509 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2510 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] }) 2511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM, 2512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 2514 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, 2515 GIR_EraseFromParent, /*InsnID*/0, 2516 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2517 // GIR_Coverage, 2065, 2518 GIR_Done, 2519 // Label 251: @4283 2520 GIM_Try, /*On fail goto*//*Label 252*/ 4315, // Rule ID 2224 // 2521 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 2522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 2523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 2524 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2525 // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in) 2526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6, 2527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 2528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 2529 GIR_EraseFromParent, /*InsnID*/0, 2530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2531 // GIR_Coverage, 2224, 2532 GIR_Done, 2533 // Label 252: @4315 2534 GIM_Try, /*On fail goto*//*Label 253*/ 4350, // Rule ID 2225 // 2535 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 2536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2538 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2539 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] }) 2540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, 2541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 2543 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, 2544 GIR_EraseFromParent, /*InsnID*/0, 2545 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2546 // GIR_Coverage, 2225, 2547 GIR_Done, 2548 // Label 253: @4350 2549 GIM_Try, /*On fail goto*//*Label 254*/ 4373, // Rule ID 41 // 2550 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 2551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2554 // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2555 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR, 2556 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2557 // GIR_Coverage, 41, 2558 GIR_Done, 2559 // Label 254: @4373 2560 GIM_Try, /*On fail goto*//*Label 255*/ 4396, // Rule ID 1033 // 2561 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 2562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 2563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 2564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, 2565 // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) 2566 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM, 2567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2568 // GIR_Coverage, 1033, 2569 GIR_Done, 2570 // Label 255: @4396 2571 GIM_Try, /*On fail goto*//*Label 256*/ 4419, // Rule ID 1047 // 2572 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 2573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2576 // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2577 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM, 2578 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2579 // GIR_Coverage, 1047, 2580 GIR_Done, 2581 // Label 256: @4419 2582 GIM_Try, /*On fail goto*//*Label 257*/ 4442, // Rule ID 1143 // 2583 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 2584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 2587 // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 2588 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6, 2589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2590 // GIR_Coverage, 1143, 2591 GIR_Done, 2592 // Label 257: @4442 2593 GIM_Try, /*On fail goto*//*Label 258*/ 4465, // Rule ID 1740 // 2594 GIM_CheckFeatures, GIFBS_InMips16Mode, 2595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 2596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 2597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 2598 // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) 2599 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16, 2600 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2601 // GIR_Coverage, 1740, 2602 GIR_Done, 2603 // Label 258: @4465 2604 GIM_Reject, 2605 // Label 242: @4466 2606 GIM_Reject, 2607 // Label 236: @4467 2608 GIM_Try, /*On fail goto*//*Label 259*/ 4554, 2609 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 2610 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 2611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 2612 GIM_Try, /*On fail goto*//*Label 260*/ 4534, // Rule ID 187 // 2613 GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, 2614 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2615 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, 2616 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2617 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2618 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 2619 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 2620 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 2621 GIM_CheckIsSafeToFold, /*InsnID*/1, 2622 // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 2623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64, 2624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs 2626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt 2627 GIR_EraseFromParent, /*InsnID*/0, 2628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2629 // GIR_Coverage, 187, 2630 GIR_Done, 2631 // Label 260: @4534 2632 GIM_Try, /*On fail goto*//*Label 261*/ 4553, // Rule ID 186 // 2633 GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, 2634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 2635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 2636 // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) 2637 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64, 2638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2639 // GIR_Coverage, 186, 2640 GIR_Done, 2641 // Label 261: @4553 2642 GIM_Reject, 2643 // Label 259: @4554 2644 GIM_Reject, 2645 // Label 237: @4555 2646 GIM_Try, /*On fail goto*//*Label 262*/ 4586, // Rule ID 1008 // 2647 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2648 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 2649 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 2650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 2652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 2653 // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 2654 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO, 2655 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2656 // GIR_Coverage, 1008, 2657 GIR_Done, 2658 // Label 262: @4586 2659 GIM_Reject, 2660 // Label 238: @4587 2661 GIM_Try, /*On fail goto*//*Label 263*/ 4618, // Rule ID 1007 // 2662 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2663 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2664 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 2665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 2666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 2667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 2668 // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 2669 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO, 2670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2671 // GIR_Coverage, 1007, 2672 GIR_Done, 2673 // Label 263: @4618 2674 GIM_Reject, 2675 // Label 239: @4619 2676 GIM_Try, /*On fail goto*//*Label 264*/ 4650, // Rule ID 1006 // 2677 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2678 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2679 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 2680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 2681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 2682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 2683 // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 2684 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO, 2685 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2686 // GIR_Coverage, 1006, 2687 GIR_Done, 2688 // Label 264: @4650 2689 GIM_Reject, 2690 // Label 240: @4651 2691 GIM_Try, /*On fail goto*//*Label 265*/ 4682, // Rule ID 1005 // 2692 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 2693 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2694 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 2695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 2696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 2697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 2698 // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 2699 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V, 2700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2701 // GIR_Coverage, 1005, 2702 GIR_Done, 2703 // Label 265: @4682 2704 GIM_Reject, 2705 // Label 241: @4683 2706 GIM_Reject, 2707 // Label 10: @4684 2708 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 274*/ 8336, 2709 /*GILLT_s32*//*Label 266*/ 4698, 2710 /*GILLT_s64*//*Label 267*/ 4937, 2711 /*GILLT_v2s16*//*Label 268*/ 4983, 2712 /*GILLT_v2s64*//*Label 269*/ 5029, 2713 /*GILLT_v4s8*//*Label 270*/ 6002, 2714 /*GILLT_v4s32*//*Label 271*/ 6048, 2715 /*GILLT_v8s16*//*Label 272*/ 6951, 2716 /*GILLT_v16s8*//*Label 273*/ 7749, 2717 // Label 266: @4698 2718 GIM_Try, /*On fail goto*//*Label 275*/ 4721, // Rule ID 117 // 2719 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 2720 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 2723 // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) 2724 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1, 2725 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2726 // GIR_Coverage, 117, 2727 GIR_Done, 2728 // Label 275: @4721 2729 GIM_Try, /*On fail goto*//*Label 276*/ 4744, // Rule ID 118 // 2730 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 2731 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 2733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2734 // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) 2735 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1, 2736 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2737 // GIR_Coverage, 118, 2738 GIR_Done, 2739 // Label 276: @4744 2740 GIM_Try, /*On fail goto*//*Label 277*/ 4767, // Rule ID 1119 // 2741 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, 2742 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 2745 // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) 2746 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM, 2747 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2748 // GIR_Coverage, 1119, 2749 GIR_Done, 2750 // Label 277: @4767 2751 GIM_Try, /*On fail goto*//*Label 278*/ 4790, // Rule ID 1120 // 2752 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, 2753 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 2755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2756 // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) 2757 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM, 2758 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2759 // GIR_Coverage, 1120, 2760 GIR_Done, 2761 // Label 278: @4790 2762 GIM_Try, /*On fail goto*//*Label 279*/ 4813, // Rule ID 1132 // 2763 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, 2764 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 2766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2767 // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) 2768 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6, 2769 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2770 // GIR_Coverage, 1132, 2771 GIR_Done, 2772 // Label 279: @4813 2773 GIM_Try, /*On fail goto*//*Label 280*/ 4836, // Rule ID 1133 // 2774 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, 2775 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 2778 // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) 2779 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6, 2780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2781 // GIR_Coverage, 1133, 2782 GIR_Done, 2783 // Label 280: @4836 2784 GIM_Try, /*On fail goto*//*Label 281*/ 4861, // Rule ID 1821 // 2785 GIM_CheckFeatures, GIFBS_HasDSP, 2786 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 2787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 2789 // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] }) 2790 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2791 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11, 2792 // GIR_Coverage, 1821, 2793 GIR_Done, 2794 // Label 281: @4861 2795 GIM_Try, /*On fail goto*//*Label 282*/ 4886, // Rule ID 1822 // 2796 GIM_CheckFeatures, GIFBS_HasDSP, 2797 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 2798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 2799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 2800 // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] }) 2801 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2802 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11, 2803 // GIR_Coverage, 1822, 2804 GIR_Done, 2805 // Label 282: @4886 2806 GIM_Try, /*On fail goto*//*Label 283*/ 4911, // Rule ID 1825 // 2807 GIM_CheckFeatures, GIFBS_HasDSP, 2808 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 2809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 2810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 2811 // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] }) 2812 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2813 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8, 2814 // GIR_Coverage, 1825, 2815 GIR_Done, 2816 // Label 283: @4911 2817 GIM_Try, /*On fail goto*//*Label 284*/ 4936, // Rule ID 1826 // 2818 GIM_CheckFeatures, GIFBS_HasDSP, 2819 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 2820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 2821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 2822 // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] }) 2823 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2824 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8, 2825 // GIR_Coverage, 1826, 2826 GIR_Done, 2827 // Label 284: @4936 2828 GIM_Reject, 2829 // Label 267: @4937 2830 GIM_Try, /*On fail goto*//*Label 285*/ 4982, 2831 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 2832 GIM_Try, /*On fail goto*//*Label 286*/ 4962, // Rule ID 119 // 2833 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 2834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 2835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 2836 // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) 2837 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1, 2838 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2839 // GIR_Coverage, 119, 2840 GIR_Done, 2841 // Label 286: @4962 2842 GIM_Try, /*On fail goto*//*Label 287*/ 4981, // Rule ID 120 // 2843 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 2844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 2845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 2846 // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) 2847 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1, 2848 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2849 // GIR_Coverage, 120, 2850 GIR_Done, 2851 // Label 287: @4981 2852 GIM_Reject, 2853 // Label 285: @4982 2854 GIM_Reject, 2855 // Label 268: @4983 2856 GIM_Try, /*On fail goto*//*Label 288*/ 5028, 2857 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 2859 GIM_Try, /*On fail goto*//*Label 289*/ 5010, // Rule ID 1823 // 2860 GIM_CheckFeatures, GIFBS_HasDSP, 2861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 2862 // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] }) 2863 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2864 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7, 2865 // GIR_Coverage, 1823, 2866 GIR_Done, 2867 // Label 289: @5010 2868 GIM_Try, /*On fail goto*//*Label 290*/ 5027, // Rule ID 1827 // 2869 GIM_CheckFeatures, GIFBS_HasDSP, 2870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 2871 // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] }) 2872 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2873 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7, 2874 // GIR_Coverage, 1827, 2875 GIR_Done, 2876 // Label 290: @5027 2877 GIM_Reject, 2878 // Label 288: @5028 2879 GIM_Reject, 2880 // Label 269: @5029 2881 GIM_Try, /*On fail goto*//*Label 291*/ 5050, // Rule ID 1908 // 2882 GIM_CheckFeatures, GIFBS_HasMSA, 2883 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 2884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2885 // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] }) 2886 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2887 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2888 // GIR_Coverage, 1908, 2889 GIR_Done, 2890 // Label 291: @5050 2891 GIM_Try, /*On fail goto*//*Label 292*/ 5071, // Rule ID 1911 // 2892 GIM_CheckFeatures, GIFBS_HasMSA, 2893 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 2894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2895 // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] }) 2896 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2897 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2898 // GIR_Coverage, 1911, 2899 GIR_Done, 2900 // Label 292: @5071 2901 GIM_Try, /*On fail goto*//*Label 293*/ 5092, // Rule ID 1928 // 2902 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2903 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2905 // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] }) 2906 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2907 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2908 // GIR_Coverage, 1928, 2909 GIR_Done, 2910 // Label 293: @5092 2911 GIM_Try, /*On fail goto*//*Label 294*/ 5113, // Rule ID 1929 // 2912 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2913 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2915 // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] }) 2916 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2917 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2918 // GIR_Coverage, 1929, 2919 GIR_Done, 2920 // Label 294: @5113 2921 GIM_Try, /*On fail goto*//*Label 295*/ 5134, // Rule ID 1930 // 2922 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2923 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2925 // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] }) 2926 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2927 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2928 // GIR_Coverage, 1930, 2929 GIR_Done, 2930 // Label 295: @5134 2931 GIM_Try, /*On fail goto*//*Label 296*/ 5155, // Rule ID 1931 // 2932 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2933 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2935 // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] }) 2936 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2937 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2938 // GIR_Coverage, 1931, 2939 GIR_Done, 2940 // Label 296: @5155 2941 GIM_Try, /*On fail goto*//*Label 297*/ 5176, // Rule ID 1932 // 2942 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2943 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2945 // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] }) 2946 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2947 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2948 // GIR_Coverage, 1932, 2949 GIR_Done, 2950 // Label 297: @5176 2951 GIM_Try, /*On fail goto*//*Label 298*/ 5197, // Rule ID 1938 // 2952 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2953 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2955 // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] }) 2956 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2957 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2958 // GIR_Coverage, 1938, 2959 GIR_Done, 2960 // Label 298: @5197 2961 GIM_Try, /*On fail goto*//*Label 299*/ 5218, // Rule ID 1939 // 2962 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2963 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2965 // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] }) 2966 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2967 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2968 // GIR_Coverage, 1939, 2969 GIR_Done, 2970 // Label 299: @5218 2971 GIM_Try, /*On fail goto*//*Label 300*/ 5239, // Rule ID 1940 // 2972 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2973 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2975 // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] }) 2976 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2977 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2978 // GIR_Coverage, 1940, 2979 GIR_Done, 2980 // Label 300: @5239 2981 GIM_Try, /*On fail goto*//*Label 301*/ 5260, // Rule ID 1941 // 2982 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2983 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2985 // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] }) 2986 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2987 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2988 // GIR_Coverage, 1941, 2989 GIR_Done, 2990 // Label 301: @5260 2991 GIM_Try, /*On fail goto*//*Label 302*/ 5281, // Rule ID 1942 // 2992 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 2993 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 2995 // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] }) 2996 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 2997 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 2998 // GIR_Coverage, 1942, 2999 GIR_Done, 3000 // Label 302: @5281 3001 GIM_Try, /*On fail goto*//*Label 303*/ 5381, // Rule ID 1947 // 3002 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3003 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3005 // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) 3006 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3007 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3008 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, 3009 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, 3010 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, 3011 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 3012 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 3013 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 3014 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, 3015 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 3016 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, 3017 GIR_AddImm, /*InsnID*/3, /*Imm*/27, 3018 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 3019 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3020 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3021 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 3022 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3023 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3024 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3025 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3026 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3027 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3030 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3031 GIR_EraseFromParent, /*InsnID*/0, 3032 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3033 // GIR_Coverage, 1947, 3034 GIR_Done, 3035 // Label 303: @5381 3036 GIM_Try, /*On fail goto*//*Label 304*/ 5481, // Rule ID 1948 // 3037 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3038 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3040 // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) 3041 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3042 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3043 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, 3044 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, 3045 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, 3046 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 3047 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 3048 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 3049 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, 3050 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 3051 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, 3052 GIR_AddImm, /*InsnID*/3, /*Imm*/27, 3053 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 3054 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3055 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3056 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 3057 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3058 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3059 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3060 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3061 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3062 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3065 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3066 GIR_EraseFromParent, /*InsnID*/0, 3067 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3068 // GIR_Coverage, 1948, 3069 GIR_Done, 3070 // Label 304: @5481 3071 GIM_Try, /*On fail goto*//*Label 305*/ 5546, // Rule ID 1952 // 3072 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3073 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3075 // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) 3076 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3077 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3078 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3079 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3080 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3081 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3082 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3083 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3084 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3085 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3086 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3089 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3090 GIR_EraseFromParent, /*InsnID*/0, 3091 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3092 // GIR_Coverage, 1952, 3093 GIR_Done, 3094 // Label 305: @5546 3095 GIM_Try, /*On fail goto*//*Label 306*/ 5611, // Rule ID 1953 // 3096 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3097 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3099 // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) 3100 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3101 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3102 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3103 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3104 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3105 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3106 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3107 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3108 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3109 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3110 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3113 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3114 GIR_EraseFromParent, /*InsnID*/0, 3115 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3116 // GIR_Coverage, 1953, 3117 GIR_Done, 3118 // Label 306: @5611 3119 GIM_Try, /*On fail goto*//*Label 307*/ 5676, // Rule ID 1957 // 3120 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3121 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3123 // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) 3124 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3125 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3126 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3127 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3128 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3129 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3130 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3131 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3132 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3133 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3134 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3137 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3138 GIR_EraseFromParent, /*InsnID*/0, 3139 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3140 // GIR_Coverage, 1957, 3141 GIR_Done, 3142 // Label 307: @5676 3143 GIM_Try, /*On fail goto*//*Label 308*/ 5741, // Rule ID 1958 // 3144 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3145 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3147 // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) 3148 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3149 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3150 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3151 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3152 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3153 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3154 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3155 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3156 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3157 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3158 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3161 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3162 GIR_EraseFromParent, /*InsnID*/0, 3163 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3164 // GIR_Coverage, 1958, 3165 GIR_Done, 3166 // Label 308: @5741 3167 GIM_Try, /*On fail goto*//*Label 309*/ 5806, // Rule ID 1962 // 3168 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3169 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3171 // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) 3172 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3173 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3174 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3175 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3176 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3177 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3178 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3179 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3180 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3181 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3182 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3185 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3186 GIR_EraseFromParent, /*InsnID*/0, 3187 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3188 // GIR_Coverage, 1962, 3189 GIR_Done, 3190 // Label 309: @5806 3191 GIM_Try, /*On fail goto*//*Label 310*/ 5871, // Rule ID 1963 // 3192 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3193 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3195 // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) 3196 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3197 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3198 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3199 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3200 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3201 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3202 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3203 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3204 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3205 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3206 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3209 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3210 GIR_EraseFromParent, /*InsnID*/0, 3211 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3212 // GIR_Coverage, 1963, 3213 GIR_Done, 3214 // Label 310: @5871 3215 GIM_Try, /*On fail goto*//*Label 311*/ 5936, // Rule ID 1967 // 3216 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3217 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3219 // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) 3220 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3221 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3222 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3223 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3224 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3225 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3226 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3227 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3228 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3229 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3230 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3233 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3234 GIR_EraseFromParent, /*InsnID*/0, 3235 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3236 // GIR_Coverage, 1967, 3237 GIR_Done, 3238 // Label 311: @5936 3239 GIM_Try, /*On fail goto*//*Label 312*/ 6001, // Rule ID 1968 // 3240 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3241 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 3243 // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) 3244 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3245 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3246 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3247 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3248 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3249 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3250 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3251 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3252 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3253 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3254 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3257 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3258 GIR_EraseFromParent, /*InsnID*/0, 3259 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67, 3260 // GIR_Coverage, 1968, 3261 GIR_Done, 3262 // Label 312: @6001 3263 GIM_Reject, 3264 // Label 270: @6002 3265 GIM_Try, /*On fail goto*//*Label 313*/ 6047, 3266 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 3267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 3268 GIM_Try, /*On fail goto*//*Label 314*/ 6029, // Rule ID 1824 // 3269 GIM_CheckFeatures, GIFBS_HasDSP, 3270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 3271 // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] }) 3272 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3273 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7, 3274 // GIR_Coverage, 1824, 3275 GIR_Done, 3276 // Label 314: @6029 3277 GIM_Try, /*On fail goto*//*Label 315*/ 6046, // Rule ID 1828 // 3278 GIM_CheckFeatures, GIFBS_HasDSP, 3279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 3280 // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] }) 3281 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3282 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7, 3283 // GIR_Coverage, 1828, 3284 GIR_Done, 3285 // Label 315: @6046 3286 GIM_Reject, 3287 // Label 313: @6047 3288 GIM_Reject, 3289 // Label 271: @6048 3290 GIM_Try, /*On fail goto*//*Label 316*/ 6069, // Rule ID 1907 // 3291 GIM_CheckFeatures, GIFBS_HasMSA, 3292 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3294 // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }) 3295 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3296 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3297 // GIR_Coverage, 1907, 3298 GIR_Done, 3299 // Label 316: @6069 3300 GIM_Try, /*On fail goto*//*Label 317*/ 6090, // Rule ID 1910 // 3301 GIM_CheckFeatures, GIFBS_HasMSA, 3302 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3304 // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }) 3305 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3306 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3307 // GIR_Coverage, 1910, 3308 GIR_Done, 3309 // Label 317: @6090 3310 GIM_Try, /*On fail goto*//*Label 318*/ 6111, // Rule ID 1923 // 3311 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3312 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3314 // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] }) 3315 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3316 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3317 // GIR_Coverage, 1923, 3318 GIR_Done, 3319 // Label 318: @6111 3320 GIM_Try, /*On fail goto*//*Label 319*/ 6132, // Rule ID 1924 // 3321 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3322 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3324 // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] }) 3325 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3326 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3327 // GIR_Coverage, 1924, 3328 GIR_Done, 3329 // Label 319: @6132 3330 GIM_Try, /*On fail goto*//*Label 320*/ 6153, // Rule ID 1925 // 3331 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3332 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3334 // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }) 3335 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3336 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3337 // GIR_Coverage, 1925, 3338 GIR_Done, 3339 // Label 320: @6153 3340 GIM_Try, /*On fail goto*//*Label 321*/ 6174, // Rule ID 1926 // 3341 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3342 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3344 // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] }) 3345 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3346 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3347 // GIR_Coverage, 1926, 3348 GIR_Done, 3349 // Label 321: @6174 3350 GIM_Try, /*On fail goto*//*Label 322*/ 6195, // Rule ID 1927 // 3351 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3352 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3354 // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }) 3355 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3356 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3357 // GIR_Coverage, 1927, 3358 GIR_Done, 3359 // Label 322: @6195 3360 GIM_Try, /*On fail goto*//*Label 323*/ 6216, // Rule ID 1933 // 3361 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3362 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3364 // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] }) 3365 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3366 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3367 // GIR_Coverage, 1933, 3368 GIR_Done, 3369 // Label 323: @6216 3370 GIM_Try, /*On fail goto*//*Label 324*/ 6237, // Rule ID 1934 // 3371 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3372 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3374 // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] }) 3375 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3376 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3377 // GIR_Coverage, 1934, 3378 GIR_Done, 3379 // Label 324: @6237 3380 GIM_Try, /*On fail goto*//*Label 325*/ 6258, // Rule ID 1935 // 3381 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3382 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3384 // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }) 3385 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3386 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3387 // GIR_Coverage, 1935, 3388 GIR_Done, 3389 // Label 325: @6258 3390 GIM_Try, /*On fail goto*//*Label 326*/ 6279, // Rule ID 1936 // 3391 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3392 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3394 // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] }) 3395 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3396 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3397 // GIR_Coverage, 1936, 3398 GIR_Done, 3399 // Label 326: @6279 3400 GIM_Try, /*On fail goto*//*Label 327*/ 6300, // Rule ID 1937 // 3401 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3402 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3404 // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }) 3405 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3406 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3407 // GIR_Coverage, 1937, 3408 GIR_Done, 3409 // Label 327: @6300 3410 GIM_Try, /*On fail goto*//*Label 328*/ 6365, // Rule ID 1945 // 3411 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3412 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3414 // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }) 3415 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 3416 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, 3417 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3418 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3419 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3420 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3421 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, 3422 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3423 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3424 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3425 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3428 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3429 GIR_EraseFromParent, /*InsnID*/0, 3430 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3431 // GIR_Coverage, 1945, 3432 GIR_Done, 3433 // Label 328: @6365 3434 GIM_Try, /*On fail goto*//*Label 329*/ 6430, // Rule ID 1946 // 3435 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3436 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3438 // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }) 3439 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 3440 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, 3441 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3442 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3443 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3444 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3445 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, 3446 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3447 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3448 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3449 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3452 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3453 GIR_EraseFromParent, /*InsnID*/0, 3454 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3455 // GIR_Coverage, 1946, 3456 GIR_Done, 3457 // Label 329: @6430 3458 GIM_Try, /*On fail goto*//*Label 330*/ 6495, // Rule ID 1950 // 3459 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3460 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3462 // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) 3463 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3464 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3465 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3466 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3467 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3468 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3469 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3470 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3471 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3472 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3473 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3476 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3477 GIR_EraseFromParent, /*InsnID*/0, 3478 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3479 // GIR_Coverage, 1950, 3480 GIR_Done, 3481 // Label 330: @6495 3482 GIM_Try, /*On fail goto*//*Label 331*/ 6560, // Rule ID 1951 // 3483 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3484 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3486 // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) 3487 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3488 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3489 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3490 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3491 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3492 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3493 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3494 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3495 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3496 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3497 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3500 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3501 GIR_EraseFromParent, /*InsnID*/0, 3502 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3503 // GIR_Coverage, 1951, 3504 GIR_Done, 3505 // Label 331: @6560 3506 GIM_Try, /*On fail goto*//*Label 332*/ 6625, // Rule ID 1955 // 3507 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3508 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3510 // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) 3511 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3512 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3513 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3514 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3515 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3516 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3517 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3518 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3519 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3520 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3521 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3524 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3525 GIR_EraseFromParent, /*InsnID*/0, 3526 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3527 // GIR_Coverage, 1955, 3528 GIR_Done, 3529 // Label 332: @6625 3530 GIM_Try, /*On fail goto*//*Label 333*/ 6690, // Rule ID 1956 // 3531 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3532 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3534 // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) 3535 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3536 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3537 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3538 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3539 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3540 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3541 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3542 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3543 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3544 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3545 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3546 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3548 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3549 GIR_EraseFromParent, /*InsnID*/0, 3550 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3551 // GIR_Coverage, 1956, 3552 GIR_Done, 3553 // Label 333: @6690 3554 GIM_Try, /*On fail goto*//*Label 334*/ 6755, // Rule ID 1972 // 3555 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3556 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3558 // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) 3559 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3560 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3561 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3562 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3563 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3564 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3565 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3566 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3567 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3568 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3569 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3571 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3572 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3573 GIR_EraseFromParent, /*InsnID*/0, 3574 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3575 // GIR_Coverage, 1972, 3576 GIR_Done, 3577 // Label 334: @6755 3578 GIM_Try, /*On fail goto*//*Label 335*/ 6820, // Rule ID 1973 // 3579 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3580 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3582 // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) 3583 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3584 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3585 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3586 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3587 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3588 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3589 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3590 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3591 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3592 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3593 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3596 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3597 GIR_EraseFromParent, /*InsnID*/0, 3598 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3599 // GIR_Coverage, 1973, 3600 GIR_Done, 3601 // Label 335: @6820 3602 GIM_Try, /*On fail goto*//*Label 336*/ 6885, // Rule ID 1977 // 3603 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3604 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3606 // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) 3607 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3608 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3609 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3610 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3611 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3612 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3613 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3614 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3615 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3616 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3617 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3618 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3620 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3621 GIR_EraseFromParent, /*InsnID*/0, 3622 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3623 // GIR_Coverage, 1977, 3624 GIR_Done, 3625 // Label 336: @6885 3626 GIM_Try, /*On fail goto*//*Label 337*/ 6950, // Rule ID 1978 // 3627 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3628 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 3630 // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) 3631 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 3632 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 3633 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3634 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3635 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3636 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3637 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 3638 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3639 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3640 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3641 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3644 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3645 GIR_EraseFromParent, /*InsnID*/0, 3646 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69, 3647 // GIR_Coverage, 1978, 3648 GIR_Done, 3649 // Label 337: @6950 3650 GIM_Reject, 3651 // Label 272: @6951 3652 GIM_Try, /*On fail goto*//*Label 338*/ 6972, // Rule ID 1906 // 3653 GIM_CheckFeatures, GIFBS_HasMSA, 3654 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3656 // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }) 3657 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3658 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3659 // GIR_Coverage, 1906, 3660 GIR_Done, 3661 // Label 338: @6972 3662 GIM_Try, /*On fail goto*//*Label 339*/ 6993, // Rule ID 1909 // 3663 GIM_CheckFeatures, GIFBS_HasMSA, 3664 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3666 // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }) 3667 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3668 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3669 // GIR_Coverage, 1909, 3670 GIR_Done, 3671 // Label 339: @6993 3672 GIM_Try, /*On fail goto*//*Label 340*/ 7014, // Rule ID 1918 // 3673 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3674 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3676 // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] }) 3677 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3678 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3679 // GIR_Coverage, 1918, 3680 GIR_Done, 3681 // Label 340: @7014 3682 GIM_Try, /*On fail goto*//*Label 341*/ 7035, // Rule ID 1919 // 3683 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3684 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3686 // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }) 3687 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3688 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3689 // GIR_Coverage, 1919, 3690 GIR_Done, 3691 // Label 341: @7035 3692 GIM_Try, /*On fail goto*//*Label 342*/ 7056, // Rule ID 1920 // 3693 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3694 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3696 // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }) 3697 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3698 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3699 // GIR_Coverage, 1920, 3700 GIR_Done, 3701 // Label 342: @7056 3702 GIM_Try, /*On fail goto*//*Label 343*/ 7077, // Rule ID 1921 // 3703 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3704 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3706 // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }) 3707 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3708 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3709 // GIR_Coverage, 1921, 3710 GIR_Done, 3711 // Label 343: @7077 3712 GIM_Try, /*On fail goto*//*Label 344*/ 7098, // Rule ID 1922 // 3713 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3714 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3716 // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }) 3717 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3718 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3719 // GIR_Coverage, 1922, 3720 GIR_Done, 3721 // Label 344: @7098 3722 GIM_Try, /*On fail goto*//*Label 345*/ 7163, // Rule ID 1943 // 3723 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3724 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3726 // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) 3727 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 3728 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, 3729 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3730 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3731 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3732 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3733 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, 3734 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3735 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3736 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3737 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3738 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3740 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3741 GIR_EraseFromParent, /*InsnID*/0, 3742 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3743 // GIR_Coverage, 1943, 3744 GIR_Done, 3745 // Label 345: @7163 3746 GIM_Try, /*On fail goto*//*Label 346*/ 7228, // Rule ID 1944 // 3747 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3748 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3750 // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) 3751 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 3752 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, 3753 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3754 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3755 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3756 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3757 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, 3758 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3759 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3760 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3761 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3764 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3765 GIR_EraseFromParent, /*InsnID*/0, 3766 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3767 // GIR_Coverage, 1944, 3768 GIR_Done, 3769 // Label 346: @7228 3770 GIM_Try, /*On fail goto*//*Label 347*/ 7293, // Rule ID 1960 // 3771 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3772 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3774 // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) 3775 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3776 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3777 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3778 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3779 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3780 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3781 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3782 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3783 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3784 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3785 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3786 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3788 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3789 GIR_EraseFromParent, /*InsnID*/0, 3790 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3791 // GIR_Coverage, 1960, 3792 GIR_Done, 3793 // Label 347: @7293 3794 GIM_Try, /*On fail goto*//*Label 348*/ 7358, // Rule ID 1961 // 3795 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3796 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3798 // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) 3799 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3800 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3801 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3802 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3803 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3804 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3805 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3806 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3807 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3808 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3809 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3812 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3813 GIR_EraseFromParent, /*InsnID*/0, 3814 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3815 // GIR_Coverage, 1961, 3816 GIR_Done, 3817 // Label 348: @7358 3818 GIM_Try, /*On fail goto*//*Label 349*/ 7423, // Rule ID 1965 // 3819 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3820 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3822 // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) 3823 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3824 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3825 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3826 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3827 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3828 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3829 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3830 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3831 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3832 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3833 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3834 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3836 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3837 GIR_EraseFromParent, /*InsnID*/0, 3838 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3839 // GIR_Coverage, 1965, 3840 GIR_Done, 3841 // Label 349: @7423 3842 GIM_Try, /*On fail goto*//*Label 350*/ 7488, // Rule ID 1966 // 3843 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3844 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3846 // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) 3847 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3848 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3849 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3850 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3851 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3852 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3853 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3854 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3855 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3856 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 3857 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3860 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3861 GIR_EraseFromParent, /*InsnID*/0, 3862 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3863 // GIR_Coverage, 1966, 3864 GIR_Done, 3865 // Label 350: @7488 3866 GIM_Try, /*On fail goto*//*Label 351*/ 7553, // Rule ID 1970 // 3867 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3868 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3870 // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) 3871 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3872 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3873 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3874 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3875 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3876 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3877 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3878 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3879 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3880 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3881 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3884 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3885 GIR_EraseFromParent, /*InsnID*/0, 3886 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3887 // GIR_Coverage, 1970, 3888 GIR_Done, 3889 // Label 351: @7553 3890 GIM_Try, /*On fail goto*//*Label 352*/ 7618, // Rule ID 1971 // 3891 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3892 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3894 // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) 3895 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3896 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3897 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3898 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3899 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3900 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3901 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3902 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3903 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3904 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3905 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3908 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3909 GIR_EraseFromParent, /*InsnID*/0, 3910 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3911 // GIR_Coverage, 1971, 3912 GIR_Done, 3913 // Label 352: @7618 3914 GIM_Try, /*On fail goto*//*Label 353*/ 7683, // Rule ID 1975 // 3915 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3916 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3918 // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) 3919 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3920 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3921 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3922 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3923 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3924 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3925 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3926 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3927 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3928 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3929 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3932 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3933 GIR_EraseFromParent, /*InsnID*/0, 3934 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3935 // GIR_Coverage, 1975, 3936 GIR_Done, 3937 // Label 353: @7683 3938 GIM_Try, /*On fail goto*//*Label 354*/ 7748, // Rule ID 1976 // 3939 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 3940 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 3942 // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) 3943 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, 3944 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 3945 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3946 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3947 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 3948 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3949 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, 3950 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3951 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3952 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 3953 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3956 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3957 GIR_EraseFromParent, /*InsnID*/0, 3958 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68, 3959 // GIR_Coverage, 1976, 3960 GIR_Done, 3961 // Label 354: @7748 3962 GIM_Reject, 3963 // Label 273: @7749 3964 GIM_Try, /*On fail goto*//*Label 355*/ 7770, // Rule ID 1912 // 3965 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3966 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 3968 // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }) 3969 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3970 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 3971 // GIR_Coverage, 1912, 3972 GIR_Done, 3973 // Label 355: @7770 3974 GIM_Try, /*On fail goto*//*Label 356*/ 7791, // Rule ID 1913 // 3975 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3976 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 3978 // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }) 3979 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3980 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 3981 // GIR_Coverage, 1913, 3982 GIR_Done, 3983 // Label 356: @7791 3984 GIM_Try, /*On fail goto*//*Label 357*/ 7812, // Rule ID 1914 // 3985 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3986 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 3988 // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }) 3989 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 3990 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 3991 // GIR_Coverage, 1914, 3992 GIR_Done, 3993 // Label 357: @7812 3994 GIM_Try, /*On fail goto*//*Label 358*/ 7833, // Rule ID 1915 // 3995 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 3996 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 3998 // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }) 3999 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 4000 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 4001 // GIR_Coverage, 1915, 4002 GIR_Done, 4003 // Label 358: @7833 4004 GIM_Try, /*On fail goto*//*Label 359*/ 7854, // Rule ID 1916 // 4005 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 4006 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 4007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 4008 // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }) 4009 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 4010 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 4011 // GIR_Coverage, 1916, 4012 GIR_Done, 4013 // Label 359: @7854 4014 GIM_Try, /*On fail goto*//*Label 360*/ 7875, // Rule ID 1917 // 4015 GIM_CheckFeatures, GIFBS_HasMSA_IsLE, 4016 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 4017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 4018 // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }) 4019 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 4020 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 4021 // GIR_Coverage, 1917, 4022 GIR_Done, 4023 // Label 360: @7875 4024 GIM_Try, /*On fail goto*//*Label 361*/ 7940, // Rule ID 1949 // 4025 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 4026 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 4027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 4028 // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) 4029 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 4030 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, 4031 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4032 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4033 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 4034 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4035 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, 4036 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4037 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4038 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 4039 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4040 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4042 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4043 GIR_EraseFromParent, /*InsnID*/0, 4044 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 4045 // GIR_Coverage, 1949, 4046 GIR_Done, 4047 // Label 361: @7940 4048 GIM_Try, /*On fail goto*//*Label 362*/ 8005, // Rule ID 1954 // 4049 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 4050 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 4051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 4052 // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) 4053 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 4054 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, 4055 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4056 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4057 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 4058 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4059 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, 4060 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4061 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4062 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 4063 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4066 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4067 GIR_EraseFromParent, /*InsnID*/0, 4068 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 4069 // GIR_Coverage, 1954, 4070 GIR_Done, 4071 // Label 362: @8005 4072 GIM_Try, /*On fail goto*//*Label 363*/ 8070, // Rule ID 1959 // 4073 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 4074 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 4075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 4076 // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] }) 4077 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 4078 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, 4079 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4080 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4081 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 4082 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4083 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, 4084 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4085 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4086 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 4087 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4088 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4090 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4091 GIR_EraseFromParent, /*InsnID*/0, 4092 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 4093 // GIR_Coverage, 1959, 4094 GIR_Done, 4095 // Label 363: @8070 4096 GIM_Try, /*On fail goto*//*Label 364*/ 8135, // Rule ID 1964 // 4097 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 4098 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 4099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 4100 // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] }) 4101 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 4102 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, 4103 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4104 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4105 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 4106 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4107 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, 4108 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4109 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4110 GIR_AddImm, /*InsnID*/1, /*Imm*/27, 4111 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4114 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4115 GIR_EraseFromParent, /*InsnID*/0, 4116 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 4117 // GIR_Coverage, 1964, 4118 GIR_Done, 4119 // Label 364: @8135 4120 GIM_Try, /*On fail goto*//*Label 365*/ 8235, // Rule ID 1969 // 4121 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 4122 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 4123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 4124 // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) 4125 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 4126 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 4127 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, 4128 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, 4129 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, 4130 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 4131 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 4132 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 4133 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, 4134 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4135 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, 4136 GIR_AddImm, /*InsnID*/3, /*Imm*/27, 4137 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4138 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4139 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4140 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 4141 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4142 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 4143 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4144 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4145 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 4146 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4149 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4150 GIR_EraseFromParent, /*InsnID*/0, 4151 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 4152 // GIR_Coverage, 1969, 4153 GIR_Done, 4154 // Label 365: @8235 4155 GIM_Try, /*On fail goto*//*Label 366*/ 8335, // Rule ID 1974 // 4156 GIM_CheckFeatures, GIFBS_HasMSA_IsBE, 4157 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 4158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 4159 // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) 4160 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, 4161 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, 4162 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, 4163 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, 4164 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, 4165 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 4166 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 4167 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 4168 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, 4169 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4170 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, 4171 GIR_AddImm, /*InsnID*/3, /*Imm*/27, 4172 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4173 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4174 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4175 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 4176 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4177 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, 4178 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4179 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4180 GIR_AddImm, /*InsnID*/1, /*Imm*/177, 4181 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4184 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4185 GIR_EraseFromParent, /*InsnID*/0, 4186 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66, 4187 // GIR_Coverage, 1974, 4188 GIR_Done, 4189 // Label 366: @8335 4190 GIM_Reject, 4191 // Label 274: @8336 4192 GIM_Reject, 4193 // Label 11: @8337 4194 GIM_Try, /*On fail goto*//*Label 367*/ 8402, // Rule ID 1897 // 4195 GIM_CheckFeatures, GIFBS_HasDSP, 4196 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4197 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 4198 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 4199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 4200 // MIs[0] Operand 1 4201 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4202 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4203 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4204 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4205 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4206 GIM_CheckIsSafeToFold, /*InsnID*/1, 4207 // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index) 4208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX, 4209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base 4211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index 4212 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 4213 GIR_EraseFromParent, /*InsnID*/0, 4214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4215 // GIR_Coverage, 1897, 4216 GIR_Done, 4217 // Label 367: @8402 4218 GIM_Reject, 4219 // Label 12: @8403 4220 GIM_Try, /*On fail goto*//*Label 368*/ 8468, // Rule ID 1896 // 4221 GIM_CheckFeatures, GIFBS_HasDSP, 4222 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4223 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 4224 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 4225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 4226 // MIs[0] Operand 1 4227 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4228 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4229 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4230 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4231 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4232 GIM_CheckIsSafeToFold, /*InsnID*/1, 4233 // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index) 4234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX, 4235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base 4237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index 4238 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 4239 GIR_EraseFromParent, /*InsnID*/0, 4240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4241 // GIR_Coverage, 1896, 4242 GIR_Done, 4243 // Label 368: @8468 4244 GIM_Reject, 4245 // Label 13: @8469 4246 GIM_Try, /*On fail goto*//*Label 369*/ 8534, // Rule ID 1895 // 4247 GIM_CheckFeatures, GIFBS_HasDSP, 4248 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4249 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 4250 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 4251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 4252 // MIs[0] Operand 1 4253 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4254 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4255 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4256 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4257 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4258 GIM_CheckIsSafeToFold, /*InsnID*/1, 4259 // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index) 4260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX, 4261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base 4263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index 4264 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 4265 GIR_EraseFromParent, /*InsnID*/0, 4266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4267 // GIR_Coverage, 1895, 4268 GIR_Done, 4269 // Label 369: @8534 4270 GIM_Reject, 4271 // Label 14: @8535 4272 GIM_Try, /*On fail goto*//*Label 370*/ 10729, 4273 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 4274 GIM_Try, /*On fail goto*//*Label 371*/ 8587, // Rule ID 400 // 4275 GIM_CheckFeatures, GIFBS_HasDSP, 4276 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, 4277 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 4278 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4280 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4281 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4282 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8, 4283 // MIs[1] Operand 1 4284 // No operand predicates 4285 GIM_CheckIsSafeToFold, /*InsnID*/1, 4286 // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm) 4287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB, 4288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4289 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 4290 GIR_EraseFromParent, /*InsnID*/0, 4291 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4292 // GIR_Coverage, 400, 4293 GIR_Done, 4294 // Label 371: @8587 4295 GIM_Try, /*On fail goto*//*Label 372*/ 8634, // Rule ID 401 // 4296 GIM_CheckFeatures, GIFBS_HasDSP, 4297 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, 4298 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4299 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4301 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4302 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4303 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10, 4304 // MIs[1] Operand 1 4305 // No operand predicates 4306 GIM_CheckIsSafeToFold, /*InsnID*/1, 4307 // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm) 4308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH, 4309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4310 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 4311 GIR_EraseFromParent, /*InsnID*/0, 4312 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4313 // GIR_Coverage, 401, 4314 GIR_Done, 4315 // Label 372: @8634 4316 GIM_Try, /*On fail goto*//*Label 373*/ 8681, // Rule ID 1245 // 4317 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 4318 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, 4319 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4320 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4322 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4323 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4324 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10, 4325 // MIs[1] Operand 1 4326 // No operand predicates 4327 GIM_CheckIsSafeToFold, /*InsnID*/1, 4328 // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm) 4329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM, 4330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4331 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 4332 GIR_EraseFromParent, /*InsnID*/0, 4333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4334 // GIR_Coverage, 1245, 4335 GIR_Done, 4336 // Label 373: @8681 4337 GIM_Try, /*On fail goto*//*Label 374*/ 8728, // Rule ID 1246 // 4338 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 4339 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, 4340 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 4341 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4343 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4344 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4345 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8, 4346 // MIs[1] Operand 1 4347 // No operand predicates 4348 GIM_CheckIsSafeToFold, /*InsnID*/1, 4349 // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm) 4350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM, 4351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 4352 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 4353 GIR_EraseFromParent, /*InsnID*/0, 4354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4355 // GIR_Coverage, 1246, 4356 GIR_Done, 4357 // Label 374: @8728 4358 GIM_Try, /*On fail goto*//*Label 375*/ 8768, // Rule ID 334 // 4359 GIM_CheckFeatures, GIFBS_HasDSP, 4360 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb, 4361 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4362 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 4364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4365 // (intrinsic_wo_chain:{ *:[i32] } 3468:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs) 4366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB, 4367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 4369 GIR_EraseFromParent, /*InsnID*/0, 4370 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4371 // GIR_Coverage, 334, 4372 GIR_Done, 4373 // Label 375: @8768 4374 GIM_Try, /*On fail goto*//*Label 376*/ 8808, // Rule ID 341 // 4375 GIM_CheckFeatures, GIFBS_HasDSP, 4376 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl, 4377 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4378 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 4379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 4380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4381 // (intrinsic_wo_chain:{ *:[i32] } 3450:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt) 4382 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL, 4383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4385 GIR_EraseFromParent, /*InsnID*/0, 4386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4387 // GIR_Coverage, 341, 4388 GIR_Done, 4389 // Label 376: @8808 4390 GIM_Try, /*On fail goto*//*Label 377*/ 8848, // Rule ID 342 // 4391 GIM_CheckFeatures, GIFBS_HasDSP, 4392 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr, 4393 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4394 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 4395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 4396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4397 // (intrinsic_wo_chain:{ *:[i32] } 3451:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt) 4398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR, 4399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4401 GIR_EraseFromParent, /*InsnID*/0, 4402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4403 // GIR_Coverage, 342, 4404 GIR_Done, 4405 // Label 377: @8848 4406 GIM_Try, /*On fail goto*//*Label 378*/ 8888, // Rule ID 343 // 4407 GIM_CheckFeatures, GIFBS_HasDSP, 4408 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl, 4409 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4410 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4413 // (intrinsic_wo_chain:{ *:[v2i16] } 3452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) 4414 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL, 4415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4417 GIR_EraseFromParent, /*InsnID*/0, 4418 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4419 // GIR_Coverage, 343, 4420 GIR_Done, 4421 // Label 378: @8888 4422 GIM_Try, /*On fail goto*//*Label 379*/ 8928, // Rule ID 344 // 4423 GIM_CheckFeatures, GIFBS_HasDSP, 4424 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr, 4425 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4426 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4429 // (intrinsic_wo_chain:{ *:[v2i16] } 3454:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) 4430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR, 4431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4433 GIR_EraseFromParent, /*InsnID*/0, 4434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4435 // GIR_Coverage, 344, 4436 GIR_Done, 4437 // Label 379: @8928 4438 GIM_Try, /*On fail goto*//*Label 380*/ 8968, // Rule ID 345 // 4439 GIM_CheckFeatures, GIFBS_HasDSP, 4440 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla, 4441 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4442 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4445 // (intrinsic_wo_chain:{ *:[v2i16] } 3453:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) 4446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA, 4447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4449 GIR_EraseFromParent, /*InsnID*/0, 4450 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4451 // GIR_Coverage, 345, 4452 GIR_Done, 4453 // Label 380: @8968 4454 GIM_Try, /*On fail goto*//*Label 381*/ 9008, // Rule ID 346 // 4455 GIM_CheckFeatures, GIFBS_HasDSP, 4456 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra, 4457 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4458 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4461 // (intrinsic_wo_chain:{ *:[v2i16] } 3455:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) 4462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA, 4463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4465 GIR_EraseFromParent, /*InsnID*/0, 4466 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4467 // GIR_Coverage, 346, 4468 GIR_Done, 4469 // Label 381: @9008 4470 GIM_Try, /*On fail goto*//*Label 382*/ 9048, // Rule ID 347 // 4471 GIM_CheckFeatures, GIFBS_HasDSP, 4472 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl, 4473 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4474 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4477 // (intrinsic_wo_chain:{ *:[v2i16] } 3456:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) 4478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL, 4479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4481 GIR_EraseFromParent, /*InsnID*/0, 4482 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4483 // GIR_Coverage, 347, 4484 GIR_Done, 4485 // Label 382: @9048 4486 GIM_Try, /*On fail goto*//*Label 383*/ 9088, // Rule ID 348 // 4487 GIM_CheckFeatures, GIFBS_HasDSP, 4488 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr, 4489 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4490 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4493 // (intrinsic_wo_chain:{ *:[v2i16] } 3458:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) 4494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR, 4495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4497 GIR_EraseFromParent, /*InsnID*/0, 4498 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4499 // GIR_Coverage, 348, 4500 GIR_Done, 4501 // Label 383: @9088 4502 GIM_Try, /*On fail goto*//*Label 384*/ 9128, // Rule ID 349 // 4503 GIM_CheckFeatures, GIFBS_HasDSP, 4504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla, 4505 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4506 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4509 // (intrinsic_wo_chain:{ *:[v2i16] } 3457:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) 4510 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA, 4511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4513 GIR_EraseFromParent, /*InsnID*/0, 4514 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4515 // GIR_Coverage, 349, 4516 GIR_Done, 4517 // Label 384: @9128 4518 GIM_Try, /*On fail goto*//*Label 385*/ 9168, // Rule ID 350 // 4519 GIM_CheckFeatures, GIFBS_HasDSP, 4520 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra, 4521 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4522 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4525 // (intrinsic_wo_chain:{ *:[v2i16] } 3459:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) 4526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA, 4527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4529 GIR_EraseFromParent, /*InsnID*/0, 4530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4531 // GIR_Coverage, 350, 4532 GIR_Done, 4533 // Label 385: @9168 4534 GIM_Try, /*On fail goto*//*Label 386*/ 9208, // Rule ID 398 // 4535 GIM_CheckFeatures, GIFBS_HasDSP, 4536 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev, 4537 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4538 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 4540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 4541 // (intrinsic_wo_chain:{ *:[i32] } 3026:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt) 4542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV, 4543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4545 GIR_EraseFromParent, /*InsnID*/0, 4546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4547 // GIR_Coverage, 398, 4548 GIR_Done, 4549 // Label 386: @9208 4550 GIM_Try, /*On fail goto*//*Label 387*/ 9248, // Rule ID 402 // 4551 GIM_CheckFeatures, GIFBS_HasDSP, 4552 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, 4553 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 4554 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 4557 // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt) 4558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB, 4559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4561 GIR_EraseFromParent, /*InsnID*/0, 4562 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4563 // GIR_Coverage, 402, 4564 GIR_Done, 4565 // Label 387: @9248 4566 GIM_Try, /*On fail goto*//*Label 388*/ 9288, // Rule ID 403 // 4567 GIM_CheckFeatures, GIFBS_HasDSP, 4568 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, 4569 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4570 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 4573 // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt) 4574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH, 4575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 4576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 4577 GIR_EraseFromParent, /*InsnID*/0, 4578 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4579 // GIR_Coverage, 403, 4580 GIR_Done, 4581 // Label 388: @9288 4582 GIM_Try, /*On fail goto*//*Label 389*/ 9328, // Rule ID 648 // 4583 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4584 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w, 4585 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4586 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4589 // (intrinsic_wo_chain:{ *:[v4i32] } 3178:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) 4590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W, 4591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4593 GIR_EraseFromParent, /*InsnID*/0, 4594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4595 // GIR_Coverage, 648, 4596 GIR_Done, 4597 // Label 389: @9328 4598 GIM_Try, /*On fail goto*//*Label 390*/ 9368, // Rule ID 649 // 4599 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4600 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d, 4601 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4602 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 4605 // (intrinsic_wo_chain:{ *:[v2i64] } 3177:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) 4606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D, 4607 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4609 GIR_EraseFromParent, /*InsnID*/0, 4610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4611 // GIR_Coverage, 649, 4612 GIR_Done, 4613 // Label 390: @9368 4614 GIM_Try, /*On fail goto*//*Label 391*/ 9408, // Rule ID 672 // 4615 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4616 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w, 4617 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4618 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 4621 // (intrinsic_wo_chain:{ *:[v4f32] } 3204:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws) 4622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W, 4623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4625 GIR_EraseFromParent, /*InsnID*/0, 4626 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4627 // GIR_Coverage, 672, 4628 GIR_Done, 4629 // Label 391: @9408 4630 GIM_Try, /*On fail goto*//*Label 392*/ 9448, // Rule ID 673 // 4631 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4632 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d, 4633 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4634 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4637 // (intrinsic_wo_chain:{ *:[v2f64] } 3203:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws) 4638 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D, 4639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4641 GIR_EraseFromParent, /*InsnID*/0, 4642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4643 // GIR_Coverage, 673, 4644 GIR_Done, 4645 // Label 392: @9448 4646 GIM_Try, /*On fail goto*//*Label 393*/ 9488, // Rule ID 674 // 4647 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4648 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w, 4649 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4650 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 4653 // (intrinsic_wo_chain:{ *:[v4f32] } 3206:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws) 4654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W, 4655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4657 GIR_EraseFromParent, /*InsnID*/0, 4658 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4659 // GIR_Coverage, 674, 4660 GIR_Done, 4661 // Label 393: @9488 4662 GIM_Try, /*On fail goto*//*Label 394*/ 9528, // Rule ID 675 // 4663 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4664 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d, 4665 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4666 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4669 // (intrinsic_wo_chain:{ *:[v2f64] } 3205:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws) 4670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D, 4671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4673 GIR_EraseFromParent, /*InsnID*/0, 4674 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4675 // GIR_Coverage, 675, 4676 GIR_Done, 4677 // Label 394: @9528 4678 GIM_Try, /*On fail goto*//*Label 395*/ 9568, // Rule ID 680 // 4679 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4680 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w, 4681 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4682 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 4685 // (intrinsic_wo_chain:{ *:[v4f32] } 3212:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws) 4686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W, 4687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4689 GIR_EraseFromParent, /*InsnID*/0, 4690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4691 // GIR_Coverage, 680, 4692 GIR_Done, 4693 // Label 395: @9568 4694 GIM_Try, /*On fail goto*//*Label 396*/ 9608, // Rule ID 681 // 4695 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4696 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_d, 4697 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4698 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4701 // (intrinsic_wo_chain:{ *:[v2f64] } 3211:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws) 4702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D, 4703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4705 GIR_EraseFromParent, /*InsnID*/0, 4706 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4707 // GIR_Coverage, 681, 4708 GIR_Done, 4709 // Label 396: @9608 4710 GIM_Try, /*On fail goto*//*Label 397*/ 9648, // Rule ID 682 // 4711 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4712 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_w, 4713 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4714 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 4717 // (intrinsic_wo_chain:{ *:[v4f32] } 3214:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws) 4718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_W, 4719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4721 GIR_EraseFromParent, /*InsnID*/0, 4722 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4723 // GIR_Coverage, 682, 4724 GIR_Done, 4725 // Label 397: @9648 4726 GIM_Try, /*On fail goto*//*Label 398*/ 9688, // Rule ID 683 // 4727 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4728 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_d, 4729 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4730 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4733 // (intrinsic_wo_chain:{ *:[v2f64] } 3213:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws) 4734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_D, 4735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4737 GIR_EraseFromParent, /*InsnID*/0, 4738 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4739 // GIR_Coverage, 683, 4740 GIR_Done, 4741 // Label 398: @9688 4742 GIM_Try, /*On fail goto*//*Label 399*/ 9728, // Rule ID 708 // 4743 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4744 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_w, 4745 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4746 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4749 // (intrinsic_wo_chain:{ *:[v4f32] } 3236:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) 4750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_W, 4751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4753 GIR_EraseFromParent, /*InsnID*/0, 4754 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4755 // GIR_Coverage, 708, 4756 GIR_Done, 4757 // Label 399: @9728 4758 GIM_Try, /*On fail goto*//*Label 400*/ 9768, // Rule ID 709 // 4759 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4760 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_d, 4761 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4762 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 4765 // (intrinsic_wo_chain:{ *:[v2f64] } 3235:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) 4766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_D, 4767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4769 GIR_EraseFromParent, /*InsnID*/0, 4770 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4771 // GIR_Coverage, 709, 4772 GIR_Done, 4773 // Label 400: @9768 4774 GIM_Try, /*On fail goto*//*Label 401*/ 9808, // Rule ID 710 // 4775 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4776 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_w, 4777 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4778 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4781 // (intrinsic_wo_chain:{ *:[v4f32] } 3240:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) 4782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_W, 4783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4785 GIR_EraseFromParent, /*InsnID*/0, 4786 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4787 // GIR_Coverage, 710, 4788 GIR_Done, 4789 // Label 401: @9808 4790 GIM_Try, /*On fail goto*//*Label 402*/ 9848, // Rule ID 711 // 4791 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4792 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_d, 4793 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4794 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 4797 // (intrinsic_wo_chain:{ *:[v2f64] } 3239:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) 4798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_D, 4799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4801 GIR_EraseFromParent, /*InsnID*/0, 4802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4803 // GIR_Coverage, 711, 4804 GIR_Done, 4805 // Label 402: @9848 4806 GIM_Try, /*On fail goto*//*Label 403*/ 9888, // Rule ID 738 // 4807 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4808 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_w, 4809 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4810 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4813 // (intrinsic_wo_chain:{ *:[v4i32] } 3268:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) 4814 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_W, 4815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4817 GIR_EraseFromParent, /*InsnID*/0, 4818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4819 // GIR_Coverage, 738, 4820 GIR_Done, 4821 // Label 403: @9888 4822 GIM_Try, /*On fail goto*//*Label 404*/ 9928, // Rule ID 739 // 4823 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4824 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_d, 4825 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4826 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 4829 // (intrinsic_wo_chain:{ *:[v2i64] } 3267:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) 4830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_D, 4831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4833 GIR_EraseFromParent, /*InsnID*/0, 4834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4835 // GIR_Coverage, 739, 4836 GIR_Done, 4837 // Label 404: @9928 4838 GIM_Try, /*On fail goto*//*Label 405*/ 9968, // Rule ID 740 // 4839 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_w, 4841 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4842 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4845 // (intrinsic_wo_chain:{ *:[v4i32] } 3270:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) 4846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_W, 4847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4849 GIR_EraseFromParent, /*InsnID*/0, 4850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4851 // GIR_Coverage, 740, 4852 GIR_Done, 4853 // Label 405: @9968 4854 GIM_Try, /*On fail goto*//*Label 406*/ 10008, // Rule ID 741 // 4855 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4856 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_d, 4857 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4858 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 4861 // (intrinsic_wo_chain:{ *:[v2i64] } 3269:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) 4862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_D, 4863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4865 GIR_EraseFromParent, /*InsnID*/0, 4866 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4867 // GIR_Coverage, 741, 4868 GIR_Done, 4869 // Label 406: @10008 4870 GIM_Try, /*On fail goto*//*Label 407*/ 10048, // Rule ID 876 // 4871 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4872 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_b, 4873 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 4874 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 4876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 4877 // (intrinsic_wo_chain:{ *:[v16i8] } 3423:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) 4878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_B, 4879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4881 GIR_EraseFromParent, /*InsnID*/0, 4882 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4883 // GIR_Coverage, 876, 4884 GIR_Done, 4885 // Label 407: @10048 4886 GIM_Try, /*On fail goto*//*Label 408*/ 10088, // Rule ID 877 // 4887 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4888 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_h, 4889 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 4890 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 4892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 4893 // (intrinsic_wo_chain:{ *:[v8i16] } 3425:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) 4894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_H, 4895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4897 GIR_EraseFromParent, /*InsnID*/0, 4898 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4899 // GIR_Coverage, 877, 4900 GIR_Done, 4901 // Label 408: @10088 4902 GIM_Try, /*On fail goto*//*Label 409*/ 10128, // Rule ID 878 // 4903 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4904 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_w, 4905 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 4906 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 4908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 4909 // (intrinsic_wo_chain:{ *:[v4i32] } 3426:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) 4910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_W, 4911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4913 GIR_EraseFromParent, /*InsnID*/0, 4914 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4915 // GIR_Coverage, 878, 4916 GIR_Done, 4917 // Label 409: @10128 4918 GIM_Try, /*On fail goto*//*Label 410*/ 10168, // Rule ID 879 // 4919 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 4920 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_d, 4921 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 4922 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 4924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 4925 // (intrinsic_wo_chain:{ *:[v2i64] } 3424:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) 4926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_D, 4927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 4928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 4929 GIR_EraseFromParent, /*InsnID*/0, 4930 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4931 // GIR_Coverage, 879, 4932 GIR_Done, 4933 // Label 410: @10168 4934 GIM_Try, /*On fail goto*//*Label 411*/ 10208, // Rule ID 1208 // 4935 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 4936 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl, 4937 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4938 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 4939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 4940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4941 // (intrinsic_wo_chain:{ *:[i32] } 3450:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs) 4942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL_MM, 4943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 4944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 4945 GIR_EraseFromParent, /*InsnID*/0, 4946 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4947 // GIR_Coverage, 1208, 4948 GIR_Done, 4949 // Label 411: @10208 4950 GIM_Try, /*On fail goto*//*Label 412*/ 10248, // Rule ID 1209 // 4951 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 4952 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr, 4953 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 4954 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 4955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 4956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4957 // (intrinsic_wo_chain:{ *:[i32] } 3451:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs) 4958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR_MM, 4959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 4960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 4961 GIR_EraseFromParent, /*InsnID*/0, 4962 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4963 // GIR_Coverage, 1209, 4964 GIR_Done, 4965 // Label 412: @10248 4966 GIM_Try, /*On fail goto*//*Label 413*/ 10288, // Rule ID 1210 // 4967 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 4968 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl, 4969 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4970 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4973 // (intrinsic_wo_chain:{ *:[v2i16] } 3452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) 4974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL_MM, 4975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 4976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 4977 GIR_EraseFromParent, /*InsnID*/0, 4978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4979 // GIR_Coverage, 1210, 4980 GIR_Done, 4981 // Label 413: @10288 4982 GIM_Try, /*On fail goto*//*Label 414*/ 10328, // Rule ID 1211 // 4983 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 4984 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla, 4985 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 4986 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 4987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 4988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 4989 // (intrinsic_wo_chain:{ *:[v2i16] } 3453:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) 4990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA_MM, 4991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 4992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 4993 GIR_EraseFromParent, /*InsnID*/0, 4994 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4995 // GIR_Coverage, 1211, 4996 GIR_Done, 4997 // Label 414: @10328 4998 GIM_Try, /*On fail goto*//*Label 415*/ 10368, // Rule ID 1212 // 4999 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr, 5001 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5002 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5005 // (intrinsic_wo_chain:{ *:[v2i16] } 3454:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) 5006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR_MM, 5007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5009 GIR_EraseFromParent, /*InsnID*/0, 5010 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5011 // GIR_Coverage, 1212, 5012 GIR_Done, 5013 // Label 415: @10368 5014 GIM_Try, /*On fail goto*//*Label 416*/ 10408, // Rule ID 1213 // 5015 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5016 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra, 5017 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5018 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5021 // (intrinsic_wo_chain:{ *:[v2i16] } 3455:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) 5022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA_MM, 5023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5025 GIR_EraseFromParent, /*InsnID*/0, 5026 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5027 // GIR_Coverage, 1213, 5028 GIR_Done, 5029 // Label 416: @10408 5030 GIM_Try, /*On fail goto*//*Label 417*/ 10448, // Rule ID 1214 // 5031 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5032 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl, 5033 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5034 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5037 // (intrinsic_wo_chain:{ *:[v2i16] } 3456:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) 5038 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL_MM, 5039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5041 GIR_EraseFromParent, /*InsnID*/0, 5042 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5043 // GIR_Coverage, 1214, 5044 GIR_Done, 5045 // Label 417: @10448 5046 GIM_Try, /*On fail goto*//*Label 418*/ 10488, // Rule ID 1215 // 5047 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5048 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla, 5049 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5050 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5053 // (intrinsic_wo_chain:{ *:[v2i16] } 3457:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) 5054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA_MM, 5055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5057 GIR_EraseFromParent, /*InsnID*/0, 5058 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5059 // GIR_Coverage, 1215, 5060 GIR_Done, 5061 // Label 418: @10488 5062 GIM_Try, /*On fail goto*//*Label 419*/ 10528, // Rule ID 1216 // 5063 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5064 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr, 5065 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5066 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5069 // (intrinsic_wo_chain:{ *:[v2i16] } 3458:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) 5070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR_MM, 5071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5073 GIR_EraseFromParent, /*InsnID*/0, 5074 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5075 // GIR_Coverage, 1216, 5076 GIR_Done, 5077 // Label 419: @10528 5078 GIM_Try, /*On fail goto*//*Label 420*/ 10568, // Rule ID 1217 // 5079 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5080 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra, 5081 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5082 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5085 // (intrinsic_wo_chain:{ *:[v2i16] } 3459:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) 5086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA_MM, 5087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5089 GIR_EraseFromParent, /*InsnID*/0, 5090 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5091 // GIR_Coverage, 1217, 5092 GIR_Done, 5093 // Label 420: @10568 5094 GIM_Try, /*On fail goto*//*Label 421*/ 10608, // Rule ID 1243 // 5095 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5096 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb, 5097 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 5098 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 5100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5101 // (intrinsic_wo_chain:{ *:[i32] } 3468:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs) 5102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB_MM, 5103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5105 GIR_EraseFromParent, /*InsnID*/0, 5106 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5107 // GIR_Coverage, 1243, 5108 GIR_Done, 5109 // Label 421: @10608 5110 GIM_Try, /*On fail goto*//*Label 422*/ 10648, // Rule ID 1247 // 5111 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5112 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, 5113 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5114 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 5117 // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs) 5118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH_MM, 5119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5121 GIR_EraseFromParent, /*InsnID*/0, 5122 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5123 // GIR_Coverage, 1247, 5124 GIR_Done, 5125 // Label 422: @10648 5126 GIM_Try, /*On fail goto*//*Label 423*/ 10688, // Rule ID 1248 // 5127 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5128 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, 5129 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 5130 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 5133 // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs) 5134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB_MM, 5135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5137 GIR_EraseFromParent, /*InsnID*/0, 5138 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5139 // GIR_Coverage, 1248, 5140 GIR_Done, 5141 // Label 423: @10688 5142 GIM_Try, /*On fail goto*//*Label 424*/ 10728, // Rule ID 1258 // 5143 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5144 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev, 5145 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 5146 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 5148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 5149 // (intrinsic_wo_chain:{ *:[i32] } 3026:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) 5150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV_MM, 5151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5153 GIR_EraseFromParent, /*InsnID*/0, 5154 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5155 // GIR_Coverage, 1258, 5156 GIR_Done, 5157 // Label 424: @10728 5158 GIM_Reject, 5159 // Label 370: @10729 5160 GIM_Try, /*On fail goto*//*Label 425*/ 21997, 5161 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, 5162 GIM_Try, /*On fail goto*//*Label 426*/ 10793, // Rule ID 357 // 5163 GIM_CheckFeatures, GIFBS_HasDSP, 5164 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, 5165 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5166 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5167 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5170 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5171 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5172 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 5173 // MIs[1] Operand 1 5174 // No operand predicates 5175 GIM_CheckIsSafeToFold, /*InsnID*/1, 5176 // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa) 5177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH, 5178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 5180 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa 5181 GIR_EraseFromParent, /*InsnID*/0, 5182 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5183 // GIR_Coverage, 357, 5184 GIR_Done, 5185 // Label 426: @10793 5186 GIM_Try, /*On fail goto*//*Label 427*/ 10852, // Rule ID 361 // 5187 GIM_CheckFeatures, GIFBS_HasDSP, 5188 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, 5189 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 5190 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5191 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 5193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 5194 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5195 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5196 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 5197 // MIs[1] Operand 1 5198 // No operand predicates 5199 GIM_CheckIsSafeToFold, /*InsnID*/1, 5200 // (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa) 5201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W, 5202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 5204 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa 5205 GIR_EraseFromParent, /*InsnID*/0, 5206 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5207 // GIR_Coverage, 361, 5208 GIR_Done, 5209 // Label 427: @10852 5210 GIM_Try, /*On fail goto*//*Label 428*/ 10911, // Rule ID 452 // 5211 GIM_CheckFeatures, GIFBS_HasDSPR2, 5212 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, 5213 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 5214 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5215 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5218 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5219 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5220 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 5221 // MIs[1] Operand 1 5222 // No operand predicates 5223 GIM_CheckIsSafeToFold, /*InsnID*/1, 5224 // (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa) 5225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB, 5226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 5228 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa 5229 GIR_EraseFromParent, /*InsnID*/0, 5230 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5231 // GIR_Coverage, 452, 5232 GIR_Done, 5233 // Label 428: @10911 5234 GIM_Try, /*On fail goto*//*Label 429*/ 10970, // Rule ID 906 // 5235 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5236 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_b, 5237 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5238 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5239 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 5241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 5242 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5243 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5244 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 5245 // MIs[1] Operand 1 5246 // No operand predicates 5247 GIM_CheckIsSafeToFold, /*InsnID*/1, 5248 // (intrinsic_wo_chain:{ *:[v16i8] } 3472:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m) 5249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_B, 5250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5252 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5253 GIR_EraseFromParent, /*InsnID*/0, 5254 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5255 // GIR_Coverage, 906, 5256 GIR_Done, 5257 // Label 429: @10970 5258 GIM_Try, /*On fail goto*//*Label 430*/ 11029, // Rule ID 907 // 5259 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5260 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_h, 5261 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5262 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5263 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 5265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 5266 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5267 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5268 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 5269 // MIs[1] Operand 1 5270 // No operand predicates 5271 GIM_CheckIsSafeToFold, /*InsnID*/1, 5272 // (intrinsic_wo_chain:{ *:[v8i16] } 3474:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m) 5273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_H, 5274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5276 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5277 GIR_EraseFromParent, /*InsnID*/0, 5278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5279 // GIR_Coverage, 907, 5280 GIR_Done, 5281 // Label 430: @11029 5282 GIM_Try, /*On fail goto*//*Label 431*/ 11088, // Rule ID 908 // 5283 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5284 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_w, 5285 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5286 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5287 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 5289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 5290 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5291 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5292 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 5293 // MIs[1] Operand 1 5294 // No operand predicates 5295 GIM_CheckIsSafeToFold, /*InsnID*/1, 5296 // (intrinsic_wo_chain:{ *:[v4i32] } 3475:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m) 5297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_W, 5298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5300 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5301 GIR_EraseFromParent, /*InsnID*/0, 5302 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5303 // GIR_Coverage, 908, 5304 GIR_Done, 5305 // Label 431: @11088 5306 GIM_Try, /*On fail goto*//*Label 432*/ 11147, // Rule ID 909 // 5307 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5308 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_d, 5309 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 5310 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5311 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 5313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 5314 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5315 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5316 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6, 5317 // MIs[1] Operand 1 5318 // No operand predicates 5319 GIM_CheckIsSafeToFold, /*InsnID*/1, 5320 // (intrinsic_wo_chain:{ *:[v2i64] } 3473:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m) 5321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_D, 5322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5324 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5325 GIR_EraseFromParent, /*InsnID*/0, 5326 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5327 // GIR_Coverage, 909, 5328 GIR_Done, 5329 // Label 432: @11147 5330 GIM_Try, /*On fail goto*//*Label 433*/ 11206, // Rule ID 910 // 5331 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5332 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_b, 5333 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5334 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5335 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 5337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 5338 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5339 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5340 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 5341 // MIs[1] Operand 1 5342 // No operand predicates 5343 GIM_CheckIsSafeToFold, /*InsnID*/1, 5344 // (intrinsic_wo_chain:{ *:[v16i8] } 3476:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m) 5345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_B, 5346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5348 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5349 GIR_EraseFromParent, /*InsnID*/0, 5350 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5351 // GIR_Coverage, 910, 5352 GIR_Done, 5353 // Label 433: @11206 5354 GIM_Try, /*On fail goto*//*Label 434*/ 11265, // Rule ID 911 // 5355 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5356 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_h, 5357 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5358 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5359 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 5361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 5362 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5363 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5364 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 5365 // MIs[1] Operand 1 5366 // No operand predicates 5367 GIM_CheckIsSafeToFold, /*InsnID*/1, 5368 // (intrinsic_wo_chain:{ *:[v8i16] } 3478:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m) 5369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_H, 5370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5372 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5373 GIR_EraseFromParent, /*InsnID*/0, 5374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5375 // GIR_Coverage, 911, 5376 GIR_Done, 5377 // Label 434: @11265 5378 GIM_Try, /*On fail goto*//*Label 435*/ 11324, // Rule ID 912 // 5379 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_w, 5381 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5382 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5383 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 5385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 5386 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5387 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5388 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 5389 // MIs[1] Operand 1 5390 // No operand predicates 5391 GIM_CheckIsSafeToFold, /*InsnID*/1, 5392 // (intrinsic_wo_chain:{ *:[v4i32] } 3479:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m) 5393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_W, 5394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5396 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5397 GIR_EraseFromParent, /*InsnID*/0, 5398 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5399 // GIR_Coverage, 912, 5400 GIR_Done, 5401 // Label 435: @11324 5402 GIM_Try, /*On fail goto*//*Label 436*/ 11383, // Rule ID 913 // 5403 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5404 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_d, 5405 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 5406 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5407 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 5409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 5410 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5411 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5412 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6, 5413 // MIs[1] Operand 1 5414 // No operand predicates 5415 GIM_CheckIsSafeToFold, /*InsnID*/1, 5416 // (intrinsic_wo_chain:{ *:[v2i64] } 3477:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m) 5417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_D, 5418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5420 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5421 GIR_EraseFromParent, /*InsnID*/0, 5422 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5423 // GIR_Coverage, 913, 5424 GIR_Done, 5425 // Label 436: @11383 5426 GIM_Try, /*On fail goto*//*Label 437*/ 11442, // Rule ID 953 // 5427 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5428 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_b, 5429 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5430 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5431 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 5433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 5434 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5435 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5436 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 5437 // MIs[1] Operand 1 5438 // No operand predicates 5439 GIM_CheckIsSafeToFold, /*InsnID*/1, 5440 // (intrinsic_wo_chain:{ *:[v16i8] } 3531:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m) 5441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_B, 5442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5444 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5445 GIR_EraseFromParent, /*InsnID*/0, 5446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5447 // GIR_Coverage, 953, 5448 GIR_Done, 5449 // Label 437: @11442 5450 GIM_Try, /*On fail goto*//*Label 438*/ 11501, // Rule ID 954 // 5451 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5452 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_h, 5453 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5454 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5455 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 5457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 5458 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5459 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5460 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 5461 // MIs[1] Operand 1 5462 // No operand predicates 5463 GIM_CheckIsSafeToFold, /*InsnID*/1, 5464 // (intrinsic_wo_chain:{ *:[v8i16] } 3533:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m) 5465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_H, 5466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5468 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5469 GIR_EraseFromParent, /*InsnID*/0, 5470 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5471 // GIR_Coverage, 954, 5472 GIR_Done, 5473 // Label 438: @11501 5474 GIM_Try, /*On fail goto*//*Label 439*/ 11560, // Rule ID 955 // 5475 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5476 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_w, 5477 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5478 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5479 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 5481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 5482 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5483 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5484 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 5485 // MIs[1] Operand 1 5486 // No operand predicates 5487 GIM_CheckIsSafeToFold, /*InsnID*/1, 5488 // (intrinsic_wo_chain:{ *:[v4i32] } 3534:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m) 5489 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_W, 5490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5491 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5492 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5493 GIR_EraseFromParent, /*InsnID*/0, 5494 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5495 // GIR_Coverage, 955, 5496 GIR_Done, 5497 // Label 439: @11560 5498 GIM_Try, /*On fail goto*//*Label 440*/ 11619, // Rule ID 956 // 5499 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5500 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_d, 5501 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 5502 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5503 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 5505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 5506 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5507 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5508 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6, 5509 // MIs[1] Operand 1 5510 // No operand predicates 5511 GIM_CheckIsSafeToFold, /*InsnID*/1, 5512 // (intrinsic_wo_chain:{ *:[v2i64] } 3532:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m) 5513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_D, 5514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5516 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5517 GIR_EraseFromParent, /*InsnID*/0, 5518 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5519 // GIR_Coverage, 956, 5520 GIR_Done, 5521 // Label 440: @11619 5522 GIM_Try, /*On fail goto*//*Label 441*/ 11678, // Rule ID 969 // 5523 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5524 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_b, 5525 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 5526 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5527 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 5529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 5530 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5531 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5532 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 5533 // MIs[1] Operand 1 5534 // No operand predicates 5535 GIM_CheckIsSafeToFold, /*InsnID*/1, 5536 // (intrinsic_wo_chain:{ *:[v16i8] } 3547:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m) 5537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_B, 5538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5540 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5541 GIR_EraseFromParent, /*InsnID*/0, 5542 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5543 // GIR_Coverage, 969, 5544 GIR_Done, 5545 // Label 441: @11678 5546 GIM_Try, /*On fail goto*//*Label 442*/ 11737, // Rule ID 970 // 5547 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5548 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_h, 5549 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 5550 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5551 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 5553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 5554 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5555 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5556 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 5557 // MIs[1] Operand 1 5558 // No operand predicates 5559 GIM_CheckIsSafeToFold, /*InsnID*/1, 5560 // (intrinsic_wo_chain:{ *:[v8i16] } 3549:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m) 5561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_H, 5562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5564 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5565 GIR_EraseFromParent, /*InsnID*/0, 5566 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5567 // GIR_Coverage, 970, 5568 GIR_Done, 5569 // Label 442: @11737 5570 GIM_Try, /*On fail goto*//*Label 443*/ 11796, // Rule ID 971 // 5571 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5572 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_w, 5573 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 5574 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5575 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 5577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 5578 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5579 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5580 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 5581 // MIs[1] Operand 1 5582 // No operand predicates 5583 GIM_CheckIsSafeToFold, /*InsnID*/1, 5584 // (intrinsic_wo_chain:{ *:[v4i32] } 3550:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m) 5585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_W, 5586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5588 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5589 GIR_EraseFromParent, /*InsnID*/0, 5590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5591 // GIR_Coverage, 971, 5592 GIR_Done, 5593 // Label 443: @11796 5594 GIM_Try, /*On fail goto*//*Label 444*/ 11855, // Rule ID 972 // 5595 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 5596 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_d, 5597 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 5598 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5599 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 5601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 5602 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5603 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5604 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6, 5605 // MIs[1] Operand 1 5606 // No operand predicates 5607 GIM_CheckIsSafeToFold, /*InsnID*/1, 5608 // (intrinsic_wo_chain:{ *:[v2i64] } 3548:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m) 5609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_D, 5610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 5611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 5612 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m 5613 GIR_EraseFromParent, /*InsnID*/0, 5614 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5615 // GIR_Coverage, 972, 5616 GIR_Done, 5617 // Label 444: @11855 5618 GIM_Try, /*On fail goto*//*Label 445*/ 11914, // Rule ID 1202 // 5619 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5620 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, 5621 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5622 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5623 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5626 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5627 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5628 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 5629 // MIs[1] Operand 1 5630 // No operand predicates 5631 GIM_CheckIsSafeToFold, /*InsnID*/1, 5632 // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa) 5633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH_MM, 5634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5636 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 5637 GIR_EraseFromParent, /*InsnID*/0, 5638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5639 // GIR_Coverage, 1202, 5640 GIR_Done, 5641 // Label 445: @11914 5642 GIM_Try, /*On fail goto*//*Label 446*/ 11973, // Rule ID 1206 // 5643 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 5644 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, 5645 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 5646 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5647 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 5649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 5650 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5651 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5652 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 5653 // MIs[1] Operand 1 5654 // No operand predicates 5655 GIM_CheckIsSafeToFold, /*InsnID*/1, 5656 // (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa) 5657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W_MM, 5658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5660 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 5661 GIR_EraseFromParent, /*InsnID*/0, 5662 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5663 // GIR_Coverage, 1206, 5664 GIR_Done, 5665 // Label 446: @11973 5666 GIM_Try, /*On fail goto*//*Label 447*/ 12032, // Rule ID 1281 // 5667 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 5668 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, 5669 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 5670 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5671 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5674 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5675 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5676 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 5677 // MIs[1] Operand 1 5678 // No operand predicates 5679 GIM_CheckIsSafeToFold, /*InsnID*/1, 5680 // (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa) 5681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB_MMR2, 5682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 5683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5684 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 5685 GIR_EraseFromParent, /*InsnID*/0, 5686 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5687 // GIR_Coverage, 1281, 5688 GIR_Done, 5689 // Label 447: @12032 5690 GIM_Try, /*On fail goto*//*Label 448*/ 12087, // Rule ID 1851 // 5691 GIM_CheckFeatures, GIFBS_HasDSP, 5692 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph, 5693 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5694 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5695 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5697 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5698 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5699 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 5700 // MIs[1] Operand 1 5701 // No operand predicates 5702 GIM_CheckIsSafeToFold, /*InsnID*/1, 5703 // (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) 5704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_PH, 5705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 5707 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 5708 GIR_EraseFromParent, /*InsnID*/0, 5709 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5710 // GIR_Coverage, 1851, 5711 GIR_Done, 5712 // Label 448: @12087 5713 GIM_Try, /*On fail goto*//*Label 449*/ 12142, // Rule ID 1852 // 5714 GIM_CheckFeatures, GIFBS_HasDSPR2, 5715 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph, 5716 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5717 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5718 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5720 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5721 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5722 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 5723 // MIs[1] Operand 1 5724 // No operand predicates 5725 GIM_CheckIsSafeToFold, /*InsnID*/1, 5726 // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) 5727 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_PH, 5728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 5730 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 5731 GIR_EraseFromParent, /*InsnID*/0, 5732 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5733 // GIR_Coverage, 1852, 5734 GIR_Done, 5735 // Label 449: @12142 5736 GIM_Try, /*On fail goto*//*Label 450*/ 12197, // Rule ID 1857 // 5737 GIM_CheckFeatures, GIFBS_HasDSPR2, 5738 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb, 5739 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 5740 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5741 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5743 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5744 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5745 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 5746 // MIs[1] Operand 1 5747 // No operand predicates 5748 GIM_CheckIsSafeToFold, /*InsnID*/1, 5749 // (intrinsic_wo_chain:{ *:[v4i8] } 3489:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) 5750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_QB, 5751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 5753 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 5754 GIR_EraseFromParent, /*InsnID*/0, 5755 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5756 // GIR_Coverage, 1857, 5757 GIR_Done, 5758 // Label 450: @12197 5759 GIM_Try, /*On fail goto*//*Label 451*/ 12252, // Rule ID 1858 // 5760 GIM_CheckFeatures, GIFBS_HasDSP, 5761 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb, 5762 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 5763 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5764 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5766 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 5767 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5768 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 5769 // MIs[1] Operand 1 5770 // No operand predicates 5771 GIM_CheckIsSafeToFold, /*InsnID*/1, 5772 // (intrinsic_wo_chain:{ *:[v4i8] } 3494:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) 5773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_QB, 5774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 5776 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 5777 GIR_EraseFromParent, /*InsnID*/0, 5778 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5779 // GIR_Coverage, 1858, 5780 GIR_Done, 5781 // Label 451: @12252 5782 GIM_Try, /*On fail goto*//*Label 452*/ 12304, // Rule ID 327 // 5783 GIM_CheckFeatures, GIFBS_HasDSP, 5784 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb, 5785 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 5786 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5787 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 5788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 5791 // (intrinsic_wo_chain:{ *:[v4i8] } 2962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 5792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB, 5793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 5796 GIR_EraseFromParent, /*InsnID*/0, 5797 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5798 // GIR_Coverage, 327, 5799 GIR_Done, 5800 // Label 452: @12304 5801 GIM_Try, /*On fail goto*//*Label 453*/ 12356, // Rule ID 328 // 5802 GIM_CheckFeatures, GIFBS_HasDSP, 5803 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb, 5804 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 5805 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5806 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 5807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 5810 // (intrinsic_wo_chain:{ *:[v4i8] } 3581:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 5811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB, 5812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 5815 GIR_EraseFromParent, /*InsnID*/0, 5816 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5817 // GIR_Coverage, 328, 5818 GIR_Done, 5819 // Label 453: @12356 5820 GIM_Try, /*On fail goto*//*Label 454*/ 12408, // Rule ID 329 // 5821 GIM_CheckFeatures, GIFBS_HasDSP, 5822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph, 5823 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5824 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5825 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 5826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 5829 // (intrinsic_wo_chain:{ *:[v2i16] } 2940:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 5830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH, 5831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 5834 GIR_EraseFromParent, /*InsnID*/0, 5835 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5836 // GIR_Coverage, 329, 5837 GIR_Done, 5838 // Label 454: @12408 5839 GIM_Try, /*On fail goto*//*Label 455*/ 12460, // Rule ID 330 // 5840 GIM_CheckFeatures, GIFBS_HasDSP, 5841 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph, 5842 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5843 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5844 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 5845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 5848 // (intrinsic_wo_chain:{ *:[v2i16] } 3556:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 5849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH, 5850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 5853 GIR_EraseFromParent, /*InsnID*/0, 5854 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5855 // GIR_Coverage, 330, 5856 GIR_Done, 5857 // Label 455: @12460 5858 GIM_Try, /*On fail goto*//*Label 456*/ 12512, // Rule ID 333 // 5859 GIM_CheckFeatures, GIFBS_HasDSP, 5860 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub, 5861 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 5862 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5863 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 5865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 5866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 5867 // (intrinsic_wo_chain:{ *:[i32] } 3388:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 5868 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB, 5869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5871 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 5872 GIR_EraseFromParent, /*InsnID*/0, 5873 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5874 // GIR_Coverage, 333, 5875 GIR_Done, 5876 // Label 456: @12512 5877 GIM_Try, /*On fail goto*//*Label 457*/ 12564, // Rule ID 337 // 5878 GIM_CheckFeatures, GIFBS_HasDSP, 5879 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph, 5880 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 5881 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5882 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 5883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 5886 // (intrinsic_wo_chain:{ *:[v4i8] } 3464:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 5887 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH, 5888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 5891 GIR_EraseFromParent, /*InsnID*/0, 5892 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5893 // GIR_Coverage, 337, 5894 GIR_Done, 5895 // Label 457: @12564 5896 GIM_Try, /*On fail goto*//*Label 458*/ 12616, // Rule ID 338 // 5897 GIM_CheckFeatures, GIFBS_HasDSP, 5898 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w, 5899 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5900 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5901 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 5904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 5905 // (intrinsic_wo_chain:{ *:[v2i16] } 3463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 5906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W, 5907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 5909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 5910 GIR_EraseFromParent, /*InsnID*/0, 5911 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5912 // GIR_Coverage, 338, 5913 GIR_Done, 5914 // Label 458: @12616 5915 GIM_Try, /*On fail goto*//*Label 459*/ 12668, // Rule ID 352 // 5916 GIM_CheckFeatures, GIFBS_HasDSP, 5917 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb, 5918 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 5919 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 5920 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 5924 // (intrinsic_wo_chain:{ *:[v4i8] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 5925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB, 5926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 5928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 5929 GIR_EraseFromParent, /*InsnID*/0, 5930 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5931 // GIR_Coverage, 352, 5932 GIR_Done, 5933 // Label 459: @12668 5934 GIM_Try, /*On fail goto*//*Label 460*/ 12720, // Rule ID 356 // 5935 GIM_CheckFeatures, GIFBS_HasDSP, 5936 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph, 5937 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5938 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5939 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 5943 // (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 5944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH, 5945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 5947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 5948 GIR_EraseFromParent, /*InsnID*/0, 5949 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5950 // GIR_Coverage, 356, 5951 GIR_Done, 5952 // Label 460: @12720 5953 GIM_Try, /*On fail goto*//*Label 461*/ 12772, // Rule ID 358 // 5954 GIM_CheckFeatures, GIFBS_HasDSP, 5955 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, 5956 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5957 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5958 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 5962 // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 5963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH, 5964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 5966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 5967 GIR_EraseFromParent, /*InsnID*/0, 5968 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5969 // GIR_Coverage, 358, 5970 GIR_Done, 5971 // Label 461: @12772 5972 GIM_Try, /*On fail goto*//*Label 462*/ 12824, // Rule ID 362 // 5973 GIM_CheckFeatures, GIFBS_HasDSP, 5974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, 5975 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 5976 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5977 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 5978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 5979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 5980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 5981 // (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 5982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W, 5983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 5985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 5986 GIR_EraseFromParent, /*InsnID*/0, 5987 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5988 // GIR_Coverage, 362, 5989 GIR_Done, 5990 // Label 462: @12824 5991 GIM_Try, /*On fail goto*//*Label 463*/ 12876, // Rule ID 399 // 5992 GIM_CheckFeatures, GIFBS_HasDSP, 5993 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph, 5994 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 5995 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 5996 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 5997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 5998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 5999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 6000 // (intrinsic_wo_chain:{ *:[v2i16] } 3435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 6001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH, 6002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6005 GIR_EraseFromParent, /*InsnID*/0, 6006 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6007 // GIR_Coverage, 399, 6008 GIR_Done, 6009 // Label 463: @12876 6010 GIM_Try, /*On fail goto*//*Label 464*/ 12928, // Rule ID 423 // 6011 GIM_CheckFeatures, GIFBS_HasDSPR2, 6012 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb, 6013 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 6014 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 6015 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 6016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 6019 // (intrinsic_wo_chain:{ *:[v4i8] } 2963:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 6020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB, 6021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6024 GIR_EraseFromParent, /*InsnID*/0, 6025 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6026 // GIR_Coverage, 423, 6027 GIR_Done, 6028 // Label 464: @12928 6029 GIM_Try, /*On fail goto*//*Label 465*/ 12980, // Rule ID 424 // 6030 GIM_CheckFeatures, GIFBS_HasDSPR2, 6031 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb, 6032 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 6033 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 6034 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 6035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 6038 // (intrinsic_wo_chain:{ *:[v4i8] } 2964:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 6039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB, 6040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6043 GIR_EraseFromParent, /*InsnID*/0, 6044 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6045 // GIR_Coverage, 424, 6046 GIR_Done, 6047 // Label 465: @12980 6048 GIM_Try, /*On fail goto*//*Label 466*/ 13032, // Rule ID 425 // 6049 GIM_CheckFeatures, GIFBS_HasDSPR2, 6050 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb, 6051 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 6052 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 6053 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 6054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 6057 // (intrinsic_wo_chain:{ *:[v4i8] } 3582:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 6058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB, 6059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6062 GIR_EraseFromParent, /*InsnID*/0, 6063 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6064 // GIR_Coverage, 425, 6065 GIR_Done, 6066 // Label 466: @13032 6067 GIM_Try, /*On fail goto*//*Label 467*/ 13084, // Rule ID 426 // 6068 GIM_CheckFeatures, GIFBS_HasDSPR2, 6069 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb, 6070 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 6071 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 6072 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 6073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 6076 // (intrinsic_wo_chain:{ *:[v4i8] } 3583:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 6077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB, 6078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6081 GIR_EraseFromParent, /*InsnID*/0, 6082 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6083 // GIR_Coverage, 426, 6084 GIR_Done, 6085 // Label 467: @13084 6086 GIM_Try, /*On fail goto*//*Label 468*/ 13136, // Rule ID 427 // 6087 GIM_CheckFeatures, GIFBS_HasDSPR2, 6088 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph, 6089 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 6090 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 6091 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 6092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 6095 // (intrinsic_wo_chain:{ *:[v2i16] } 2942:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 6096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH, 6097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6100 GIR_EraseFromParent, /*InsnID*/0, 6101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6102 // GIR_Coverage, 427, 6103 GIR_Done, 6104 // Label 468: @13136 6105 GIM_Try, /*On fail goto*//*Label 469*/ 13188, // Rule ID 428 // 6106 GIM_CheckFeatures, GIFBS_HasDSPR2, 6107 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph, 6108 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 6109 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 6110 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 6111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 6114 // (intrinsic_wo_chain:{ *:[v2i16] } 2943:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 6115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH, 6116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6119 GIR_EraseFromParent, /*InsnID*/0, 6120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6121 // GIR_Coverage, 428, 6122 GIR_Done, 6123 // Label 469: @13188 6124 GIM_Try, /*On fail goto*//*Label 470*/ 13240, // Rule ID 429 // 6125 GIM_CheckFeatures, GIFBS_HasDSPR2, 6126 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph, 6127 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 6128 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 6129 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 6130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 6133 // (intrinsic_wo_chain:{ *:[v2i16] } 3558:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 6134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH, 6135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6138 GIR_EraseFromParent, /*InsnID*/0, 6139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6140 // GIR_Coverage, 429, 6141 GIR_Done, 6142 // Label 470: @13240 6143 GIM_Try, /*On fail goto*//*Label 471*/ 13292, // Rule ID 430 // 6144 GIM_CheckFeatures, GIFBS_HasDSPR2, 6145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph, 6146 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 6147 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 6148 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 6149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 6152 // (intrinsic_wo_chain:{ *:[v2i16] } 3559:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 6153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH, 6154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6157 GIR_EraseFromParent, /*InsnID*/0, 6158 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6159 // GIR_Coverage, 430, 6160 GIR_Done, 6161 // Label 471: @13292 6162 GIM_Try, /*On fail goto*//*Label 472*/ 13344, // Rule ID 431 // 6163 GIM_CheckFeatures, GIFBS_HasDSPR2, 6164 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w, 6165 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 6166 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6167 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 6168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 6169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 6170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 6171 // (intrinsic_wo_chain:{ *:[i32] } 2945:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 6172 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W, 6173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6176 GIR_EraseFromParent, /*InsnID*/0, 6177 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6178 // GIR_Coverage, 431, 6179 GIR_Done, 6180 // Label 472: @13344 6181 GIM_Try, /*On fail goto*//*Label 473*/ 13396, // Rule ID 432 // 6182 GIM_CheckFeatures, GIFBS_HasDSPR2, 6183 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w, 6184 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 6185 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6186 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 6187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 6188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 6189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 6190 // (intrinsic_wo_chain:{ *:[i32] } 2944:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 6191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W, 6192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6195 GIR_EraseFromParent, /*InsnID*/0, 6196 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6197 // GIR_Coverage, 432, 6198 GIR_Done, 6199 // Label 473: @13396 6200 GIM_Try, /*On fail goto*//*Label 474*/ 13448, // Rule ID 433 // 6201 GIM_CheckFeatures, GIFBS_HasDSPR2, 6202 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w, 6203 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 6204 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6205 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 6206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 6207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 6208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 6209 // (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 6210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W, 6211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6214 GIR_EraseFromParent, /*InsnID*/0, 6215 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6216 // GIR_Coverage, 433, 6217 GIR_Done, 6218 // Label 474: @13448 6219 GIM_Try, /*On fail goto*//*Label 475*/ 13500, // Rule ID 434 // 6220 GIM_CheckFeatures, GIFBS_HasDSPR2, 6221 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w, 6222 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 6223 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6224 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 6225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 6226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 6227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 6228 // (intrinsic_wo_chain:{ *:[i32] } 3560:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 6229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W, 6230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 6232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 6233 GIR_EraseFromParent, /*InsnID*/0, 6234 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6235 // GIR_Coverage, 434, 6236 GIR_Done, 6237 // Label 475: @13500 6238 GIM_Try, /*On fail goto*//*Label 476*/ 13552, // Rule ID 451 // 6239 GIM_CheckFeatures, GIFBS_HasDSPR2, 6240 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb, 6241 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 6242 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 6243 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 6244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 6247 // (intrinsic_wo_chain:{ *:[v4i8] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 6248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB, 6249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 6251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 6252 GIR_EraseFromParent, /*InsnID*/0, 6253 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6254 // GIR_Coverage, 451, 6255 GIR_Done, 6256 // Label 476: @13552 6257 GIM_Try, /*On fail goto*//*Label 477*/ 13604, // Rule ID 453 // 6258 GIM_CheckFeatures, GIFBS_HasDSPR2, 6259 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, 6260 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 6261 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 6262 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 6263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 6266 // (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 6267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB, 6268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 6270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 6271 GIR_EraseFromParent, /*InsnID*/0, 6272 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6273 // GIR_Coverage, 453, 6274 GIR_Done, 6275 // Label 477: @13604 6276 GIM_Try, /*On fail goto*//*Label 478*/ 13656, // Rule ID 454 // 6277 GIM_CheckFeatures, GIFBS_HasDSPR2, 6278 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph, 6279 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 6280 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 6281 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 6282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 6283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 6284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 6285 // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 6286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH, 6287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 6289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 6290 GIR_EraseFromParent, /*InsnID*/0, 6291 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6292 // GIR_Coverage, 454, 6293 GIR_Done, 6294 // Label 478: @13656 6295 GIM_Try, /*On fail goto*//*Label 479*/ 13708, // Rule ID 459 // 6296 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6297 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_b, 6298 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6299 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6300 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6304 // (intrinsic_wo_chain:{ *:[v16i8] } 2935:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6305 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_B, 6306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6309 GIR_EraseFromParent, /*InsnID*/0, 6310 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6311 // GIR_Coverage, 459, 6312 GIR_Done, 6313 // Label 479: @13708 6314 GIM_Try, /*On fail goto*//*Label 480*/ 13760, // Rule ID 460 // 6315 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6316 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_h, 6317 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6318 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6319 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 6321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 6322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 6323 // (intrinsic_wo_chain:{ *:[v8i16] } 2937:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 6324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_H, 6325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6328 GIR_EraseFromParent, /*InsnID*/0, 6329 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6330 // GIR_Coverage, 460, 6331 GIR_Done, 6332 // Label 480: @13760 6333 GIM_Try, /*On fail goto*//*Label 481*/ 13812, // Rule ID 461 // 6334 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6335 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_w, 6336 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6337 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6338 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 6340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 6341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 6342 // (intrinsic_wo_chain:{ *:[v4i32] } 2938:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 6343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_W, 6344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6347 GIR_EraseFromParent, /*InsnID*/0, 6348 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6349 // GIR_Coverage, 461, 6350 GIR_Done, 6351 // Label 481: @13812 6352 GIM_Try, /*On fail goto*//*Label 482*/ 13864, // Rule ID 462 // 6353 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6354 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_d, 6355 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6356 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6357 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 6359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 6360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 6361 // (intrinsic_wo_chain:{ *:[v2i64] } 2936:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 6362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_D, 6363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6366 GIR_EraseFromParent, /*InsnID*/0, 6367 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6368 // GIR_Coverage, 462, 6369 GIR_Done, 6370 // Label 482: @13864 6371 GIM_Try, /*On fail goto*//*Label 483*/ 13916, // Rule ID 463 // 6372 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6373 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_b, 6374 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6375 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6376 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6380 // (intrinsic_wo_chain:{ *:[v16i8] } 2946:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_B, 6382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6385 GIR_EraseFromParent, /*InsnID*/0, 6386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6387 // GIR_Coverage, 463, 6388 GIR_Done, 6389 // Label 483: @13916 6390 GIM_Try, /*On fail goto*//*Label 484*/ 13968, // Rule ID 464 // 6391 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6392 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_h, 6393 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6394 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6395 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 6397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 6398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 6399 // (intrinsic_wo_chain:{ *:[v8i16] } 2948:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 6400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_H, 6401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6404 GIR_EraseFromParent, /*InsnID*/0, 6405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6406 // GIR_Coverage, 464, 6407 GIR_Done, 6408 // Label 484: @13968 6409 GIM_Try, /*On fail goto*//*Label 485*/ 14020, // Rule ID 465 // 6410 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6411 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_w, 6412 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6413 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6414 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 6416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 6417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 6418 // (intrinsic_wo_chain:{ *:[v4i32] } 2949:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 6419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_W, 6420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6423 GIR_EraseFromParent, /*InsnID*/0, 6424 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6425 // GIR_Coverage, 465, 6426 GIR_Done, 6427 // Label 485: @14020 6428 GIM_Try, /*On fail goto*//*Label 486*/ 14072, // Rule ID 466 // 6429 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6430 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_d, 6431 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6432 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6433 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 6435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 6436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 6437 // (intrinsic_wo_chain:{ *:[v2i64] } 2947:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 6438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_D, 6439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6442 GIR_EraseFromParent, /*InsnID*/0, 6443 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6444 // GIR_Coverage, 466, 6445 GIR_Done, 6446 // Label 486: @14072 6447 GIM_Try, /*On fail goto*//*Label 487*/ 14124, // Rule ID 467 // 6448 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6449 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_b, 6450 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6451 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6452 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6456 // (intrinsic_wo_chain:{ *:[v16i8] } 2950:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_B, 6458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6461 GIR_EraseFromParent, /*InsnID*/0, 6462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6463 // GIR_Coverage, 467, 6464 GIR_Done, 6465 // Label 487: @14124 6466 GIM_Try, /*On fail goto*//*Label 488*/ 14176, // Rule ID 468 // 6467 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6468 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_h, 6469 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6470 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6471 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 6473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 6474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 6475 // (intrinsic_wo_chain:{ *:[v8i16] } 2952:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 6476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_H, 6477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6480 GIR_EraseFromParent, /*InsnID*/0, 6481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6482 // GIR_Coverage, 468, 6483 GIR_Done, 6484 // Label 488: @14176 6485 GIM_Try, /*On fail goto*//*Label 489*/ 14228, // Rule ID 469 // 6486 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6487 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_w, 6488 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6489 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6490 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 6492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 6493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 6494 // (intrinsic_wo_chain:{ *:[v4i32] } 2953:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 6495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_W, 6496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6499 GIR_EraseFromParent, /*InsnID*/0, 6500 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6501 // GIR_Coverage, 469, 6502 GIR_Done, 6503 // Label 489: @14228 6504 GIM_Try, /*On fail goto*//*Label 490*/ 14280, // Rule ID 470 // 6505 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6506 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_d, 6507 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6508 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6509 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 6511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 6512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 6513 // (intrinsic_wo_chain:{ *:[v2i64] } 2951:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 6514 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_D, 6515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6518 GIR_EraseFromParent, /*InsnID*/0, 6519 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6520 // GIR_Coverage, 470, 6521 GIR_Done, 6522 // Label 490: @14280 6523 GIM_Try, /*On fail goto*//*Label 491*/ 14332, // Rule ID 471 // 6524 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6525 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_b, 6526 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6527 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6528 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6532 // (intrinsic_wo_chain:{ *:[v16i8] } 2954:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_B, 6534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6537 GIR_EraseFromParent, /*InsnID*/0, 6538 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6539 // GIR_Coverage, 471, 6540 GIR_Done, 6541 // Label 491: @14332 6542 GIM_Try, /*On fail goto*//*Label 492*/ 14384, // Rule ID 472 // 6543 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6544 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_h, 6545 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6546 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6547 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 6549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 6550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 6551 // (intrinsic_wo_chain:{ *:[v8i16] } 2956:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 6552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_H, 6553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6556 GIR_EraseFromParent, /*InsnID*/0, 6557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6558 // GIR_Coverage, 472, 6559 GIR_Done, 6560 // Label 492: @14384 6561 GIM_Try, /*On fail goto*//*Label 493*/ 14436, // Rule ID 473 // 6562 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6563 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_w, 6564 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6565 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6566 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 6568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 6569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 6570 // (intrinsic_wo_chain:{ *:[v4i32] } 2957:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 6571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_W, 6572 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6575 GIR_EraseFromParent, /*InsnID*/0, 6576 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6577 // GIR_Coverage, 473, 6578 GIR_Done, 6579 // Label 493: @14436 6580 GIM_Try, /*On fail goto*//*Label 494*/ 14488, // Rule ID 474 // 6581 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6582 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_d, 6583 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6584 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6585 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 6587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 6588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 6589 // (intrinsic_wo_chain:{ *:[v2i64] } 2955:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 6590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_D, 6591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6594 GIR_EraseFromParent, /*InsnID*/0, 6595 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6596 // GIR_Coverage, 474, 6597 GIR_Done, 6598 // Label 494: @14488 6599 GIM_Try, /*On fail goto*//*Label 495*/ 14540, // Rule ID 488 // 6600 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6601 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_b, 6602 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6603 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6604 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6608 // (intrinsic_wo_chain:{ *:[v16i8] } 2977:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_B, 6610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6613 GIR_EraseFromParent, /*InsnID*/0, 6614 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6615 // GIR_Coverage, 488, 6616 GIR_Done, 6617 // Label 495: @14540 6618 GIM_Try, /*On fail goto*//*Label 496*/ 14592, // Rule ID 489 // 6619 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6620 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_h, 6621 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6622 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6623 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 6625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 6626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 6627 // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 6628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_H, 6629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6632 GIR_EraseFromParent, /*InsnID*/0, 6633 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6634 // GIR_Coverage, 489, 6635 GIR_Done, 6636 // Label 496: @14592 6637 GIM_Try, /*On fail goto*//*Label 497*/ 14644, // Rule ID 490 // 6638 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6639 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_w, 6640 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6641 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6642 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 6644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 6645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 6646 // (intrinsic_wo_chain:{ *:[v4i32] } 2980:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 6647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_W, 6648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6651 GIR_EraseFromParent, /*InsnID*/0, 6652 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6653 // GIR_Coverage, 490, 6654 GIR_Done, 6655 // Label 497: @14644 6656 GIM_Try, /*On fail goto*//*Label 498*/ 14696, // Rule ID 491 // 6657 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_d, 6659 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6660 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6661 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 6663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 6664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 6665 // (intrinsic_wo_chain:{ *:[v2i64] } 2978:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 6666 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_D, 6667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6670 GIR_EraseFromParent, /*InsnID*/0, 6671 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6672 // GIR_Coverage, 491, 6673 GIR_Done, 6674 // Label 498: @14696 6675 GIM_Try, /*On fail goto*//*Label 499*/ 14748, // Rule ID 492 // 6676 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6677 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_b, 6678 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6679 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6680 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6684 // (intrinsic_wo_chain:{ *:[v16i8] } 2981:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_B, 6686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6689 GIR_EraseFromParent, /*InsnID*/0, 6690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6691 // GIR_Coverage, 492, 6692 GIR_Done, 6693 // Label 499: @14748 6694 GIM_Try, /*On fail goto*//*Label 500*/ 14800, // Rule ID 493 // 6695 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6696 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_h, 6697 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6698 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6699 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 6701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 6702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 6703 // (intrinsic_wo_chain:{ *:[v8i16] } 2983:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 6704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_H, 6705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6708 GIR_EraseFromParent, /*InsnID*/0, 6709 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6710 // GIR_Coverage, 493, 6711 GIR_Done, 6712 // Label 500: @14800 6713 GIM_Try, /*On fail goto*//*Label 501*/ 14852, // Rule ID 494 // 6714 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6715 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_w, 6716 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6717 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6718 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 6720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 6721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 6722 // (intrinsic_wo_chain:{ *:[v4i32] } 2984:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 6723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_W, 6724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6727 GIR_EraseFromParent, /*InsnID*/0, 6728 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6729 // GIR_Coverage, 494, 6730 GIR_Done, 6731 // Label 501: @14852 6732 GIM_Try, /*On fail goto*//*Label 502*/ 14904, // Rule ID 495 // 6733 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6734 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_d, 6735 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6736 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6737 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 6739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 6740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 6741 // (intrinsic_wo_chain:{ *:[v2i64] } 2982:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 6742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_D, 6743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6746 GIR_EraseFromParent, /*InsnID*/0, 6747 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6748 // GIR_Coverage, 495, 6749 GIR_Done, 6750 // Label 502: @14904 6751 GIM_Try, /*On fail goto*//*Label 503*/ 14956, // Rule ID 496 // 6752 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6753 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_b, 6754 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6755 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6756 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6760 // (intrinsic_wo_chain:{ *:[v16i8] } 2985:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_B, 6762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6765 GIR_EraseFromParent, /*InsnID*/0, 6766 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6767 // GIR_Coverage, 496, 6768 GIR_Done, 6769 // Label 503: @14956 6770 GIM_Try, /*On fail goto*//*Label 504*/ 15008, // Rule ID 497 // 6771 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6772 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_h, 6773 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6774 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6775 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 6777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 6778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 6779 // (intrinsic_wo_chain:{ *:[v8i16] } 2987:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 6780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_H, 6781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6784 GIR_EraseFromParent, /*InsnID*/0, 6785 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6786 // GIR_Coverage, 497, 6787 GIR_Done, 6788 // Label 504: @15008 6789 GIM_Try, /*On fail goto*//*Label 505*/ 15060, // Rule ID 498 // 6790 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6791 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_w, 6792 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6793 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6794 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 6796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 6797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 6798 // (intrinsic_wo_chain:{ *:[v4i32] } 2988:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 6799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_W, 6800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6803 GIR_EraseFromParent, /*InsnID*/0, 6804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6805 // GIR_Coverage, 498, 6806 GIR_Done, 6807 // Label 505: @15060 6808 GIM_Try, /*On fail goto*//*Label 506*/ 15112, // Rule ID 499 // 6809 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6810 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_d, 6811 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6812 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6813 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 6815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 6816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 6817 // (intrinsic_wo_chain:{ *:[v2i64] } 2986:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 6818 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_D, 6819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6822 GIR_EraseFromParent, /*InsnID*/0, 6823 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6824 // GIR_Coverage, 499, 6825 GIR_Done, 6826 // Label 506: @15112 6827 GIM_Try, /*On fail goto*//*Label 507*/ 15164, // Rule ID 500 // 6828 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6829 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_b, 6830 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6831 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6832 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6836 // (intrinsic_wo_chain:{ *:[v16i8] } 2989:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_B, 6838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6841 GIR_EraseFromParent, /*InsnID*/0, 6842 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6843 // GIR_Coverage, 500, 6844 GIR_Done, 6845 // Label 507: @15164 6846 GIM_Try, /*On fail goto*//*Label 508*/ 15216, // Rule ID 501 // 6847 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6848 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_h, 6849 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6850 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6851 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 6853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 6854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 6855 // (intrinsic_wo_chain:{ *:[v8i16] } 2991:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 6856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_H, 6857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6860 GIR_EraseFromParent, /*InsnID*/0, 6861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6862 // GIR_Coverage, 501, 6863 GIR_Done, 6864 // Label 508: @15216 6865 GIM_Try, /*On fail goto*//*Label 509*/ 15268, // Rule ID 502 // 6866 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6867 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_w, 6868 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6869 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6870 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 6872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 6873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 6874 // (intrinsic_wo_chain:{ *:[v4i32] } 2992:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 6875 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_W, 6876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6879 GIR_EraseFromParent, /*InsnID*/0, 6880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6881 // GIR_Coverage, 502, 6882 GIR_Done, 6883 // Label 509: @15268 6884 GIM_Try, /*On fail goto*//*Label 510*/ 15320, // Rule ID 503 // 6885 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6886 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_d, 6887 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6888 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6889 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 6891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 6892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 6893 // (intrinsic_wo_chain:{ *:[v2i64] } 2990:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 6894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_D, 6895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6898 GIR_EraseFromParent, /*InsnID*/0, 6899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6900 // GIR_Coverage, 503, 6901 GIR_Done, 6902 // Label 510: @15320 6903 GIM_Try, /*On fail goto*//*Label 511*/ 15372, // Rule ID 504 // 6904 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6905 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_b, 6906 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6907 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6908 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6912 // (intrinsic_wo_chain:{ *:[v16i8] } 2993:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_B, 6914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6917 GIR_EraseFromParent, /*InsnID*/0, 6918 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6919 // GIR_Coverage, 504, 6920 GIR_Done, 6921 // Label 511: @15372 6922 GIM_Try, /*On fail goto*//*Label 512*/ 15424, // Rule ID 505 // 6923 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6924 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_h, 6925 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 6926 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6927 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 6928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 6929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 6930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 6931 // (intrinsic_wo_chain:{ *:[v8i16] } 2995:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 6932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_H, 6933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6936 GIR_EraseFromParent, /*InsnID*/0, 6937 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6938 // GIR_Coverage, 505, 6939 GIR_Done, 6940 // Label 512: @15424 6941 GIM_Try, /*On fail goto*//*Label 513*/ 15476, // Rule ID 506 // 6942 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6943 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_w, 6944 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 6945 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6946 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 6947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 6948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 6949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 6950 // (intrinsic_wo_chain:{ *:[v4i32] } 2996:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 6951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_W, 6952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6955 GIR_EraseFromParent, /*InsnID*/0, 6956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6957 // GIR_Coverage, 506, 6958 GIR_Done, 6959 // Label 513: @15476 6960 GIM_Try, /*On fail goto*//*Label 514*/ 15528, // Rule ID 507 // 6961 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6962 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_d, 6963 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 6964 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6965 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 6966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 6967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 6968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 6969 // (intrinsic_wo_chain:{ *:[v2i64] } 2994:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 6970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_D, 6971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6974 GIR_EraseFromParent, /*InsnID*/0, 6975 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6976 // GIR_Coverage, 507, 6977 GIR_Done, 6978 // Label 514: @15528 6979 GIM_Try, /*On fail goto*//*Label 515*/ 15580, // Rule ID 508 // 6980 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 6981 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_b, 6982 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 6983 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6984 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 6985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 6986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 6987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 6988 // (intrinsic_wo_chain:{ *:[v16i8] } 2997:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 6989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_B, 6990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 6991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 6992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 6993 GIR_EraseFromParent, /*InsnID*/0, 6994 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6995 // GIR_Coverage, 508, 6996 GIR_Done, 6997 // Label 515: @15580 6998 GIM_Try, /*On fail goto*//*Label 516*/ 15632, // Rule ID 509 // 6999 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_h, 7001 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7002 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7003 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 7005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 7006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 7007 // (intrinsic_wo_chain:{ *:[v8i16] } 2999:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 7008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_H, 7009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7012 GIR_EraseFromParent, /*InsnID*/0, 7013 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7014 // GIR_Coverage, 509, 7015 GIR_Done, 7016 // Label 516: @15632 7017 GIM_Try, /*On fail goto*//*Label 517*/ 15684, // Rule ID 510 // 7018 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7019 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_w, 7020 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7021 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7022 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7026 // (intrinsic_wo_chain:{ *:[v4i32] } 3000:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 7027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_W, 7028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7031 GIR_EraseFromParent, /*InsnID*/0, 7032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7033 // GIR_Coverage, 510, 7034 GIR_Done, 7035 // Label 517: @15684 7036 GIM_Try, /*On fail goto*//*Label 518*/ 15736, // Rule ID 511 // 7037 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7038 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_d, 7039 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7040 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7041 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7045 // (intrinsic_wo_chain:{ *:[v2i64] } 2998:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 7046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_D, 7047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7050 GIR_EraseFromParent, /*InsnID*/0, 7051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7052 // GIR_Coverage, 511, 7053 GIR_Done, 7054 // Label 518: @15736 7055 GIM_Try, /*On fail goto*//*Label 519*/ 15788, // Rule ID 620 // 7056 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7057 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_h, 7058 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7059 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7060 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 7062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 7063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 7064 // (intrinsic_wo_chain:{ *:[v8i16] } 3132:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 7065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_H, 7066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7069 GIR_EraseFromParent, /*InsnID*/0, 7070 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7071 // GIR_Coverage, 620, 7072 GIR_Done, 7073 // Label 519: @15788 7074 GIM_Try, /*On fail goto*//*Label 520*/ 15840, // Rule ID 621 // 7075 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7076 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_w, 7077 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7078 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7079 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 7082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 7083 // (intrinsic_wo_chain:{ *:[v4i32] } 3133:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 7084 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_W, 7085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7088 GIR_EraseFromParent, /*InsnID*/0, 7089 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7090 // GIR_Coverage, 621, 7091 GIR_Done, 7092 // Label 520: @15840 7093 GIM_Try, /*On fail goto*//*Label 521*/ 15892, // Rule ID 622 // 7094 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7095 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_d, 7096 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7097 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7098 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7102 // (intrinsic_wo_chain:{ *:[v2i64] } 3131:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 7103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_D, 7104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7107 GIR_EraseFromParent, /*InsnID*/0, 7108 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7109 // GIR_Coverage, 622, 7110 GIR_Done, 7111 // Label 521: @15892 7112 GIM_Try, /*On fail goto*//*Label 522*/ 15944, // Rule ID 623 // 7113 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7114 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_h, 7115 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7116 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7117 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 7119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 7120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 7121 // (intrinsic_wo_chain:{ *:[v8i16] } 3135:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 7122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_H, 7123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7126 GIR_EraseFromParent, /*InsnID*/0, 7127 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7128 // GIR_Coverage, 623, 7129 GIR_Done, 7130 // Label 522: @15944 7131 GIM_Try, /*On fail goto*//*Label 523*/ 15996, // Rule ID 624 // 7132 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7133 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_w, 7134 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7135 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7136 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 7139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 7140 // (intrinsic_wo_chain:{ *:[v4i32] } 3136:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 7141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_W, 7142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7145 GIR_EraseFromParent, /*InsnID*/0, 7146 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7147 // GIR_Coverage, 624, 7148 GIR_Done, 7149 // Label 523: @15996 7150 GIM_Try, /*On fail goto*//*Label 524*/ 16048, // Rule ID 625 // 7151 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7152 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_d, 7153 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7154 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7155 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7159 // (intrinsic_wo_chain:{ *:[v2i64] } 3134:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 7160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_D, 7161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7164 GIR_EraseFromParent, /*InsnID*/0, 7165 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7166 // GIR_Coverage, 625, 7167 GIR_Done, 7168 // Label 524: @16048 7169 GIM_Try, /*On fail goto*//*Label 525*/ 16100, // Rule ID 640 // 7170 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7171 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_w, 7172 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7173 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7174 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7178 // (intrinsic_wo_chain:{ *:[v4i32] } 3174:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_W, 7180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7183 GIR_EraseFromParent, /*InsnID*/0, 7184 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7185 // GIR_Coverage, 640, 7186 GIR_Done, 7187 // Label 525: @16100 7188 GIM_Try, /*On fail goto*//*Label 526*/ 16152, // Rule ID 641 // 7189 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7190 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_d, 7191 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7192 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7193 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7197 // (intrinsic_wo_chain:{ *:[v2i64] } 3173:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7198 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_D, 7199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7202 GIR_EraseFromParent, /*InsnID*/0, 7203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7204 // GIR_Coverage, 641, 7205 GIR_Done, 7206 // Label 526: @16152 7207 GIM_Try, /*On fail goto*//*Label 527*/ 16204, // Rule ID 666 // 7208 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_h, 7210 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7211 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7212 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 7214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7216 // (intrinsic_wo_chain:{ *:[v8f16] } 3199:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_H, 7218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7221 GIR_EraseFromParent, /*InsnID*/0, 7222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7223 // GIR_Coverage, 666, 7224 GIR_Done, 7225 // Label 527: @16204 7226 GIM_Try, /*On fail goto*//*Label 528*/ 16256, // Rule ID 667 // 7227 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7228 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_w, 7229 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7230 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7231 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7235 // (intrinsic_wo_chain:{ *:[v4f32] } 3200:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_W, 7237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7240 GIR_EraseFromParent, /*InsnID*/0, 7241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7242 // GIR_Coverage, 667, 7243 GIR_Done, 7244 // Label 528: @16256 7245 GIM_Try, /*On fail goto*//*Label 529*/ 16308, // Rule ID 694 // 7246 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7247 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_w, 7248 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7249 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7250 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7254 // (intrinsic_wo_chain:{ *:[v4f32] } 3226:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_W, 7256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7259 GIR_EraseFromParent, /*InsnID*/0, 7260 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7261 // GIR_Coverage, 694, 7262 GIR_Done, 7263 // Label 529: @16308 7264 GIM_Try, /*On fail goto*//*Label 530*/ 16360, // Rule ID 695 // 7265 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7266 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_d, 7267 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7268 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7269 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7273 // (intrinsic_wo_chain:{ *:[v2f64] } 3225:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_D, 7275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7278 GIR_EraseFromParent, /*InsnID*/0, 7279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7280 // GIR_Coverage, 695, 7281 GIR_Done, 7282 // Label 530: @16360 7283 GIM_Try, /*On fail goto*//*Label 531*/ 16412, // Rule ID 696 // 7284 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7285 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_w, 7286 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7287 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7288 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7292 // (intrinsic_wo_chain:{ *:[v4f32] } 3224:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_W, 7294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7297 GIR_EraseFromParent, /*InsnID*/0, 7298 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7299 // GIR_Coverage, 696, 7300 GIR_Done, 7301 // Label 531: @16412 7302 GIM_Try, /*On fail goto*//*Label 532*/ 16464, // Rule ID 697 // 7303 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7304 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_d, 7305 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7306 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7307 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7311 // (intrinsic_wo_chain:{ *:[v2f64] } 3223:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_D, 7313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7316 GIR_EraseFromParent, /*InsnID*/0, 7317 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7318 // GIR_Coverage, 697, 7319 GIR_Done, 7320 // Label 532: @16464 7321 GIM_Try, /*On fail goto*//*Label 533*/ 16516, // Rule ID 698 // 7322 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7323 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_w, 7324 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7325 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7326 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7330 // (intrinsic_wo_chain:{ *:[v4f32] } 3230:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_W, 7332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7335 GIR_EraseFromParent, /*InsnID*/0, 7336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7337 // GIR_Coverage, 698, 7338 GIR_Done, 7339 // Label 533: @16516 7340 GIM_Try, /*On fail goto*//*Label 534*/ 16568, // Rule ID 699 // 7341 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7342 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_d, 7343 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7344 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7345 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7349 // (intrinsic_wo_chain:{ *:[v2f64] } 3229:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_D, 7351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7354 GIR_EraseFromParent, /*InsnID*/0, 7355 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7356 // GIR_Coverage, 699, 7357 GIR_Done, 7358 // Label 534: @16568 7359 GIM_Try, /*On fail goto*//*Label 535*/ 16620, // Rule ID 700 // 7360 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7361 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_w, 7362 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7363 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7364 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7368 // (intrinsic_wo_chain:{ *:[v4f32] } 3228:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_W, 7370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7373 GIR_EraseFromParent, /*InsnID*/0, 7374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7375 // GIR_Coverage, 700, 7376 GIR_Done, 7377 // Label 535: @16620 7378 GIM_Try, /*On fail goto*//*Label 536*/ 16672, // Rule ID 701 // 7379 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_d, 7381 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7382 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7383 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7387 // (intrinsic_wo_chain:{ *:[v2f64] } 3227:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_D, 7389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7392 GIR_EraseFromParent, /*InsnID*/0, 7393 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7394 // GIR_Coverage, 701, 7395 GIR_Done, 7396 // Label 536: @16672 7397 GIM_Try, /*On fail goto*//*Label 537*/ 16724, // Rule ID 712 // 7398 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7399 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_w, 7400 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7401 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7402 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7406 // (intrinsic_wo_chain:{ *:[v4i32] } 3242:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_W, 7408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7411 GIR_EraseFromParent, /*InsnID*/0, 7412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7413 // GIR_Coverage, 712, 7414 GIR_Done, 7415 // Label 537: @16724 7416 GIM_Try, /*On fail goto*//*Label 538*/ 16776, // Rule ID 713 // 7417 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7418 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_d, 7419 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7420 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7421 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7425 // (intrinsic_wo_chain:{ *:[v2i64] } 3241:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_D, 7427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7430 GIR_EraseFromParent, /*InsnID*/0, 7431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7432 // GIR_Coverage, 713, 7433 GIR_Done, 7434 // Label 538: @16776 7435 GIM_Try, /*On fail goto*//*Label 539*/ 16828, // Rule ID 714 // 7436 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7437 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_w, 7438 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7439 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7440 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7444 // (intrinsic_wo_chain:{ *:[v4i32] } 3244:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_W, 7446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7449 GIR_EraseFromParent, /*InsnID*/0, 7450 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7451 // GIR_Coverage, 714, 7452 GIR_Done, 7453 // Label 539: @16828 7454 GIM_Try, /*On fail goto*//*Label 540*/ 16880, // Rule ID 715 // 7455 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7456 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_d, 7457 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7458 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7459 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7463 // (intrinsic_wo_chain:{ *:[v2i64] } 3243:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7464 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_D, 7465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7468 GIR_EraseFromParent, /*InsnID*/0, 7469 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7470 // GIR_Coverage, 715, 7471 GIR_Done, 7472 // Label 540: @16880 7473 GIM_Try, /*On fail goto*//*Label 541*/ 16932, // Rule ID 716 // 7474 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7475 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_w, 7476 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7477 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7478 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7482 // (intrinsic_wo_chain:{ *:[v4i32] } 3246:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_W, 7484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7487 GIR_EraseFromParent, /*InsnID*/0, 7488 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7489 // GIR_Coverage, 716, 7490 GIR_Done, 7491 // Label 541: @16932 7492 GIM_Try, /*On fail goto*//*Label 542*/ 16984, // Rule ID 717 // 7493 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7494 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_d, 7495 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7496 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7497 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7501 // (intrinsic_wo_chain:{ *:[v2i64] } 3245:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_D, 7503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7506 GIR_EraseFromParent, /*InsnID*/0, 7507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7508 // GIR_Coverage, 717, 7509 GIR_Done, 7510 // Label 542: @16984 7511 GIM_Try, /*On fail goto*//*Label 543*/ 17036, // Rule ID 718 // 7512 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7513 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_w, 7514 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7515 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7516 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7520 // (intrinsic_wo_chain:{ *:[v4i32] } 3248:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_W, 7522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7525 GIR_EraseFromParent, /*InsnID*/0, 7526 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7527 // GIR_Coverage, 718, 7528 GIR_Done, 7529 // Label 543: @17036 7530 GIM_Try, /*On fail goto*//*Label 544*/ 17088, // Rule ID 719 // 7531 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_d, 7533 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7534 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7535 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7539 // (intrinsic_wo_chain:{ *:[v2i64] } 3247:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_D, 7541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7544 GIR_EraseFromParent, /*InsnID*/0, 7545 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7546 // GIR_Coverage, 719, 7547 GIR_Done, 7548 // Label 544: @17088 7549 GIM_Try, /*On fail goto*//*Label 545*/ 17140, // Rule ID 720 // 7550 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7551 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_w, 7552 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7553 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7554 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7558 // (intrinsic_wo_chain:{ *:[v4i32] } 3250:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7559 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_W, 7560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7563 GIR_EraseFromParent, /*InsnID*/0, 7564 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7565 // GIR_Coverage, 720, 7566 GIR_Done, 7567 // Label 545: @17140 7568 GIM_Try, /*On fail goto*//*Label 546*/ 17192, // Rule ID 721 // 7569 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7570 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_d, 7571 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7572 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7573 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7577 // (intrinsic_wo_chain:{ *:[v2i64] } 3249:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_D, 7579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7581 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7582 GIR_EraseFromParent, /*InsnID*/0, 7583 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7584 // GIR_Coverage, 721, 7585 GIR_Done, 7586 // Label 546: @17192 7587 GIM_Try, /*On fail goto*//*Label 547*/ 17244, // Rule ID 722 // 7588 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7589 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_w, 7590 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7591 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7592 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7596 // (intrinsic_wo_chain:{ *:[v4i32] } 3252:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_W, 7598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7601 GIR_EraseFromParent, /*InsnID*/0, 7602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7603 // GIR_Coverage, 722, 7604 GIR_Done, 7605 // Label 547: @17244 7606 GIM_Try, /*On fail goto*//*Label 548*/ 17296, // Rule ID 723 // 7607 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7608 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_d, 7609 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7610 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7611 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7615 // (intrinsic_wo_chain:{ *:[v2i64] } 3251:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_D, 7617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7620 GIR_EraseFromParent, /*InsnID*/0, 7621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7622 // GIR_Coverage, 723, 7623 GIR_Done, 7624 // Label 548: @17296 7625 GIM_Try, /*On fail goto*//*Label 549*/ 17348, // Rule ID 728 // 7626 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7627 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_w, 7628 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7629 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7630 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7634 // (intrinsic_wo_chain:{ *:[v4i32] } 3258:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7635 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_W, 7636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7639 GIR_EraseFromParent, /*InsnID*/0, 7640 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7641 // GIR_Coverage, 728, 7642 GIR_Done, 7643 // Label 549: @17348 7644 GIM_Try, /*On fail goto*//*Label 550*/ 17400, // Rule ID 729 // 7645 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7646 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_d, 7647 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7648 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7649 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7653 // (intrinsic_wo_chain:{ *:[v2i64] } 3257:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_D, 7655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7658 GIR_EraseFromParent, /*InsnID*/0, 7659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7660 // GIR_Coverage, 729, 7661 GIR_Done, 7662 // Label 550: @17400 7663 GIM_Try, /*On fail goto*//*Label 551*/ 17452, // Rule ID 730 // 7664 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_w, 7666 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7667 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7668 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7672 // (intrinsic_wo_chain:{ *:[v4i32] } 3260:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_W, 7674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7677 GIR_EraseFromParent, /*InsnID*/0, 7678 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7679 // GIR_Coverage, 730, 7680 GIR_Done, 7681 // Label 551: @17452 7682 GIM_Try, /*On fail goto*//*Label 552*/ 17504, // Rule ID 731 // 7683 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7684 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_d, 7685 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7686 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7687 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7691 // (intrinsic_wo_chain:{ *:[v2i64] } 3259:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_D, 7693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7696 GIR_EraseFromParent, /*InsnID*/0, 7697 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7698 // GIR_Coverage, 731, 7699 GIR_Done, 7700 // Label 552: @17504 7701 GIM_Try, /*On fail goto*//*Label 553*/ 17556, // Rule ID 732 // 7702 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7703 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_w, 7704 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7705 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7706 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7710 // (intrinsic_wo_chain:{ *:[v4i32] } 3262:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_W, 7712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7715 GIR_EraseFromParent, /*InsnID*/0, 7716 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7717 // GIR_Coverage, 732, 7718 GIR_Done, 7719 // Label 553: @17556 7720 GIM_Try, /*On fail goto*//*Label 554*/ 17608, // Rule ID 733 // 7721 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7722 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_d, 7723 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7724 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7725 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7729 // (intrinsic_wo_chain:{ *:[v2i64] } 3261:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_D, 7731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7734 GIR_EraseFromParent, /*InsnID*/0, 7735 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7736 // GIR_Coverage, 733, 7737 GIR_Done, 7738 // Label 554: @17608 7739 GIM_Try, /*On fail goto*//*Label 555*/ 17660, // Rule ID 734 // 7740 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7741 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_w, 7742 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7743 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7744 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7748 // (intrinsic_wo_chain:{ *:[v4i32] } 3264:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_W, 7750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7753 GIR_EraseFromParent, /*InsnID*/0, 7754 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7755 // GIR_Coverage, 734, 7756 GIR_Done, 7757 // Label 555: @17660 7758 GIM_Try, /*On fail goto*//*Label 556*/ 17712, // Rule ID 735 // 7759 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7760 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_d, 7761 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7762 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7763 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7767 // (intrinsic_wo_chain:{ *:[v2i64] } 3263:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_D, 7769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7772 GIR_EraseFromParent, /*InsnID*/0, 7773 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7774 // GIR_Coverage, 735, 7775 GIR_Done, 7776 // Label 556: @17712 7777 GIM_Try, /*On fail goto*//*Label 557*/ 17764, // Rule ID 736 // 7778 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7779 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_w, 7780 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7781 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7782 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7786 // (intrinsic_wo_chain:{ *:[v4i32] } 3266:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7787 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_W, 7788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7791 GIR_EraseFromParent, /*InsnID*/0, 7792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7793 // GIR_Coverage, 736, 7794 GIR_Done, 7795 // Label 557: @17764 7796 GIM_Try, /*On fail goto*//*Label 558*/ 17816, // Rule ID 737 // 7797 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7798 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_d, 7799 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7800 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7801 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7805 // (intrinsic_wo_chain:{ *:[v2i64] } 3265:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_D, 7807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7810 GIR_EraseFromParent, /*InsnID*/0, 7811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7812 // GIR_Coverage, 737, 7813 GIR_Done, 7814 // Label 558: @17816 7815 GIM_Try, /*On fail goto*//*Label 559*/ 17868, // Rule ID 742 // 7816 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7817 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_h, 7818 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7819 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7820 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 7822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7824 // (intrinsic_wo_chain:{ *:[v8i16] } 3271:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 7825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_H, 7826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7829 GIR_EraseFromParent, /*InsnID*/0, 7830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7831 // GIR_Coverage, 742, 7832 GIR_Done, 7833 // Label 559: @17868 7834 GIM_Try, /*On fail goto*//*Label 560*/ 17920, // Rule ID 743 // 7835 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7836 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_w, 7837 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7838 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7839 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 7840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 7842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 7843 // (intrinsic_wo_chain:{ *:[v4i32] } 3272:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 7844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_W, 7845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7848 GIR_EraseFromParent, /*InsnID*/0, 7849 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7850 // GIR_Coverage, 743, 7851 GIR_Done, 7852 // Label 560: @17920 7853 GIM_Try, /*On fail goto*//*Label 561*/ 17972, // Rule ID 748 // 7854 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7855 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_h, 7856 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7857 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7858 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 7860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 7861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 7862 // (intrinsic_wo_chain:{ *:[v8i16] } 3278:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 7863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_H, 7864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7867 GIR_EraseFromParent, /*InsnID*/0, 7868 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7869 // GIR_Coverage, 748, 7870 GIR_Done, 7871 // Label 561: @17972 7872 GIM_Try, /*On fail goto*//*Label 562*/ 18024, // Rule ID 749 // 7873 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7874 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_w, 7875 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7876 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7877 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 7880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 7881 // (intrinsic_wo_chain:{ *:[v4i32] } 3279:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 7882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_W, 7883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7886 GIR_EraseFromParent, /*InsnID*/0, 7887 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7888 // GIR_Coverage, 749, 7889 GIR_Done, 7890 // Label 562: @18024 7891 GIM_Try, /*On fail goto*//*Label 563*/ 18076, // Rule ID 750 // 7892 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7893 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_d, 7894 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7895 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7896 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7900 // (intrinsic_wo_chain:{ *:[v2i64] } 3277:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 7901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_D, 7902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7905 GIR_EraseFromParent, /*InsnID*/0, 7906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7907 // GIR_Coverage, 750, 7908 GIR_Done, 7909 // Label 563: @18076 7910 GIM_Try, /*On fail goto*//*Label 564*/ 18128, // Rule ID 751 // 7911 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7912 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_h, 7913 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7914 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7915 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 7917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 7918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 7919 // (intrinsic_wo_chain:{ *:[v8i16] } 3281:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 7920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_H, 7921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7924 GIR_EraseFromParent, /*InsnID*/0, 7925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7926 // GIR_Coverage, 751, 7927 GIR_Done, 7928 // Label 564: @18128 7929 GIM_Try, /*On fail goto*//*Label 565*/ 18180, // Rule ID 752 // 7930 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7931 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_w, 7932 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7933 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7934 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 7937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 7938 // (intrinsic_wo_chain:{ *:[v4i32] } 3282:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 7939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_W, 7940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7943 GIR_EraseFromParent, /*InsnID*/0, 7944 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7945 // GIR_Coverage, 752, 7946 GIR_Done, 7947 // Label 565: @18180 7948 GIM_Try, /*On fail goto*//*Label 566*/ 18232, // Rule ID 753 // 7949 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7950 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_d, 7951 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7952 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7953 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 7955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 7956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 7957 // (intrinsic_wo_chain:{ *:[v2i64] } 3280:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 7958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_D, 7959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7962 GIR_EraseFromParent, /*InsnID*/0, 7963 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7964 // GIR_Coverage, 753, 7965 GIR_Done, 7966 // Label 566: @18232 7967 GIM_Try, /*On fail goto*//*Label 567*/ 18284, // Rule ID 754 // 7968 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7969 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_h, 7970 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7971 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7972 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 7974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 7975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 7976 // (intrinsic_wo_chain:{ *:[v8i16] } 3284:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 7977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_H, 7978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 7981 GIR_EraseFromParent, /*InsnID*/0, 7982 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7983 // GIR_Coverage, 754, 7984 GIR_Done, 7985 // Label 567: @18284 7986 GIM_Try, /*On fail goto*//*Label 568*/ 18336, // Rule ID 755 // 7987 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 7988 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_w, 7989 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7990 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7991 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 7993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 7994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 7995 // (intrinsic_wo_chain:{ *:[v4i32] } 3285:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 7996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_W, 7997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 7998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 7999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8000 GIR_EraseFromParent, /*InsnID*/0, 8001 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8002 // GIR_Coverage, 755, 8003 GIR_Done, 8004 // Label 568: @18336 8005 GIM_Try, /*On fail goto*//*Label 569*/ 18388, // Rule ID 756 // 8006 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8007 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_d, 8008 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8009 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8010 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8014 // (intrinsic_wo_chain:{ *:[v2i64] } 3283:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8015 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_D, 8016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8019 GIR_EraseFromParent, /*InsnID*/0, 8020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8021 // GIR_Coverage, 756, 8022 GIR_Done, 8023 // Label 569: @18388 8024 GIM_Try, /*On fail goto*//*Label 570*/ 18440, // Rule ID 757 // 8025 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8026 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_h, 8027 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8028 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8029 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 8032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 8033 // (intrinsic_wo_chain:{ *:[v8i16] } 3287:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 8034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_H, 8035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8038 GIR_EraseFromParent, /*InsnID*/0, 8039 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8040 // GIR_Coverage, 757, 8041 GIR_Done, 8042 // Label 570: @18440 8043 GIM_Try, /*On fail goto*//*Label 571*/ 18492, // Rule ID 758 // 8044 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8045 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_w, 8046 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8047 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8048 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8052 // (intrinsic_wo_chain:{ *:[v4i32] } 3288:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_W, 8054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8057 GIR_EraseFromParent, /*InsnID*/0, 8058 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8059 // GIR_Coverage, 758, 8060 GIR_Done, 8061 // Label 571: @18492 8062 GIM_Try, /*On fail goto*//*Label 572*/ 18544, // Rule ID 759 // 8063 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8064 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_d, 8065 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8066 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8067 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8071 // (intrinsic_wo_chain:{ *:[v2i64] } 3286:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_D, 8073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8076 GIR_EraseFromParent, /*InsnID*/0, 8077 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8078 // GIR_Coverage, 759, 8079 GIR_Done, 8080 // Label 572: @18544 8081 GIM_Try, /*On fail goto*//*Label 573*/ 18596, // Rule ID 812 // 8082 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8083 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_b, 8084 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8085 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8086 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 8088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 8089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 8090 // (intrinsic_wo_chain:{ *:[v16i8] } 3340:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 8091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_B, 8092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8095 GIR_EraseFromParent, /*InsnID*/0, 8096 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8097 // GIR_Coverage, 812, 8098 GIR_Done, 8099 // Label 573: @18596 8100 GIM_Try, /*On fail goto*//*Label 574*/ 18648, // Rule ID 813 // 8101 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8102 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_h, 8103 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8104 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8105 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8109 // (intrinsic_wo_chain:{ *:[v8i16] } 3342:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_H, 8111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8114 GIR_EraseFromParent, /*InsnID*/0, 8115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8116 // GIR_Coverage, 813, 8117 GIR_Done, 8118 // Label 574: @18648 8119 GIM_Try, /*On fail goto*//*Label 575*/ 18700, // Rule ID 814 // 8120 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8121 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_w, 8122 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8123 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8124 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8128 // (intrinsic_wo_chain:{ *:[v4i32] } 3343:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_W, 8130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8133 GIR_EraseFromParent, /*InsnID*/0, 8134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8135 // GIR_Coverage, 814, 8136 GIR_Done, 8137 // Label 575: @18700 8138 GIM_Try, /*On fail goto*//*Label 576*/ 18752, // Rule ID 815 // 8139 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8140 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_d, 8141 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8142 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8143 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 8146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 8147 // (intrinsic_wo_chain:{ *:[v2i64] } 3341:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 8148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_D, 8149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8152 GIR_EraseFromParent, /*InsnID*/0, 8153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8154 // GIR_Coverage, 815, 8155 GIR_Done, 8156 // Label 576: @18752 8157 GIM_Try, /*On fail goto*//*Label 577*/ 18804, // Rule ID 832 // 8158 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8159 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_b, 8160 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8161 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8162 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 8164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 8165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 8166 // (intrinsic_wo_chain:{ *:[v16i8] } 3360:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 8167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_B, 8168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8171 GIR_EraseFromParent, /*InsnID*/0, 8172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8173 // GIR_Coverage, 832, 8174 GIR_Done, 8175 // Label 577: @18804 8176 GIM_Try, /*On fail goto*//*Label 578*/ 18856, // Rule ID 833 // 8177 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8178 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_h, 8179 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8180 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8181 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8185 // (intrinsic_wo_chain:{ *:[v8i16] } 3362:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_H, 8187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8190 GIR_EraseFromParent, /*InsnID*/0, 8191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8192 // GIR_Coverage, 833, 8193 GIR_Done, 8194 // Label 578: @18856 8195 GIM_Try, /*On fail goto*//*Label 579*/ 18908, // Rule ID 834 // 8196 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8197 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_w, 8198 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8199 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8200 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8204 // (intrinsic_wo_chain:{ *:[v4i32] } 3363:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8205 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_W, 8206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8209 GIR_EraseFromParent, /*InsnID*/0, 8210 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8211 // GIR_Coverage, 834, 8212 GIR_Done, 8213 // Label 579: @18908 8214 GIM_Try, /*On fail goto*//*Label 580*/ 18960, // Rule ID 835 // 8215 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8216 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_d, 8217 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8218 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8219 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 8222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 8223 // (intrinsic_wo_chain:{ *:[v2i64] } 3361:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 8224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_D, 8225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8228 GIR_EraseFromParent, /*InsnID*/0, 8229 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8230 // GIR_Coverage, 835, 8231 GIR_Done, 8232 // Label 580: @18960 8233 GIM_Try, /*On fail goto*//*Label 581*/ 19012, // Rule ID 868 // 8234 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8235 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_h, 8236 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8237 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8238 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8242 // (intrinsic_wo_chain:{ *:[v8i16] } 3402:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_H, 8244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8247 GIR_EraseFromParent, /*InsnID*/0, 8248 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8249 // GIR_Coverage, 868, 8250 GIR_Done, 8251 // Label 581: @19012 8252 GIM_Try, /*On fail goto*//*Label 582*/ 19064, // Rule ID 869 // 8253 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8254 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_w, 8255 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8256 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8257 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8261 // (intrinsic_wo_chain:{ *:[v4i32] } 3403:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_W, 8263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8266 GIR_EraseFromParent, /*InsnID*/0, 8267 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8268 // GIR_Coverage, 869, 8269 GIR_Done, 8270 // Label 582: @19064 8271 GIM_Try, /*On fail goto*//*Label 583*/ 19116, // Rule ID 870 // 8272 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8273 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_h, 8274 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8275 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8276 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8280 // (intrinsic_wo_chain:{ *:[v8i16] } 3413:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_H, 8282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8285 GIR_EraseFromParent, /*InsnID*/0, 8286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8287 // GIR_Coverage, 870, 8288 GIR_Done, 8289 // Label 583: @19116 8290 GIM_Try, /*On fail goto*//*Label 584*/ 19168, // Rule ID 871 // 8291 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8292 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_w, 8293 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8294 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8295 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8299 // (intrinsic_wo_chain:{ *:[v4i32] } 3414:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_W, 8301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8304 GIR_EraseFromParent, /*InsnID*/0, 8305 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8306 // GIR_Coverage, 871, 8307 GIR_Done, 8308 // Label 584: @19168 8309 GIM_Try, /*On fail goto*//*Label 585*/ 19220, // Rule ID 949 // 8310 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8311 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_b, 8312 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8313 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8314 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 8316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 8317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 8318 // (intrinsic_wo_chain:{ *:[v16i8] } 3527:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 8319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_B, 8320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8323 GIR_EraseFromParent, /*InsnID*/0, 8324 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8325 // GIR_Coverage, 949, 8326 GIR_Done, 8327 // Label 585: @19220 8328 GIM_Try, /*On fail goto*//*Label 586*/ 19272, // Rule ID 950 // 8329 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8330 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_h, 8331 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8332 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8333 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8337 // (intrinsic_wo_chain:{ *:[v8i16] } 3529:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8338 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_H, 8339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8342 GIR_EraseFromParent, /*InsnID*/0, 8343 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8344 // GIR_Coverage, 950, 8345 GIR_Done, 8346 // Label 586: @19272 8347 GIM_Try, /*On fail goto*//*Label 587*/ 19324, // Rule ID 951 // 8348 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8349 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_w, 8350 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8351 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8352 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8356 // (intrinsic_wo_chain:{ *:[v4i32] } 3530:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_W, 8358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8361 GIR_EraseFromParent, /*InsnID*/0, 8362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8363 // GIR_Coverage, 951, 8364 GIR_Done, 8365 // Label 587: @19324 8366 GIM_Try, /*On fail goto*//*Label 588*/ 19376, // Rule ID 952 // 8367 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8368 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_d, 8369 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8370 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8371 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 8374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 8375 // (intrinsic_wo_chain:{ *:[v2i64] } 3528:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 8376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_D, 8377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8380 GIR_EraseFromParent, /*InsnID*/0, 8381 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8382 // GIR_Coverage, 952, 8383 GIR_Done, 8384 // Label 588: @19376 8385 GIM_Try, /*On fail goto*//*Label 589*/ 19428, // Rule ID 965 // 8386 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8387 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_b, 8388 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8389 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8390 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 8392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 8393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 8394 // (intrinsic_wo_chain:{ *:[v16i8] } 3543:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 8395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_B, 8396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8399 GIR_EraseFromParent, /*InsnID*/0, 8400 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8401 // GIR_Coverage, 965, 8402 GIR_Done, 8403 // Label 589: @19428 8404 GIM_Try, /*On fail goto*//*Label 590*/ 19480, // Rule ID 966 // 8405 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8406 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_h, 8407 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8408 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8409 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8413 // (intrinsic_wo_chain:{ *:[v8i16] } 3545:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8414 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_H, 8415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8418 GIR_EraseFromParent, /*InsnID*/0, 8419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8420 // GIR_Coverage, 966, 8421 GIR_Done, 8422 // Label 590: @19480 8423 GIM_Try, /*On fail goto*//*Label 591*/ 19532, // Rule ID 967 // 8424 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8425 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_w, 8426 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8427 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8428 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8432 // (intrinsic_wo_chain:{ *:[v4i32] } 3546:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_W, 8434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8437 GIR_EraseFromParent, /*InsnID*/0, 8438 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8439 // GIR_Coverage, 967, 8440 GIR_Done, 8441 // Label 591: @19532 8442 GIM_Try, /*On fail goto*//*Label 592*/ 19584, // Rule ID 968 // 8443 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8444 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_d, 8445 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8446 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8447 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 8450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 8451 // (intrinsic_wo_chain:{ *:[v2i64] } 3544:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 8452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_D, 8453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8456 GIR_EraseFromParent, /*InsnID*/0, 8457 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8458 // GIR_Coverage, 968, 8459 GIR_Done, 8460 // Label 592: @19584 8461 GIM_Try, /*On fail goto*//*Label 593*/ 19636, // Rule ID 977 // 8462 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8463 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_b, 8464 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8465 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8466 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 8468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 8469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 8470 // (intrinsic_wo_chain:{ *:[v16i8] } 3562:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 8471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_B, 8472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8475 GIR_EraseFromParent, /*InsnID*/0, 8476 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8477 // GIR_Coverage, 977, 8478 GIR_Done, 8479 // Label 593: @19636 8480 GIM_Try, /*On fail goto*//*Label 594*/ 19688, // Rule ID 978 // 8481 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8482 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_h, 8483 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8484 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8485 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8489 // (intrinsic_wo_chain:{ *:[v8i16] } 3564:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8490 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_H, 8491 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8494 GIR_EraseFromParent, /*InsnID*/0, 8495 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8496 // GIR_Coverage, 978, 8497 GIR_Done, 8498 // Label 594: @19688 8499 GIM_Try, /*On fail goto*//*Label 595*/ 19740, // Rule ID 979 // 8500 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8501 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_w, 8502 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8503 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8504 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8508 // (intrinsic_wo_chain:{ *:[v4i32] } 3565:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8509 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_W, 8510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8513 GIR_EraseFromParent, /*InsnID*/0, 8514 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8515 // GIR_Coverage, 979, 8516 GIR_Done, 8517 // Label 595: @19740 8518 GIM_Try, /*On fail goto*//*Label 596*/ 19792, // Rule ID 980 // 8519 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8520 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_d, 8521 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8522 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8523 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 8526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 8527 // (intrinsic_wo_chain:{ *:[v2i64] } 3563:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 8528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_D, 8529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8532 GIR_EraseFromParent, /*InsnID*/0, 8533 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8534 // GIR_Coverage, 980, 8535 GIR_Done, 8536 // Label 596: @19792 8537 GIM_Try, /*On fail goto*//*Label 597*/ 19844, // Rule ID 981 // 8538 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8539 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_b, 8540 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8541 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8542 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 8544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 8545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 8546 // (intrinsic_wo_chain:{ *:[v16i8] } 3566:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 8547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_B, 8548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8550 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8551 GIR_EraseFromParent, /*InsnID*/0, 8552 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8553 // GIR_Coverage, 981, 8554 GIR_Done, 8555 // Label 597: @19844 8556 GIM_Try, /*On fail goto*//*Label 598*/ 19896, // Rule ID 982 // 8557 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8558 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_h, 8559 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8560 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8561 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8565 // (intrinsic_wo_chain:{ *:[v8i16] } 3568:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_H, 8567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8570 GIR_EraseFromParent, /*InsnID*/0, 8571 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8572 // GIR_Coverage, 982, 8573 GIR_Done, 8574 // Label 598: @19896 8575 GIM_Try, /*On fail goto*//*Label 599*/ 19948, // Rule ID 983 // 8576 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8577 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_w, 8578 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8579 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8580 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8584 // (intrinsic_wo_chain:{ *:[v4i32] } 3569:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_W, 8586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8589 GIR_EraseFromParent, /*InsnID*/0, 8590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8591 // GIR_Coverage, 983, 8592 GIR_Done, 8593 // Label 599: @19948 8594 GIM_Try, /*On fail goto*//*Label 600*/ 20000, // Rule ID 984 // 8595 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8596 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_d, 8597 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8598 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8599 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 8602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 8603 // (intrinsic_wo_chain:{ *:[v2i64] } 3567:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 8604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_D, 8605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8607 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8608 GIR_EraseFromParent, /*InsnID*/0, 8609 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8610 // GIR_Coverage, 984, 8611 GIR_Done, 8612 // Label 600: @20000 8613 GIM_Try, /*On fail goto*//*Label 601*/ 20052, // Rule ID 985 // 8614 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8615 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_b, 8616 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8617 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8618 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 8620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 8621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 8622 // (intrinsic_wo_chain:{ *:[v16i8] } 3570:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 8623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_B, 8624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8627 GIR_EraseFromParent, /*InsnID*/0, 8628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8629 // GIR_Coverage, 985, 8630 GIR_Done, 8631 // Label 601: @20052 8632 GIM_Try, /*On fail goto*//*Label 602*/ 20104, // Rule ID 986 // 8633 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8634 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_h, 8635 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8636 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8637 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8641 // (intrinsic_wo_chain:{ *:[v8i16] } 3572:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_H, 8643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8646 GIR_EraseFromParent, /*InsnID*/0, 8647 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8648 // GIR_Coverage, 986, 8649 GIR_Done, 8650 // Label 602: @20104 8651 GIM_Try, /*On fail goto*//*Label 603*/ 20156, // Rule ID 987 // 8652 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8653 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_w, 8654 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8655 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8656 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8660 // (intrinsic_wo_chain:{ *:[v4i32] } 3573:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_W, 8662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8665 GIR_EraseFromParent, /*InsnID*/0, 8666 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8667 // GIR_Coverage, 987, 8668 GIR_Done, 8669 // Label 603: @20156 8670 GIM_Try, /*On fail goto*//*Label 604*/ 20208, // Rule ID 988 // 8671 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8672 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_d, 8673 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8674 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8675 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 8678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 8679 // (intrinsic_wo_chain:{ *:[v2i64] } 3571:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 8680 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_D, 8681 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8684 GIR_EraseFromParent, /*InsnID*/0, 8685 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8686 // GIR_Coverage, 988, 8687 GIR_Done, 8688 // Label 604: @20208 8689 GIM_Try, /*On fail goto*//*Label 605*/ 20260, // Rule ID 989 // 8690 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8691 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_b, 8692 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8693 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8694 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 8696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 8697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 8698 // (intrinsic_wo_chain:{ *:[v16i8] } 3574:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 8699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_B, 8700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8703 GIR_EraseFromParent, /*InsnID*/0, 8704 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8705 // GIR_Coverage, 989, 8706 GIR_Done, 8707 // Label 605: @20260 8708 GIM_Try, /*On fail goto*//*Label 606*/ 20312, // Rule ID 990 // 8709 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8710 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_h, 8711 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8712 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8713 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 8715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 8716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 8717 // (intrinsic_wo_chain:{ *:[v8i16] } 3576:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 8718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_H, 8719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8722 GIR_EraseFromParent, /*InsnID*/0, 8723 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8724 // GIR_Coverage, 990, 8725 GIR_Done, 8726 // Label 606: @20312 8727 GIM_Try, /*On fail goto*//*Label 607*/ 20364, // Rule ID 991 // 8728 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8729 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_w, 8730 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8731 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8732 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 8734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 8735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 8736 // (intrinsic_wo_chain:{ *:[v4i32] } 3577:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 8737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_W, 8738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8741 GIR_EraseFromParent, /*InsnID*/0, 8742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8743 // GIR_Coverage, 991, 8744 GIR_Done, 8745 // Label 607: @20364 8746 GIM_Try, /*On fail goto*//*Label 608*/ 20416, // Rule ID 992 // 8747 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 8748 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_d, 8749 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8750 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8751 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 8753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 8754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 8755 // (intrinsic_wo_chain:{ *:[v2i64] } 3575:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 8756 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_D, 8757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 8758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 8759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt 8760 GIR_EraseFromParent, /*InsnID*/0, 8761 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8762 // GIR_Coverage, 992, 8763 GIR_Done, 8764 // Label 608: @20416 8765 GIM_Try, /*On fail goto*//*Label 609*/ 20468, // Rule ID 1180 // 8766 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8767 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph, 8768 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 8769 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 8770 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 8771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 8773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 8774 // (intrinsic_wo_chain:{ *:[v2i16] } 2940:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 8775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH_MM, 8776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 8778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 8779 GIR_EraseFromParent, /*InsnID*/0, 8780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8781 // GIR_Coverage, 1180, 8782 GIR_Done, 8783 // Label 609: @20468 8784 GIM_Try, /*On fail goto*//*Label 610*/ 20520, // Rule ID 1182 // 8785 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8786 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb, 8787 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 8788 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 8789 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 8790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 8792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 8793 // (intrinsic_wo_chain:{ *:[v4i8] } 2962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 8794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB_MM, 8795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 8797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 8798 GIR_EraseFromParent, /*InsnID*/0, 8799 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8800 // GIR_Coverage, 1182, 8801 GIR_Done, 8802 // Label 610: @20520 8803 GIM_Try, /*On fail goto*//*Label 611*/ 20572, // Rule ID 1203 // 8804 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8805 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph, 8806 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 8807 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 8808 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 8811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 8812 // (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 8813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH_MM, 8814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 8816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 8817 GIR_EraseFromParent, /*InsnID*/0, 8818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8819 // GIR_Coverage, 1203, 8820 GIR_Done, 8821 // Label 611: @20572 8822 GIM_Try, /*On fail goto*//*Label 612*/ 20624, // Rule ID 1204 // 8823 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8824 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, 8825 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 8826 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 8827 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 8830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 8831 // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 8832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH_MM, 8833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 8835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 8836 GIR_EraseFromParent, /*InsnID*/0, 8837 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8838 // GIR_Coverage, 1204, 8839 GIR_Done, 8840 // Label 612: @20624 8841 GIM_Try, /*On fail goto*//*Label 613*/ 20676, // Rule ID 1205 // 8842 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8843 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, 8844 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 8845 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8846 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 8848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 8849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 8850 // (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 8851 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W_MM, 8852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8853 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 8854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 8855 GIR_EraseFromParent, /*InsnID*/0, 8856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8857 // GIR_Coverage, 1205, 8858 GIR_Done, 8859 // Label 613: @20676 8860 GIM_Try, /*On fail goto*//*Label 614*/ 20728, // Rule ID 1207 // 8861 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8862 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb, 8863 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 8864 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 8865 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 8868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 8869 // (intrinsic_wo_chain:{ *:[v4i8] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 8870 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB_MM, 8871 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 8873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 8874 GIR_EraseFromParent, /*InsnID*/0, 8875 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8876 // GIR_Coverage, 1207, 8877 GIR_Done, 8878 // Label 614: @20728 8879 GIM_Try, /*On fail goto*//*Label 615*/ 20780, // Rule ID 1218 // 8880 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8881 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph, 8882 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 8883 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 8884 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 8885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 8887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 8888 // (intrinsic_wo_chain:{ *:[v2i16] } 3556:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 8889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH_MM, 8890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 8892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 8893 GIR_EraseFromParent, /*InsnID*/0, 8894 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8895 // GIR_Coverage, 1218, 8896 GIR_Done, 8897 // Label 615: @20780 8898 GIM_Try, /*On fail goto*//*Label 616*/ 20832, // Rule ID 1220 // 8899 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8900 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb, 8901 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 8902 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 8903 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 8904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 8906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 8907 // (intrinsic_wo_chain:{ *:[v4i8] } 3581:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 8908 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB_MM, 8909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 8911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 8912 GIR_EraseFromParent, /*InsnID*/0, 8913 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8914 // GIR_Coverage, 1220, 8915 GIR_Done, 8916 // Label 616: @20832 8917 GIM_Try, /*On fail goto*//*Label 617*/ 20884, // Rule ID 1230 // 8918 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8919 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w, 8920 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 8921 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8922 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 8925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 8926 // (intrinsic_wo_chain:{ *:[v2i16] } 3463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 8927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W_MM, 8928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 8930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 8931 GIR_EraseFromParent, /*InsnID*/0, 8932 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8933 // GIR_Coverage, 1230, 8934 GIR_Done, 8935 // Label 617: @20884 8936 GIM_Try, /*On fail goto*//*Label 618*/ 20936, // Rule ID 1231 // 8937 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8938 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph, 8939 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 8940 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 8941 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 8942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 8944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 8945 // (intrinsic_wo_chain:{ *:[v4i8] } 3464:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 8946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH_MM, 8947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 8949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 8950 GIR_EraseFromParent, /*InsnID*/0, 8951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8952 // GIR_Coverage, 1231, 8953 GIR_Done, 8954 // Label 618: @20936 8955 GIM_Try, /*On fail goto*//*Label 619*/ 20988, // Rule ID 1250 // 8956 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8957 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph, 8958 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 8959 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 8960 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 8961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 8962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 8963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 8964 // (intrinsic_wo_chain:{ *:[v2i16] } 3435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 8965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH_MM, 8966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 8968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 8969 GIR_EraseFromParent, /*InsnID*/0, 8970 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8971 // GIR_Coverage, 1250, 8972 GIR_Done, 8973 // Label 619: @20988 8974 GIM_Try, /*On fail goto*//*Label 620*/ 21040, // Rule ID 1256 // 8975 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 8976 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub, 8977 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 8978 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8979 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 8981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 8982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 8983 // (intrinsic_wo_chain:{ *:[i32] } 3388:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 8984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB_MM, 8985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 8986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 8987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 8988 GIR_EraseFromParent, /*InsnID*/0, 8989 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8990 // GIR_Coverage, 1256, 8991 GIR_Done, 8992 // Label 620: @21040 8993 GIM_Try, /*On fail goto*//*Label 621*/ 21092, // Rule ID 1269 // 8994 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 8995 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph, 8996 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 8997 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 8998 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 8999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 9002 // (intrinsic_wo_chain:{ *:[v2i16] } 2942:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 9003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH_MMR2, 9004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9007 GIR_EraseFromParent, /*InsnID*/0, 9008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9009 // GIR_Coverage, 1269, 9010 GIR_Done, 9011 // Label 621: @21092 9012 GIM_Try, /*On fail goto*//*Label 622*/ 21144, // Rule ID 1270 // 9013 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9014 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph, 9015 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9016 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 9017 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 9018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 9021 // (intrinsic_wo_chain:{ *:[v2i16] } 2943:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 9022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH_MMR2, 9023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9026 GIR_EraseFromParent, /*InsnID*/0, 9027 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9028 // GIR_Coverage, 1270, 9029 GIR_Done, 9030 // Label 622: @21144 9031 GIM_Try, /*On fail goto*//*Label 623*/ 21196, // Rule ID 1271 // 9032 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9033 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w, 9034 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9035 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9036 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9040 // (intrinsic_wo_chain:{ *:[i32] } 2945:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 9041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W_MMR2, 9042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9045 GIR_EraseFromParent, /*InsnID*/0, 9046 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9047 // GIR_Coverage, 1271, 9048 GIR_Done, 9049 // Label 623: @21196 9050 GIM_Try, /*On fail goto*//*Label 624*/ 21248, // Rule ID 1272 // 9051 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w, 9053 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9055 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9059 // (intrinsic_wo_chain:{ *:[i32] } 2944:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 9060 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W_MMR2, 9061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9064 GIR_EraseFromParent, /*InsnID*/0, 9065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9066 // GIR_Coverage, 1272, 9067 GIR_Done, 9068 // Label 624: @21248 9069 GIM_Try, /*On fail goto*//*Label 625*/ 21300, // Rule ID 1275 // 9070 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9071 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb, 9072 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 9073 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 9074 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 9075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 9078 // (intrinsic_wo_chain:{ *:[v4i8] } 2963:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 9079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB_MMR2, 9080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9083 GIR_EraseFromParent, /*InsnID*/0, 9084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9085 // GIR_Coverage, 1275, 9086 GIR_Done, 9087 // Label 625: @21300 9088 GIM_Try, /*On fail goto*//*Label 626*/ 21352, // Rule ID 1276 // 9089 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb, 9091 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 9092 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 9093 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 9094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 9097 // (intrinsic_wo_chain:{ *:[v4i8] } 2964:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 9098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB_MMR2, 9099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9102 GIR_EraseFromParent, /*InsnID*/0, 9103 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9104 // GIR_Coverage, 1276, 9105 GIR_Done, 9106 // Label 626: @21352 9107 GIM_Try, /*On fail goto*//*Label 627*/ 21404, // Rule ID 1282 // 9108 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9109 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb, 9110 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 9111 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 9112 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9116 // (intrinsic_wo_chain:{ *:[v4i8] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 9117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB_MMR2, 9118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 9120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9121 GIR_EraseFromParent, /*InsnID*/0, 9122 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9123 // GIR_Coverage, 1282, 9124 GIR_Done, 9125 // Label 627: @21404 9126 GIM_Try, /*On fail goto*//*Label 628*/ 21456, // Rule ID 1283 // 9127 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9128 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, 9129 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 9130 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 9131 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9135 // (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 9136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB_MMR2, 9137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 9139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9140 GIR_EraseFromParent, /*InsnID*/0, 9141 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9142 // GIR_Coverage, 1283, 9143 GIR_Done, 9144 // Label 628: @21456 9145 GIM_Try, /*On fail goto*//*Label 629*/ 21508, // Rule ID 1288 // 9146 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9147 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph, 9148 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9149 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 9150 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9154 // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 9155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH_MMR2, 9156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 9158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9159 GIR_EraseFromParent, /*InsnID*/0, 9160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9161 // GIR_Coverage, 1288, 9162 GIR_Done, 9163 // Label 629: @21508 9164 GIM_Try, /*On fail goto*//*Label 630*/ 21560, // Rule ID 1289 // 9165 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9166 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph, 9167 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9168 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 9169 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 9170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 9173 // (intrinsic_wo_chain:{ *:[v2i16] } 3558:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 9174 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH_MMR2, 9175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9178 GIR_EraseFromParent, /*InsnID*/0, 9179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9180 // GIR_Coverage, 1289, 9181 GIR_Done, 9182 // Label 630: @21560 9183 GIM_Try, /*On fail goto*//*Label 631*/ 21612, // Rule ID 1290 // 9184 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9185 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph, 9186 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9187 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 9188 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 9189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 9192 // (intrinsic_wo_chain:{ *:[v2i16] } 3559:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 9193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH_MMR2, 9194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9197 GIR_EraseFromParent, /*InsnID*/0, 9198 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9199 // GIR_Coverage, 1290, 9200 GIR_Done, 9201 // Label 631: @21612 9202 GIM_Try, /*On fail goto*//*Label 632*/ 21664, // Rule ID 1291 // 9203 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9204 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w, 9205 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9206 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9207 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9211 // (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 9212 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W_MMR2, 9213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9216 GIR_EraseFromParent, /*InsnID*/0, 9217 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9218 // GIR_Coverage, 1291, 9219 GIR_Done, 9220 // Label 632: @21664 9221 GIM_Try, /*On fail goto*//*Label 633*/ 21716, // Rule ID 1292 // 9222 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9223 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w, 9224 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9225 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9226 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9230 // (intrinsic_wo_chain:{ *:[i32] } 3560:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 9231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W_MMR2, 9232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9235 GIR_EraseFromParent, /*InsnID*/0, 9236 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9237 // GIR_Coverage, 1292, 9238 GIR_Done, 9239 // Label 633: @21716 9240 GIM_Try, /*On fail goto*//*Label 634*/ 21768, // Rule ID 1295 // 9241 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9242 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb, 9243 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 9244 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 9245 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 9246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 9249 // (intrinsic_wo_chain:{ *:[v4i8] } 3582:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 9250 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB_MMR2, 9251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9254 GIR_EraseFromParent, /*InsnID*/0, 9255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9256 // GIR_Coverage, 1295, 9257 GIR_Done, 9258 // Label 634: @21768 9259 GIM_Try, /*On fail goto*//*Label 635*/ 21820, // Rule ID 1296 // 9260 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9261 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb, 9262 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 9263 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 9264 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 9265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 9267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 9268 // (intrinsic_wo_chain:{ *:[v4i8] } 3583:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 9269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB_MMR2, 9270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 9272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 9273 GIR_EraseFromParent, /*InsnID*/0, 9274 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9275 // GIR_Coverage, 1296, 9276 GIR_Done, 9277 // Label 635: @21820 9278 GIM_Try, /*On fail goto*//*Label 636*/ 21864, // Rule ID 1833 // 9279 GIM_CheckFeatures, GIFBS_HasDSP, 9280 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_ph, 9281 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9282 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 9283 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 9284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9285 // (intrinsic_wo_chain:{ *:[v2i16] } 2939:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) 9286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_PH, 9287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 9289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b 9290 GIR_EraseFromParent, /*InsnID*/0, 9291 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9292 // GIR_Coverage, 1833, 9293 GIR_Done, 9294 // Label 636: @21864 9295 GIM_Try, /*On fail goto*//*Label 637*/ 21908, // Rule ID 1835 // 9296 GIM_CheckFeatures, GIFBS_HasDSP, 9297 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_ph, 9298 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9299 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 9300 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 9301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9302 // (intrinsic_wo_chain:{ *:[v2i16] } 3555:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) 9303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_PH, 9304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 9306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b 9307 GIR_EraseFromParent, /*InsnID*/0, 9308 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9309 // GIR_Coverage, 1835, 9310 GIR_Done, 9311 // Label 637: @21908 9312 GIM_Try, /*On fail goto*//*Label 638*/ 21952, // Rule ID 1839 // 9313 GIM_CheckFeatures, GIFBS_HasDSP, 9314 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_qb, 9315 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 9316 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 9317 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 9318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9319 // (intrinsic_wo_chain:{ *:[v4i8] } 2960:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) 9320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_QB, 9321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 9323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b 9324 GIR_EraseFromParent, /*InsnID*/0, 9325 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9326 // GIR_Coverage, 1839, 9327 GIR_Done, 9328 // Label 638: @21952 9329 GIM_Try, /*On fail goto*//*Label 639*/ 21996, // Rule ID 1841 // 9330 GIM_CheckFeatures, GIFBS_HasDSP, 9331 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_qb, 9332 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 9333 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 9334 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 9335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9336 // (intrinsic_wo_chain:{ *:[v4i8] } 3579:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) 9337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_QB, 9338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 9340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b 9341 GIR_EraseFromParent, /*InsnID*/0, 9342 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9343 // GIR_Coverage, 1841, 9344 GIR_Done, 9345 // Label 639: @21996 9346 GIM_Reject, 9347 // Label 425: @21997 9348 GIM_Try, /*On fail goto*//*Label 640*/ 25045, 9349 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, 9350 GIM_Try, /*On fail goto*//*Label 641*/ 22073, // Rule ID 449 // 9351 GIM_CheckFeatures, GIFBS_HasDSPR2, 9352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w, 9353 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9354 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9355 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9356 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9360 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9361 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9362 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 9363 // MIs[1] Operand 1 9364 // No operand predicates 9365 GIM_CheckIsSafeToFold, /*InsnID*/1, 9366 // (intrinsic_wo_chain:{ *:[v2i16] } 3461:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) 9367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W, 9368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9370 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 9371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9372 GIR_EraseFromParent, /*InsnID*/0, 9373 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9374 // GIR_Coverage, 449, 9375 GIR_Done, 9376 // Label 641: @22073 9377 GIM_Try, /*On fail goto*//*Label 642*/ 22144, // Rule ID 450 // 9378 GIM_CheckFeatures, GIFBS_HasDSPR2, 9379 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w, 9380 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9381 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9382 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9383 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9387 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9388 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9389 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 9390 // MIs[1] Operand 1 9391 // No operand predicates 9392 GIM_CheckIsSafeToFold, /*InsnID*/1, 9393 // (intrinsic_wo_chain:{ *:[v2i16] } 3462:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) 9394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W, 9395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9397 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 9398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9399 GIR_EraseFromParent, /*InsnID*/0, 9400 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9401 // GIR_Coverage, 450, 9402 GIR_Done, 9403 // Label 642: @22144 9404 GIM_Try, /*On fail goto*//*Label 643*/ 22215, // Rule ID 455 // 9405 GIM_CheckFeatures, GIFBS_HasDSPR2, 9406 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append, 9407 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9408 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9409 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9410 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9414 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9415 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9416 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 9417 // MIs[1] Operand 1 9418 // No operand predicates 9419 GIM_CheckIsSafeToFold, /*InsnID*/1, 9420 // (intrinsic_wo_chain:{ *:[i32] } 2976:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) 9421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND, 9422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9424 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 9425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9426 GIR_EraseFromParent, /*InsnID*/0, 9427 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9428 // GIR_Coverage, 455, 9429 GIR_Done, 9430 // Label 643: @22215 9431 GIM_Try, /*On fail goto*//*Label 644*/ 22286, // Rule ID 456 // 9432 GIM_CheckFeatures, GIFBS_HasDSPR2, 9433 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign, 9434 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9435 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9436 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9437 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9441 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9442 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9443 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2, 9444 // MIs[1] Operand 1 9445 // No operand predicates 9446 GIM_CheckIsSafeToFold, /*InsnID*/1, 9447 // (intrinsic_wo_chain:{ *:[i32] } 3001:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) 9448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN, 9449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9451 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 9452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9453 GIR_EraseFromParent, /*InsnID*/0, 9454 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9455 // GIR_Coverage, 456, 9456 GIR_Done, 9457 // Label 644: @22286 9458 GIM_Try, /*On fail goto*//*Label 645*/ 22357, // Rule ID 457 // 9459 GIM_CheckFeatures, GIFBS_HasDSPR2, 9460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend, 9461 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9462 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9463 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9464 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9468 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9469 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9470 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 9471 // MIs[1] Operand 1 9472 // No operand predicates 9473 GIM_CheckIsSafeToFold, /*InsnID*/1, 9474 // (intrinsic_wo_chain:{ *:[i32] } 3467:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) 9475 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND, 9476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9478 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 9479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9480 GIR_EraseFromParent, /*InsnID*/0, 9481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9482 // GIR_Coverage, 457, 9483 GIR_Done, 9484 // Label 645: @22357 9485 GIM_Try, /*On fail goto*//*Label 646*/ 22428, // Rule ID 921 // 9486 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9487 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_b, 9488 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 9489 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 9490 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 9491 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 9493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 9494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 9495 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9496 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9497 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 9498 // MIs[1] Operand 1 9499 // No operand predicates 9500 GIM_CheckIsSafeToFold, /*InsnID*/1, 9501 // (intrinsic_wo_chain:{ *:[v16i8] } 3499:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$n) 9502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_B, 9503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9506 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n 9507 GIR_EraseFromParent, /*InsnID*/0, 9508 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9509 // GIR_Coverage, 921, 9510 GIR_Done, 9511 // Label 646: @22428 9512 GIM_Try, /*On fail goto*//*Label 647*/ 22499, // Rule ID 922 // 9513 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_h, 9515 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9516 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9517 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9518 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 9520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 9521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 9522 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9523 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9524 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 9525 // MIs[1] Operand 1 9526 // No operand predicates 9527 GIM_CheckIsSafeToFold, /*InsnID*/1, 9528 // (intrinsic_wo_chain:{ *:[v8i16] } 3501:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$n) 9529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_H, 9530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9533 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n 9534 GIR_EraseFromParent, /*InsnID*/0, 9535 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9536 // GIR_Coverage, 922, 9537 GIR_Done, 9538 // Label 647: @22499 9539 GIM_Try, /*On fail goto*//*Label 648*/ 22570, // Rule ID 923 // 9540 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9541 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_w, 9542 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9543 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9544 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9545 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 9547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 9548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 9549 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9550 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9551 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2, 9552 // MIs[1] Operand 1 9553 // No operand predicates 9554 GIM_CheckIsSafeToFold, /*InsnID*/1, 9555 // (intrinsic_wo_chain:{ *:[v4i32] } 3502:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$n) 9556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_W, 9557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9558 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9560 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n 9561 GIR_EraseFromParent, /*InsnID*/0, 9562 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9563 // GIR_Coverage, 923, 9564 GIR_Done, 9565 // Label 648: @22570 9566 GIM_Try, /*On fail goto*//*Label 649*/ 22641, // Rule ID 924 // 9567 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9568 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_d, 9569 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9570 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9571 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9572 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 9574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 9575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 9576 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9577 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9578 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt1, 9579 // MIs[1] Operand 1 9580 // No operand predicates 9581 GIM_CheckIsSafeToFold, /*InsnID*/1, 9582 // (intrinsic_wo_chain:{ *:[v2i64] } 3500:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt1>>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$n) 9583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_D, 9584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9587 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n 9588 GIR_EraseFromParent, /*InsnID*/0, 9589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9590 // GIR_Coverage, 924, 9591 GIR_Done, 9592 // Label 649: @22641 9593 GIM_Try, /*On fail goto*//*Label 650*/ 22712, // Rule ID 1284 // 9594 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9595 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign, 9596 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9597 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9598 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9599 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9603 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9604 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9605 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2, 9606 // MIs[1] Operand 1 9607 // No operand predicates 9608 GIM_CheckIsSafeToFold, /*InsnID*/1, 9609 // (intrinsic_wo_chain:{ *:[i32] } 3001:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src) 9610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN_MMR2, 9611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9613 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp 9614 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9615 GIR_EraseFromParent, /*InsnID*/0, 9616 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9617 // GIR_Coverage, 1284, 9618 GIR_Done, 9619 // Label 650: @22712 9620 GIM_Try, /*On fail goto*//*Label 651*/ 22783, // Rule ID 1306 // 9621 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w, 9623 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9624 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9625 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9626 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9630 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9631 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9632 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 9633 // MIs[1] Operand 1 9634 // No operand predicates 9635 GIM_CheckIsSafeToFold, /*InsnID*/1, 9636 // (intrinsic_wo_chain:{ *:[v2i16] } 3461:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) 9637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W_MMR2, 9638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9640 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 9641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9642 GIR_EraseFromParent, /*InsnID*/0, 9643 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9644 // GIR_Coverage, 1306, 9645 GIR_Done, 9646 // Label 651: @22783 9647 GIM_Try, /*On fail goto*//*Label 652*/ 22854, // Rule ID 1307 // 9648 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9649 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w, 9650 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 9651 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9652 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9653 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 9655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9657 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9658 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9659 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 9660 // MIs[1] Operand 1 9661 // No operand predicates 9662 GIM_CheckIsSafeToFold, /*InsnID*/1, 9663 // (intrinsic_wo_chain:{ *:[v2i16] } 3462:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) 9664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W_MMR2, 9665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9667 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 9668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9669 GIR_EraseFromParent, /*InsnID*/0, 9670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9671 // GIR_Coverage, 1307, 9672 GIR_Done, 9673 // Label 652: @22854 9674 GIM_Try, /*On fail goto*//*Label 653*/ 22925, // Rule ID 1308 // 9675 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9676 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend, 9677 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9678 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9679 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9680 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9684 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9685 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9686 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 9687 // MIs[1] Operand 1 9688 // No operand predicates 9689 GIM_CheckIsSafeToFold, /*InsnID*/1, 9690 // (intrinsic_wo_chain:{ *:[i32] } 3467:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) 9691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND_MMR2, 9692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9694 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 9695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9696 GIR_EraseFromParent, /*InsnID*/0, 9697 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9698 // GIR_Coverage, 1308, 9699 GIR_Done, 9700 // Label 653: @22925 9701 GIM_Try, /*On fail goto*//*Label 654*/ 22996, // Rule ID 1309 // 9702 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 9703 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append, 9704 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9705 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9706 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 9707 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 9708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 9709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 9710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 9711 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 9712 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9713 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 9714 // MIs[1] Operand 1 9715 // No operand predicates 9716 GIM_CheckIsSafeToFold, /*InsnID*/1, 9717 // (intrinsic_wo_chain:{ *:[i32] } 2976:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) 9718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND_MMR2, 9719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 9720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 9721 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 9722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 9723 GIR_EraseFromParent, /*InsnID*/0, 9724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9725 // GIR_Coverage, 1309, 9726 GIR_Done, 9727 // Label 654: @22996 9728 GIM_Try, /*On fail goto*//*Label 655*/ 23060, // Rule ID 520 // 9729 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9730 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_b, 9731 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 9732 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 9733 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 9734 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 9735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 9736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 9737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 9738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, 9739 // (intrinsic_wo_chain:{ *:[v16i8] } 3010:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 9740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_B, 9741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9745 GIR_EraseFromParent, /*InsnID*/0, 9746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9747 // GIR_Coverage, 520, 9748 GIR_Done, 9749 // Label 655: @23060 9750 GIM_Try, /*On fail goto*//*Label 656*/ 23124, // Rule ID 521 // 9751 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9752 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_h, 9753 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9754 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9755 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9756 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 9757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 9758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 9759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 9760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 9761 // (intrinsic_wo_chain:{ *:[v8i16] } 3012:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 9762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_H, 9763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9767 GIR_EraseFromParent, /*InsnID*/0, 9768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9769 // GIR_Coverage, 521, 9770 GIR_Done, 9771 // Label 656: @23124 9772 GIM_Try, /*On fail goto*//*Label 657*/ 23188, // Rule ID 522 // 9773 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_w, 9775 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9777 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9778 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 9780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 9781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 9782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 9783 // (intrinsic_wo_chain:{ *:[v4i32] } 3013:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 9784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_W, 9785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9789 GIR_EraseFromParent, /*InsnID*/0, 9790 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9791 // GIR_Coverage, 522, 9792 GIR_Done, 9793 // Label 657: @23188 9794 GIM_Try, /*On fail goto*//*Label 658*/ 23252, // Rule ID 523 // 9795 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9796 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_d, 9797 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9798 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9799 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9800 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 9801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 9802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 9803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 9804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID, 9805 // (intrinsic_wo_chain:{ *:[v2i64] } 3011:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 9806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_D, 9807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9811 GIR_EraseFromParent, /*InsnID*/0, 9812 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9813 // GIR_Coverage, 523, 9814 GIR_Done, 9815 // Label 658: @23252 9816 GIM_Try, /*On fail goto*//*Label 659*/ 23316, // Rule ID 528 // 9817 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9818 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_b, 9819 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 9820 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 9821 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 9822 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 9823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 9824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 9825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 9826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, 9827 // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 9828 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_B, 9829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9833 GIR_EraseFromParent, /*InsnID*/0, 9834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9835 // GIR_Coverage, 528, 9836 GIR_Done, 9837 // Label 659: @23316 9838 GIM_Try, /*On fail goto*//*Label 660*/ 23380, // Rule ID 529 // 9839 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_h, 9841 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9842 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9843 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9844 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 9845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 9846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 9847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 9848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 9849 // (intrinsic_wo_chain:{ *:[v8i16] } 3020:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 9850 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_H, 9851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9853 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9855 GIR_EraseFromParent, /*InsnID*/0, 9856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9857 // GIR_Coverage, 529, 9858 GIR_Done, 9859 // Label 660: @23380 9860 GIM_Try, /*On fail goto*//*Label 661*/ 23444, // Rule ID 530 // 9861 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9862 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_w, 9863 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9864 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9865 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9866 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 9868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 9869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 9870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 9871 // (intrinsic_wo_chain:{ *:[v4i32] } 3021:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 9872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_W, 9873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9877 GIR_EraseFromParent, /*InsnID*/0, 9878 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9879 // GIR_Coverage, 530, 9880 GIR_Done, 9881 // Label 661: @23444 9882 GIM_Try, /*On fail goto*//*Label 662*/ 23508, // Rule ID 531 // 9883 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9884 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_d, 9885 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9886 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9887 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9888 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 9889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 9890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 9891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 9892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID, 9893 // (intrinsic_wo_chain:{ *:[v2i64] } 3019:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 9894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_D, 9895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9899 GIR_EraseFromParent, /*InsnID*/0, 9900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9901 // GIR_Coverage, 531, 9902 GIR_Done, 9903 // Label 662: @23508 9904 GIM_Try, /*On fail goto*//*Label 663*/ 23572, // Rule ID 626 // 9905 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9906 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_h, 9907 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9908 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9909 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 9910 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 9911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 9912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 9913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 9914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, 9915 // (intrinsic_wo_chain:{ *:[v8i16] } 3139:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 9916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_H, 9917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9921 GIR_EraseFromParent, /*InsnID*/0, 9922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9923 // GIR_Coverage, 626, 9924 GIR_Done, 9925 // Label 663: @23572 9926 GIM_Try, /*On fail goto*//*Label 664*/ 23636, // Rule ID 627 // 9927 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_w, 9929 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9930 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9931 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9932 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 9933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 9934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 9935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 9936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 9937 // (intrinsic_wo_chain:{ *:[v4i32] } 3140:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 9938 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_W, 9939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9943 GIR_EraseFromParent, /*InsnID*/0, 9944 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9945 // GIR_Coverage, 627, 9946 GIR_Done, 9947 // Label 664: @23636 9948 GIM_Try, /*On fail goto*//*Label 665*/ 23700, // Rule ID 628 // 9949 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9950 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_d, 9951 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9952 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9953 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9954 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 9956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 9957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 9958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 9959 // (intrinsic_wo_chain:{ *:[v2i64] } 3138:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 9960 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_D, 9961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9965 GIR_EraseFromParent, /*InsnID*/0, 9966 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9967 // GIR_Coverage, 628, 9968 GIR_Done, 9969 // Label 665: @23700 9970 GIM_Try, /*On fail goto*//*Label 666*/ 23764, // Rule ID 629 // 9971 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9972 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_h, 9973 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9974 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9975 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 9976 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 9977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 9978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 9979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 9980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, 9981 // (intrinsic_wo_chain:{ *:[v8i16] } 3142:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 9982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_H, 9983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 9984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 9985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 9986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 9987 GIR_EraseFromParent, /*InsnID*/0, 9988 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9989 // GIR_Coverage, 629, 9990 GIR_Done, 9991 // Label 666: @23764 9992 GIM_Try, /*On fail goto*//*Label 667*/ 23828, // Rule ID 630 // 9993 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 9994 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_w, 9995 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9996 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9997 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9998 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 9999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 10000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 10001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 10002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 10003 // (intrinsic_wo_chain:{ *:[v4i32] } 3143:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 10004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_W, 10005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10009 GIR_EraseFromParent, /*InsnID*/0, 10010 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10011 // GIR_Coverage, 630, 10012 GIR_Done, 10013 // Label 667: @23828 10014 GIM_Try, /*On fail goto*//*Label 668*/ 23892, // Rule ID 631 // 10015 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10016 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_d, 10017 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10018 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10019 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 10020 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 10021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 10022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 10023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 10024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 10025 // (intrinsic_wo_chain:{ *:[v2i64] } 3141:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 10026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_D, 10027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10031 GIR_EraseFromParent, /*InsnID*/0, 10032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10033 // GIR_Coverage, 631, 10034 GIR_Done, 10035 // Label 668: @23892 10036 GIM_Try, /*On fail goto*//*Label 669*/ 23956, // Rule ID 632 // 10037 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10038 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_h, 10039 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10040 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10041 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 10042 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 10043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 10044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 10045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 10046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, 10047 // (intrinsic_wo_chain:{ *:[v8i16] } 3159:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 10048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_H, 10049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10053 GIR_EraseFromParent, /*InsnID*/0, 10054 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10055 // GIR_Coverage, 632, 10056 GIR_Done, 10057 // Label 669: @23956 10058 GIM_Try, /*On fail goto*//*Label 670*/ 24020, // Rule ID 633 // 10059 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10060 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_w, 10061 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10062 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10063 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10064 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 10065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 10066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 10067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 10068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 10069 // (intrinsic_wo_chain:{ *:[v4i32] } 3160:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 10070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_W, 10071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10075 GIR_EraseFromParent, /*InsnID*/0, 10076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10077 // GIR_Coverage, 633, 10078 GIR_Done, 10079 // Label 670: @24020 10080 GIM_Try, /*On fail goto*//*Label 671*/ 24084, // Rule ID 634 // 10081 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_d, 10083 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10084 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10085 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 10086 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 10087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 10088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 10089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 10090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 10091 // (intrinsic_wo_chain:{ *:[v2i64] } 3158:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 10092 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_D, 10093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10097 GIR_EraseFromParent, /*InsnID*/0, 10098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10099 // GIR_Coverage, 634, 10100 GIR_Done, 10101 // Label 671: @24084 10102 GIM_Try, /*On fail goto*//*Label 672*/ 24148, // Rule ID 635 // 10103 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10104 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_h, 10105 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10106 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10107 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 10108 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 10109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 10110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 10111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 10112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, 10113 // (intrinsic_wo_chain:{ *:[v8i16] } 3162:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 10114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_H, 10115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10119 GIR_EraseFromParent, /*InsnID*/0, 10120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10121 // GIR_Coverage, 635, 10122 GIR_Done, 10123 // Label 672: @24148 10124 GIM_Try, /*On fail goto*//*Label 673*/ 24212, // Rule ID 636 // 10125 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10126 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_w, 10127 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10128 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10129 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10130 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 10131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 10132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 10133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 10134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 10135 // (intrinsic_wo_chain:{ *:[v4i32] } 3163:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 10136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_W, 10137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10141 GIR_EraseFromParent, /*InsnID*/0, 10142 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10143 // GIR_Coverage, 636, 10144 GIR_Done, 10145 // Label 673: @24212 10146 GIM_Try, /*On fail goto*//*Label 674*/ 24276, // Rule ID 637 // 10147 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10148 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_d, 10149 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10150 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10151 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 10152 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 10153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 10154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 10155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 10156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 10157 // (intrinsic_wo_chain:{ *:[v2i64] } 3161:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 10158 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_D, 10159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10163 GIR_EraseFromParent, /*InsnID*/0, 10164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10165 // GIR_Coverage, 637, 10166 GIR_Done, 10167 // Label 674: @24276 10168 GIM_Try, /*On fail goto*//*Label 675*/ 24340, // Rule ID 804 // 10169 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10170 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_h, 10171 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10172 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10173 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10174 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 10175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 10176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 10177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 10178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 10179 // (intrinsic_wo_chain:{ *:[v8i16] } 3327:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 10180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_H, 10181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10185 GIR_EraseFromParent, /*InsnID*/0, 10186 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10187 // GIR_Coverage, 804, 10188 GIR_Done, 10189 // Label 675: @24340 10190 GIM_Try, /*On fail goto*//*Label 676*/ 24404, // Rule ID 805 // 10191 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10192 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_w, 10193 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10194 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10195 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 10196 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 10197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 10198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 10199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 10200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 10201 // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 10202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_W, 10203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10207 GIR_EraseFromParent, /*InsnID*/0, 10208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10209 // GIR_Coverage, 805, 10210 GIR_Done, 10211 // Label 676: @24404 10212 GIM_Try, /*On fail goto*//*Label 677*/ 24468, // Rule ID 806 // 10213 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10214 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_h, 10215 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10216 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10217 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10218 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 10219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 10220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 10221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 10222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 10223 // (intrinsic_wo_chain:{ *:[v8i16] } 3329:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 10224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_H, 10225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10229 GIR_EraseFromParent, /*InsnID*/0, 10230 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10231 // GIR_Coverage, 806, 10232 GIR_Done, 10233 // Label 677: @24468 10234 GIM_Try, /*On fail goto*//*Label 678*/ 24532, // Rule ID 807 // 10235 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10236 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_w, 10237 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10238 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10239 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 10240 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 10241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 10242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 10243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 10244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 10245 // (intrinsic_wo_chain:{ *:[v4i32] } 3330:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 10246 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_W, 10247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10251 GIR_EraseFromParent, /*InsnID*/0, 10252 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10253 // GIR_Coverage, 807, 10254 GIR_Done, 10255 // Label 678: @24532 10256 GIM_Try, /*On fail goto*//*Label 679*/ 24596, // Rule ID 860 // 10257 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10258 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_h, 10259 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10260 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10261 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10262 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 10263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 10264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 10265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 10266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 10267 // (intrinsic_wo_chain:{ *:[v8i16] } 3391:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 10268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_H, 10269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10273 GIR_EraseFromParent, /*InsnID*/0, 10274 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10275 // GIR_Coverage, 860, 10276 GIR_Done, 10277 // Label 679: @24596 10278 GIM_Try, /*On fail goto*//*Label 680*/ 24660, // Rule ID 861 // 10279 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10280 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_w, 10281 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10282 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10283 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 10284 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 10285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 10286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 10287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 10288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 10289 // (intrinsic_wo_chain:{ *:[v4i32] } 3392:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 10290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_W, 10291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10295 GIR_EraseFromParent, /*InsnID*/0, 10296 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10297 // GIR_Coverage, 861, 10298 GIR_Done, 10299 // Label 680: @24660 10300 GIM_Try, /*On fail goto*//*Label 681*/ 24724, // Rule ID 862 // 10301 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10302 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_h, 10303 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10304 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10305 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10306 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 10307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 10308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 10309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 10310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, 10311 // (intrinsic_wo_chain:{ *:[v8i16] } 3393:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 10312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_H, 10313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10317 GIR_EraseFromParent, /*InsnID*/0, 10318 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10319 // GIR_Coverage, 862, 10320 GIR_Done, 10321 // Label 681: @24724 10322 GIM_Try, /*On fail goto*//*Label 682*/ 24788, // Rule ID 863 // 10323 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10324 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_w, 10325 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10326 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10327 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 10328 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 10329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 10330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 10331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 10332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, 10333 // (intrinsic_wo_chain:{ *:[v4i32] } 3394:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 10334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_W, 10335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt 10339 GIR_EraseFromParent, /*InsnID*/0, 10340 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10341 // GIR_Coverage, 863, 10342 GIR_Done, 10343 // Label 682: @24788 10344 GIM_Try, /*On fail goto*//*Label 683*/ 24852, // Rule ID 917 // 10345 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10346 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_b, 10347 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 10348 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10349 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 10350 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 10351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 10352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 10353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, 10354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, 10355 // (intrinsic_wo_chain:{ *:[v16i8] } 3495:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) 10356 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_B, 10357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt 10361 GIR_EraseFromParent, /*InsnID*/0, 10362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10363 // GIR_Coverage, 917, 10364 GIR_Done, 10365 // Label 683: @24852 10366 GIM_Try, /*On fail goto*//*Label 684*/ 24916, // Rule ID 918 // 10367 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10368 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_h, 10369 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10370 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10371 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10372 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 10373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 10374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 10375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, 10376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, 10377 // (intrinsic_wo_chain:{ *:[v8i16] } 3497:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) 10378 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_H, 10379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt 10383 GIR_EraseFromParent, /*InsnID*/0, 10384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10385 // GIR_Coverage, 918, 10386 GIR_Done, 10387 // Label 684: @24916 10388 GIM_Try, /*On fail goto*//*Label 685*/ 24980, // Rule ID 919 // 10389 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10390 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_w, 10391 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10392 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10393 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 10394 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 10395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 10396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 10397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 10398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, 10399 // (intrinsic_wo_chain:{ *:[v4i32] } 3498:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) 10400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_W, 10401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt 10405 GIR_EraseFromParent, /*InsnID*/0, 10406 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10407 // GIR_Coverage, 919, 10408 GIR_Done, 10409 // Label 685: @24980 10410 GIM_Try, /*On fail goto*//*Label 686*/ 25044, // Rule ID 920 // 10411 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 10412 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_d, 10413 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10414 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10415 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 10416 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 10417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 10418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 10419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 10420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, 10421 // (intrinsic_wo_chain:{ *:[v2i64] } 3496:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) 10422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_D, 10423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 10424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in 10425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws 10426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt 10427 GIR_EraseFromParent, /*InsnID*/0, 10428 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10429 // GIR_Coverage, 920, 10430 GIR_Done, 10431 // Label 686: @25044 10432 GIM_Reject, 10433 // Label 640: @25045 10434 GIM_Reject, 10435 // Label 15: @25046 10436 GIM_Try, /*On fail goto*//*Label 687*/ 25079, // Rule ID 326 // 10437 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, 10438 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bposge32, 10439 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 10441 // (intrinsic_w_chain:{ *:[i32] } 3044:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] }) 10442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BPOSGE32_PSEUDO, 10443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10444 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10445 GIR_EraseFromParent, /*InsnID*/0, 10446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10447 // GIR_Coverage, 326, 10448 GIR_Done, 10449 // Label 687: @25079 10450 GIM_Try, /*On fail goto*//*Label 688*/ 25981, 10451 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 10452 GIM_Try, /*On fail goto*//*Label 689*/ 25136, // Rule ID 413 // 10453 GIM_CheckFeatures, GIFBS_HasDSP, 10454 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp, 10455 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10456 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 10458 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 10459 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10460 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt10, 10461 // MIs[1] Operand 1 10462 // No operand predicates 10463 GIM_CheckIsSafeToFold, /*InsnID*/1, 10464 // (intrinsic_w_chain:{ *:[i32] } 3469:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt10>>:$mask) => (RDDSP:{ *:[i32] } (imm:{ *:[i32] }):$mask) 10465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP, 10466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10467 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // mask 10468 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 10469 GIR_EraseFromParent, /*InsnID*/0, 10470 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10471 // GIR_Coverage, 413, 10472 GIR_Done, 10473 // Label 689: @25136 10474 GIM_Try, /*On fail goto*//*Label 690*/ 25188, // Rule ID 414 // 10475 GIM_CheckFeatures, GIFBS_HasDSP_NotInMicroMips, 10476 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp, 10477 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10478 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 10480 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 10481 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10482 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt10, 10483 // MIs[1] Operand 1 10484 // No operand predicates 10485 GIM_CheckIsSafeToFold, /*InsnID*/1, 10486 // (intrinsic_void 3596:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt10>>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$mask) 10487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP, 10488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10489 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // mask 10490 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 10491 GIR_EraseFromParent, /*InsnID*/0, 10492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10493 // GIR_Coverage, 414, 10494 GIR_Done, 10495 // Label 690: @25188 10496 GIM_Try, /*On fail goto*//*Label 691*/ 25232, // Rule ID 335 // 10497 GIM_CheckFeatures, GIFBS_HasDSP, 10498 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph, 10499 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 10500 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 10502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10503 // (intrinsic_w_chain:{ *:[v2i16] } 2932:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt) 10504 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH, 10505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10507 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10508 GIR_EraseFromParent, /*InsnID*/0, 10509 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10510 // GIR_Coverage, 335, 10511 GIR_Done, 10512 // Label 691: @25232 10513 GIM_Try, /*On fail goto*//*Label 692*/ 25276, // Rule ID 336 // 10514 GIM_CheckFeatures, GIFBS_HasDSP, 10515 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w, 10516 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10517 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 10519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 10520 // (intrinsic_w_chain:{ *:[i32] } 2934:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt) 10521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W, 10522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10524 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10525 GIR_EraseFromParent, /*InsnID*/0, 10526 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10527 // GIR_Coverage, 336, 10528 GIR_Done, 10529 // Label 692: @25276 10530 GIM_Try, /*On fail goto*//*Label 693*/ 25320, // Rule ID 422 // 10531 GIM_CheckFeatures, GIFBS_HasDSPR2, 10532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb, 10533 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 10534 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 10535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 10536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10537 // (intrinsic_w_chain:{ *:[v4i8] } 2933:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt) 10538 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB, 10539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10541 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10542 GIR_EraseFromParent, /*InsnID*/0, 10543 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10544 // GIR_Coverage, 422, 10545 GIR_Done, 10546 // Label 693: @25320 10547 GIM_Try, /*On fail goto*//*Label 694*/ 25364, // Rule ID 1187 // 10548 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10549 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph, 10550 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 10551 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 10553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10554 // (intrinsic_w_chain:{ *:[v2i16] } 2932:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs) 10555 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH_MM, 10556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 10557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 10558 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10559 GIR_EraseFromParent, /*InsnID*/0, 10560 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10561 // GIR_Coverage, 1187, 10562 GIR_Done, 10563 // Label 694: @25364 10564 GIM_Try, /*On fail goto*//*Label 695*/ 25408, // Rule ID 1188 // 10565 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10566 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w, 10567 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10568 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 10570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 10571 // (intrinsic_w_chain:{ *:[i32] } 2934:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) 10572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W_MM, 10573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 10574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 10575 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10576 GIR_EraseFromParent, /*InsnID*/0, 10577 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10578 // GIR_Coverage, 1188, 10579 GIR_Done, 10580 // Label 695: @25408 10581 GIM_Try, /*On fail goto*//*Label 696*/ 25452, // Rule ID 1268 // 10582 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 10583 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb, 10584 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 10585 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 10586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 10587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10588 // (intrinsic_w_chain:{ *:[v4i8] } 2933:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs) 10589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB_MMR2, 10590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 10591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 10592 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10593 GIR_EraseFromParent, /*InsnID*/0, 10594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10595 // GIR_Coverage, 1268, 10596 GIR_Done, 10597 // Label 696: @25452 10598 GIM_Try, /*On fail goto*//*Label 697*/ 25496, // Rule ID 389 // 10599 GIM_CheckFeatures, GIFBS_HasDSP, 10600 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb, 10601 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 10602 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 10603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10605 // (intrinsic_void 3110:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 10606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB, 10607 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10609 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10610 GIR_EraseFromParent, /*InsnID*/0, 10611 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10612 // GIR_Coverage, 389, 10613 GIR_Done, 10614 // Label 697: @25496 10615 GIM_Try, /*On fail goto*//*Label 698*/ 25540, // Rule ID 390 // 10616 GIM_CheckFeatures, GIFBS_HasDSP, 10617 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb, 10618 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 10619 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 10620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10622 // (intrinsic_void 3112:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 10623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB, 10624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10626 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10627 GIR_EraseFromParent, /*InsnID*/0, 10628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10629 // GIR_Coverage, 390, 10630 GIR_Done, 10631 // Label 698: @25540 10632 GIM_Try, /*On fail goto*//*Label 699*/ 25584, // Rule ID 391 // 10633 GIM_CheckFeatures, GIFBS_HasDSP, 10634 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb, 10635 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 10636 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 10637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10639 // (intrinsic_void 3111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 10640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB, 10641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10643 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10644 GIR_EraseFromParent, /*InsnID*/0, 10645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10646 // GIR_Coverage, 391, 10647 GIR_Done, 10648 // Label 699: @25584 10649 GIM_Try, /*On fail goto*//*Label 700*/ 25628, // Rule ID 395 // 10650 GIM_CheckFeatures, GIFBS_HasDSP, 10651 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph, 10652 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 10653 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10656 // (intrinsic_void 3101:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 10657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH, 10658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10660 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10661 GIR_EraseFromParent, /*InsnID*/0, 10662 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10663 // GIR_Coverage, 395, 10664 GIR_Done, 10665 // Label 700: @25628 10666 GIM_Try, /*On fail goto*//*Label 701*/ 25672, // Rule ID 396 // 10667 GIM_CheckFeatures, GIFBS_HasDSP, 10668 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph, 10669 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 10670 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10673 // (intrinsic_void 3103:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 10674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH, 10675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10677 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10678 GIR_EraseFromParent, /*InsnID*/0, 10679 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10680 // GIR_Coverage, 396, 10681 GIR_Done, 10682 // Label 701: @25672 10683 GIM_Try, /*On fail goto*//*Label 702*/ 25716, // Rule ID 397 // 10684 GIM_CheckFeatures, GIFBS_HasDSP, 10685 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph, 10686 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 10687 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10690 // (intrinsic_void 3102:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 10691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH, 10692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10694 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10695 GIR_EraseFromParent, /*InsnID*/0, 10696 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10697 // GIR_Coverage, 397, 10698 GIR_Done, 10699 // Label 702: @25716 10700 GIM_Try, /*On fail goto*//*Label 703*/ 25760, // Rule ID 1259 // 10701 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10702 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph, 10703 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 10704 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10707 // (intrinsic_void 3101:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 10708 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH_MM, 10709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10711 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10712 GIR_EraseFromParent, /*InsnID*/0, 10713 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10714 // GIR_Coverage, 1259, 10715 GIR_Done, 10716 // Label 703: @25760 10717 GIM_Try, /*On fail goto*//*Label 704*/ 25804, // Rule ID 1260 // 10718 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10719 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph, 10720 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 10721 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10724 // (intrinsic_void 3103:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 10725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH_MM, 10726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10728 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10729 GIR_EraseFromParent, /*InsnID*/0, 10730 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10731 // GIR_Coverage, 1260, 10732 GIR_Done, 10733 // Label 704: @25804 10734 GIM_Try, /*On fail goto*//*Label 705*/ 25848, // Rule ID 1261 // 10735 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10736 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph, 10737 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, 10738 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10741 // (intrinsic_void 3102:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 10742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH_MM, 10743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10745 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10746 GIR_EraseFromParent, /*InsnID*/0, 10747 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10748 // GIR_Coverage, 1261, 10749 GIR_Done, 10750 // Label 705: @25848 10751 GIM_Try, /*On fail goto*//*Label 706*/ 25892, // Rule ID 1265 // 10752 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10753 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb, 10754 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 10755 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 10756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10758 // (intrinsic_void 3110:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 10759 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB_MM, 10760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10762 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10763 GIR_EraseFromParent, /*InsnID*/0, 10764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10765 // GIR_Coverage, 1265, 10766 GIR_Done, 10767 // Label 706: @25892 10768 GIM_Try, /*On fail goto*//*Label 707*/ 25936, // Rule ID 1266 // 10769 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10770 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb, 10771 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 10772 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 10773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10775 // (intrinsic_void 3112:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 10776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB_MM, 10777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10779 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10780 GIR_EraseFromParent, /*InsnID*/0, 10781 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10782 // GIR_Coverage, 1266, 10783 GIR_Done, 10784 // Label 707: @25936 10785 GIM_Try, /*On fail goto*//*Label 708*/ 25980, // Rule ID 1267 // 10786 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10787 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb, 10788 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, 10789 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 10790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, 10791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10792 // (intrinsic_void 3111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 10793 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB_MM, 10794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs 10795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10796 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10797 GIR_EraseFromParent, /*InsnID*/0, 10798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10799 // GIR_Coverage, 1267, 10800 GIR_Done, 10801 // Label 708: @25980 10802 GIM_Reject, 10803 // Label 688: @25981 10804 GIM_Try, /*On fail goto*//*Label 709*/ 29969, 10805 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, 10806 GIM_Try, /*On fail goto*//*Label 710*/ 26050, // Rule ID 354 // 10807 GIM_CheckFeatures, GIFBS_HasDSP, 10808 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, 10809 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 10810 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10811 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 10813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10814 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10815 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10816 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 10817 // MIs[1] Operand 1 10818 // No operand predicates 10819 GIM_CheckIsSafeToFold, /*InsnID*/1, 10820 // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa) 10821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH, 10822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10824 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa 10825 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 10826 GIR_EraseFromParent, /*InsnID*/0, 10827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10828 // GIR_Coverage, 354, 10829 GIR_Done, 10830 // Label 710: @26050 10831 GIM_Try, /*On fail goto*//*Label 711*/ 26114, // Rule ID 359 // 10832 GIM_CheckFeatures, GIFBS_HasDSP, 10833 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, 10834 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10835 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10836 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 10838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 10839 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10840 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10841 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 10842 // MIs[1] Operand 1 10843 // No operand predicates 10844 GIM_CheckIsSafeToFold, /*InsnID*/1, 10845 // (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa) 10846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W, 10847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 10849 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa 10850 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 10851 GIR_EraseFromParent, /*InsnID*/0, 10852 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10853 // GIR_Coverage, 359, 10854 GIR_Done, 10855 // Label 711: @26114 10856 GIM_Try, /*On fail goto*//*Label 712*/ 26178, // Rule ID 1196 // 10857 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10858 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, 10859 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 10860 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10861 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 10863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 10864 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10865 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10866 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 10867 // MIs[1] Operand 1 10868 // No operand predicates 10869 GIM_CheckIsSafeToFold, /*InsnID*/1, 10870 // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa) 10871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH_MM, 10872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 10873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 10874 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 10875 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 10876 GIR_EraseFromParent, /*InsnID*/0, 10877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10878 // GIR_Coverage, 1196, 10879 GIR_Done, 10880 // Label 712: @26178 10881 GIM_Try, /*On fail goto*//*Label 713*/ 26242, // Rule ID 1201 // 10882 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 10883 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, 10884 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10885 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10886 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 10888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 10889 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10890 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10891 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 10892 // MIs[1] Operand 1 10893 // No operand predicates 10894 GIM_CheckIsSafeToFold, /*InsnID*/1, 10895 // (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa) 10896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W_MM, 10897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 10898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 10899 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa 10900 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 10901 GIR_EraseFromParent, /*InsnID*/0, 10902 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10903 // GIR_Coverage, 1201, 10904 GIR_Done, 10905 // Label 713: @26242 10906 GIM_Try, /*On fail goto*//*Label 714*/ 26297, // Rule ID 1850 // 10907 GIM_CheckFeatures, GIFBS_HasDSP, 10908 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph, 10909 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 10910 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 10911 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 10913 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10914 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10915 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4, 10916 // MIs[1] Operand 1 10917 // No operand predicates 10918 GIM_CheckIsSafeToFold, /*InsnID*/1, 10919 // (intrinsic_w_chain:{ *:[v2i16] } 3484:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) 10920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_PH, 10921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 10923 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 10924 GIR_EraseFromParent, /*InsnID*/0, 10925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10926 // GIR_Coverage, 1850, 10927 GIR_Done, 10928 // Label 714: @26297 10929 GIM_Try, /*On fail goto*//*Label 715*/ 26352, // Rule ID 1856 // 10930 GIM_CheckFeatures, GIFBS_HasDSP, 10931 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb, 10932 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 10933 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 10934 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 10936 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10937 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10938 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3, 10939 // MIs[1] Operand 1 10940 // No operand predicates 10941 GIM_CheckIsSafeToFold, /*InsnID*/1, 10942 // (intrinsic_w_chain:{ *:[v4i8] } 3485:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) 10943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_QB, 10944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 10946 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 10947 GIR_EraseFromParent, /*InsnID*/0, 10948 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10949 // GIR_Coverage, 1856, 10950 GIR_Done, 10951 // Label 715: @26352 10952 GIM_Try, /*On fail goto*//*Label 716*/ 26408, // Rule ID 331 // 10953 GIM_CheckFeatures, GIFBS_HasDSP, 10954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w, 10955 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10956 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10957 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 10959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 10960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 10961 // (intrinsic_w_chain:{ *:[i32] } 2941:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 10962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W, 10963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 10965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 10966 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10967 GIR_EraseFromParent, /*InsnID*/0, 10968 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10969 // GIR_Coverage, 331, 10970 GIR_Done, 10971 // Label 716: @26408 10972 GIM_Try, /*On fail goto*//*Label 717*/ 26464, // Rule ID 332 // 10973 GIM_CheckFeatures, GIFBS_HasDSP, 10974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w, 10975 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10976 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10977 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 10979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 10980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 10981 // (intrinsic_w_chain:{ *:[i32] } 3557:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 10982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W, 10983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 10985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 10986 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10987 GIR_EraseFromParent, /*InsnID*/0, 10988 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10989 // GIR_Coverage, 332, 10990 GIR_Done, 10991 // Label 717: @26464 10992 GIM_Try, /*On fail goto*//*Label 718*/ 26520, // Rule ID 339 // 10993 GIM_CheckFeatures, GIFBS_HasDSP, 10994 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w, 10995 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 10996 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10997 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 10999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11001 // (intrinsic_w_chain:{ *:[v2i16] } 3465:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 11002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W, 11003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11006 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11007 GIR_EraseFromParent, /*InsnID*/0, 11008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11009 // GIR_Coverage, 339, 11010 GIR_Done, 11011 // Label 718: @26520 11012 GIM_Try, /*On fail goto*//*Label 719*/ 26576, // Rule ID 340 // 11013 GIM_CheckFeatures, GIFBS_HasDSP, 11014 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph, 11015 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 11016 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11017 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11021 // (intrinsic_w_chain:{ *:[v4i8] } 3466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH, 11023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11026 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11027 GIR_EraseFromParent, /*InsnID*/0, 11028 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11029 // GIR_Coverage, 340, 11030 GIR_Done, 11031 // Label 719: @26576 11032 GIM_Try, /*On fail goto*//*Label 720*/ 26632, // Rule ID 351 // 11033 GIM_CheckFeatures, GIFBS_HasDSP, 11034 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb, 11035 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 11036 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11037 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11041 // (intrinsic_w_chain:{ *:[v4i8] } 3485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 11042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB, 11043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 11045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 11046 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11047 GIR_EraseFromParent, /*InsnID*/0, 11048 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11049 // GIR_Coverage, 351, 11050 GIR_Done, 11051 // Label 720: @26632 11052 GIM_Try, /*On fail goto*//*Label 721*/ 26688, // Rule ID 353 // 11053 GIM_CheckFeatures, GIFBS_HasDSP, 11054 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph, 11055 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11056 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11057 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11061 // (intrinsic_w_chain:{ *:[v2i16] } 3484:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 11062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH, 11063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 11065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 11066 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11067 GIR_EraseFromParent, /*InsnID*/0, 11068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11069 // GIR_Coverage, 353, 11070 GIR_Done, 11071 // Label 721: @26688 11072 GIM_Try, /*On fail goto*//*Label 722*/ 26744, // Rule ID 355 // 11073 GIM_CheckFeatures, GIFBS_HasDSP, 11074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, 11075 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11076 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11077 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11081 // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 11082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH, 11083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 11085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 11086 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11087 GIR_EraseFromParent, /*InsnID*/0, 11088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11089 // GIR_Coverage, 355, 11090 GIR_Done, 11091 // Label 722: @26744 11092 GIM_Try, /*On fail goto*//*Label 723*/ 26800, // Rule ID 360 // 11093 GIM_CheckFeatures, GIFBS_HasDSP, 11094 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, 11095 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11096 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11097 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11101 // (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) 11102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W, 11103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 11105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa 11106 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11107 GIR_EraseFromParent, /*InsnID*/0, 11108 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11109 // GIR_Coverage, 360, 11110 GIR_Done, 11111 // Label 723: @26800 11112 GIM_Try, /*On fail goto*//*Label 724*/ 26856, // Rule ID 363 // 11113 GIM_CheckFeatures, GIFBS_HasDSP, 11114 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl, 11115 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11116 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11117 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11121 // (intrinsic_w_chain:{ *:[v2i16] } 3407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL, 11123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11126 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11127 GIR_EraseFromParent, /*InsnID*/0, 11128 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11129 // GIR_Coverage, 363, 11130 GIR_Done, 11131 // Label 724: @26856 11132 GIM_Try, /*On fail goto*//*Label 725*/ 26912, // Rule ID 364 // 11133 GIM_CheckFeatures, GIFBS_HasDSP, 11134 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr, 11135 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11136 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11137 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11141 // (intrinsic_w_chain:{ *:[v2i16] } 3408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR, 11143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11146 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11147 GIR_EraseFromParent, /*InsnID*/0, 11148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11149 // GIR_Coverage, 364, 11150 GIR_Done, 11151 // Label 725: @26912 11152 GIM_Try, /*On fail goto*//*Label 726*/ 26968, // Rule ID 365 // 11153 GIM_CheckFeatures, GIFBS_HasDSP, 11154 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl, 11155 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11156 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11157 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11161 // (intrinsic_w_chain:{ *:[i32] } 3405:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL, 11163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11166 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11167 GIR_EraseFromParent, /*InsnID*/0, 11168 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11169 // GIR_Coverage, 365, 11170 GIR_Done, 11171 // Label 726: @26968 11172 GIM_Try, /*On fail goto*//*Label 727*/ 27024, // Rule ID 366 // 11173 GIM_CheckFeatures, GIFBS_HasDSP, 11174 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr, 11175 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11176 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11177 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11181 // (intrinsic_w_chain:{ *:[i32] } 3406:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR, 11183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11186 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11187 GIR_EraseFromParent, /*InsnID*/0, 11188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11189 // GIR_Coverage, 366, 11190 GIR_Done, 11191 // Label 727: @27024 11192 GIM_Try, /*On fail goto*//*Label 728*/ 27080, // Rule ID 367 // 11193 GIM_CheckFeatures, GIFBS_HasDSP, 11194 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph, 11195 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11196 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11197 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11201 // (intrinsic_w_chain:{ *:[v2i16] } 3409:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH, 11203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11206 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11207 GIR_EraseFromParent, /*InsnID*/0, 11208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11209 // GIR_Coverage, 367, 11210 GIR_Done, 11211 // Label 728: @27080 11212 GIM_Try, /*On fail goto*//*Label 729*/ 27136, // Rule ID 392 // 11213 GIM_CheckFeatures, GIFBS_HasDSP, 11214 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb, 11215 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11216 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11217 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11221 // (intrinsic_w_chain:{ *:[i32] } 3107:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB, 11223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11226 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11227 GIR_EraseFromParent, /*InsnID*/0, 11228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11229 // GIR_Coverage, 392, 11230 GIR_Done, 11231 // Label 729: @27136 11232 GIM_Try, /*On fail goto*//*Label 730*/ 27192, // Rule ID 393 // 11233 GIM_CheckFeatures, GIFBS_HasDSP, 11234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb, 11235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11237 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11241 // (intrinsic_w_chain:{ *:[i32] } 3109:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB, 11243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11246 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11247 GIR_EraseFromParent, /*InsnID*/0, 11248 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11249 // GIR_Coverage, 393, 11250 GIR_Done, 11251 // Label 730: @27192 11252 GIM_Try, /*On fail goto*//*Label 731*/ 27248, // Rule ID 394 // 11253 GIM_CheckFeatures, GIFBS_HasDSP, 11254 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb, 11255 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11256 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11257 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11261 // (intrinsic_w_chain:{ *:[i32] } 3108:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB, 11263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11266 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11267 GIR_EraseFromParent, /*InsnID*/0, 11268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11269 // GIR_Coverage, 394, 11270 GIR_Done, 11271 // Label 731: @27248 11272 GIM_Try, /*On fail goto*//*Label 732*/ 27304, // Rule ID 404 // 11273 GIM_CheckFeatures, GIFBS_HasDSP, 11274 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb, 11275 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 11276 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11277 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11281 // (intrinsic_w_chain:{ *:[v4i8] } 3449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB, 11283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11286 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11287 GIR_EraseFromParent, /*InsnID*/0, 11288 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11289 // GIR_Coverage, 404, 11290 GIR_Done, 11291 // Label 732: @27304 11292 GIM_Try, /*On fail goto*//*Label 733*/ 27360, // Rule ID 405 // 11293 GIM_CheckFeatures, GIFBS_HasDSP, 11294 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph, 11295 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11296 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11297 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11301 // (intrinsic_w_chain:{ *:[v2i16] } 3448:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH, 11303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11306 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11307 GIR_EraseFromParent, /*InsnID*/0, 11308 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11309 // GIR_Coverage, 405, 11310 GIR_Done, 11311 // Label 733: @27360 11312 GIM_Try, /*On fail goto*//*Label 734*/ 27416, // Rule ID 409 // 11313 GIM_CheckFeatures, GIFBS_HasDSP, 11314 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv, 11315 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11316 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11317 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11321 // (intrinsic_w_chain:{ *:[i32] } 3309:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) 11322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV, 11323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 11324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 11325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 11326 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11327 GIR_EraseFromParent, /*InsnID*/0, 11328 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11329 // GIR_Coverage, 409, 11330 GIR_Done, 11331 // Label 734: @27416 11332 GIM_Try, /*On fail goto*//*Label 735*/ 27472, // Rule ID 415 // 11333 GIM_CheckFeatures, GIFBS_HasDSPR2, 11334 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph, 11335 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11336 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11337 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11341 // (intrinsic_w_chain:{ *:[v2i16] } 2959:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH, 11343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11346 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11347 GIR_EraseFromParent, /*InsnID*/0, 11348 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11349 // GIR_Coverage, 415, 11350 GIR_Done, 11351 // Label 735: @27472 11352 GIM_Try, /*On fail goto*//*Label 736*/ 27528, // Rule ID 416 // 11353 GIM_CheckFeatures, GIFBS_HasDSPR2, 11354 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph, 11355 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11356 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11357 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11361 // (intrinsic_w_chain:{ *:[v2i16] } 2961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH, 11363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11366 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11367 GIR_EraseFromParent, /*InsnID*/0, 11368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11369 // GIR_Coverage, 416, 11370 GIR_Done, 11371 // Label 736: @27528 11372 GIM_Try, /*On fail goto*//*Label 737*/ 27584, // Rule ID 417 // 11373 GIM_CheckFeatures, GIFBS_HasDSPR2, 11374 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph, 11375 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11376 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11377 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11381 // (intrinsic_w_chain:{ *:[v2i16] } 3578:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11382 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH, 11383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11386 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11387 GIR_EraseFromParent, /*InsnID*/0, 11388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11389 // GIR_Coverage, 417, 11390 GIR_Done, 11391 // Label 737: @27584 11392 GIM_Try, /*On fail goto*//*Label 738*/ 27640, // Rule ID 418 // 11393 GIM_CheckFeatures, GIFBS_HasDSPR2, 11394 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph, 11395 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11396 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11397 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11401 // (intrinsic_w_chain:{ *:[v2i16] } 3580:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH, 11403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11406 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11407 GIR_EraseFromParent, /*InsnID*/0, 11408 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11409 // GIR_Coverage, 418, 11410 GIR_Done, 11411 // Label 738: @27640 11412 GIM_Try, /*On fail goto*//*Label 739*/ 27696, // Rule ID 419 // 11413 GIM_CheckFeatures, GIFBS_HasDSPR2, 11414 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb, 11415 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11416 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11417 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11421 // (intrinsic_w_chain:{ *:[i32] } 3104:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB, 11423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11426 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11427 GIR_EraseFromParent, /*InsnID*/0, 11428 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11429 // GIR_Coverage, 419, 11430 GIR_Done, 11431 // Label 739: @27696 11432 GIM_Try, /*On fail goto*//*Label 740*/ 27752, // Rule ID 420 // 11433 GIM_CheckFeatures, GIFBS_HasDSPR2, 11434 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb, 11435 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11436 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11437 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11441 // (intrinsic_w_chain:{ *:[i32] } 3106:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB, 11443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11446 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11447 GIR_EraseFromParent, /*InsnID*/0, 11448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11449 // GIR_Coverage, 420, 11450 GIR_Done, 11451 // Label 740: @27752 11452 GIM_Try, /*On fail goto*//*Label 741*/ 27808, // Rule ID 421 // 11453 GIM_CheckFeatures, GIFBS_HasDSPR2, 11454 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb, 11455 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11456 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11457 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11461 // (intrinsic_w_chain:{ *:[i32] } 3105:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB, 11463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11466 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11467 GIR_EraseFromParent, /*InsnID*/0, 11468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11469 // GIR_Coverage, 421, 11470 GIR_Done, 11471 // Label 741: @27808 11472 GIM_Try, /*On fail goto*//*Label 742*/ 27864, // Rule ID 435 // 11473 GIM_CheckFeatures, GIFBS_HasDSPR2, 11474 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph, 11475 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11476 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11477 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11481 // (intrinsic_w_chain:{ *:[v2i16] } 3404:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH, 11483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11486 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11487 GIR_EraseFromParent, /*InsnID*/0, 11488 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11489 // GIR_Coverage, 435, 11490 GIR_Done, 11491 // Label 742: @27864 11492 GIM_Try, /*On fail goto*//*Label 743*/ 27920, // Rule ID 436 // 11493 GIM_CheckFeatures, GIFBS_HasDSPR2, 11494 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w, 11495 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11496 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11497 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11501 // (intrinsic_w_chain:{ *:[i32] } 3412:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 11502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W, 11503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11506 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11507 GIR_EraseFromParent, /*InsnID*/0, 11508 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11509 // GIR_Coverage, 436, 11510 GIR_Done, 11511 // Label 743: @27920 11512 GIM_Try, /*On fail goto*//*Label 744*/ 27976, // Rule ID 437 // 11513 GIM_CheckFeatures, GIFBS_HasDSPR2, 11514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w, 11515 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11516 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11517 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11521 // (intrinsic_w_chain:{ *:[i32] } 3410:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 11522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W, 11523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11526 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11527 GIR_EraseFromParent, /*InsnID*/0, 11528 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11529 // GIR_Coverage, 437, 11530 GIR_Done, 11531 // Label 744: @27976 11532 GIM_Try, /*On fail goto*//*Label 745*/ 28032, // Rule ID 438 // 11533 GIM_CheckFeatures, GIFBS_HasDSPR2, 11534 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph, 11535 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11536 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11537 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11541 // (intrinsic_w_chain:{ *:[v2i16] } 3411:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH, 11543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11546 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11547 GIR_EraseFromParent, /*InsnID*/0, 11548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11549 // GIR_Coverage, 438, 11550 GIR_Done, 11551 // Label 745: @28032 11552 GIM_Try, /*On fail goto*//*Label 746*/ 28088, // Rule ID 448 // 11553 GIM_CheckFeatures, GIFBS_HasDSPR2, 11554 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph, 11555 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 11556 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11557 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11561 // (intrinsic_w_chain:{ *:[v4i8] } 3460:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH, 11563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11566 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11567 GIR_EraseFromParent, /*InsnID*/0, 11568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11569 // GIR_Coverage, 448, 11570 GIR_Done, 11571 // Label 746: @28088 11572 GIM_Try, /*On fail goto*//*Label 747*/ 28144, // Rule ID 1181 // 11573 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11574 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w, 11575 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11576 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11577 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11581 // (intrinsic_w_chain:{ *:[i32] } 2941:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 11582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W_MM, 11583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11586 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11587 GIR_EraseFromParent, /*InsnID*/0, 11588 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11589 // GIR_Coverage, 1181, 11590 GIR_Done, 11591 // Label 747: @28144 11592 GIM_Try, /*On fail goto*//*Label 748*/ 28200, // Rule ID 1189 // 11593 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11594 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv, 11595 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11596 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11597 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11601 // (intrinsic_w_chain:{ *:[i32] } 3309:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) 11602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV_MM, 11603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 11604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 11605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 11606 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11607 GIR_EraseFromParent, /*InsnID*/0, 11608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11609 // GIR_Coverage, 1189, 11610 GIR_Done, 11611 // Label 748: @28200 11612 GIM_Try, /*On fail goto*//*Label 749*/ 28256, // Rule ID 1197 // 11613 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11614 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph, 11615 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11616 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11617 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11621 // (intrinsic_w_chain:{ *:[v2i16] } 3484:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 11622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH_MM, 11623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 11625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 11626 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11627 GIR_EraseFromParent, /*InsnID*/0, 11628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11629 // GIR_Coverage, 1197, 11630 GIR_Done, 11631 // Label 749: @28256 11632 GIM_Try, /*On fail goto*//*Label 750*/ 28312, // Rule ID 1198 // 11633 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11634 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, 11635 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11636 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11637 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11641 // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 11642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH_MM, 11643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 11645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 11646 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11647 GIR_EraseFromParent, /*InsnID*/0, 11648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11649 // GIR_Coverage, 1198, 11650 GIR_Done, 11651 // Label 750: @28312 11652 GIM_Try, /*On fail goto*//*Label 751*/ 28368, // Rule ID 1199 // 11653 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11654 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb, 11655 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 11656 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11657 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11661 // (intrinsic_w_chain:{ *:[v4i8] } 3485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 11662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB_MM, 11663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 11665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 11666 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11667 GIR_EraseFromParent, /*InsnID*/0, 11668 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11669 // GIR_Coverage, 1199, 11670 GIR_Done, 11671 // Label 751: @28368 11672 GIM_Try, /*On fail goto*//*Label 752*/ 28424, // Rule ID 1200 // 11673 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11674 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, 11675 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11676 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11677 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11681 // (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 11682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W_MM, 11683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt 11685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs 11686 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11687 GIR_EraseFromParent, /*InsnID*/0, 11688 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11689 // GIR_Coverage, 1200, 11690 GIR_Done, 11691 // Label 752: @28424 11692 GIM_Try, /*On fail goto*//*Label 753*/ 28480, // Rule ID 1219 // 11693 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11694 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w, 11695 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11696 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11697 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11701 // (intrinsic_w_chain:{ *:[i32] } 3557:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 11702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W_MM, 11703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11706 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11707 GIR_EraseFromParent, /*InsnID*/0, 11708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11709 // GIR_Coverage, 1219, 11710 GIR_Done, 11711 // Label 753: @28480 11712 GIM_Try, /*On fail goto*//*Label 754*/ 28536, // Rule ID 1225 // 11713 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11714 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl, 11715 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11716 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11717 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11721 // (intrinsic_w_chain:{ *:[i32] } 3405:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL_MM, 11723 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11726 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11727 GIR_EraseFromParent, /*InsnID*/0, 11728 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11729 // GIR_Coverage, 1225, 11730 GIR_Done, 11731 // Label 754: @28536 11732 GIM_Try, /*On fail goto*//*Label 755*/ 28592, // Rule ID 1226 // 11733 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11734 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr, 11735 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11736 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11737 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11741 // (intrinsic_w_chain:{ *:[i32] } 3406:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR_MM, 11743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11746 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11747 GIR_EraseFromParent, /*InsnID*/0, 11748 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11749 // GIR_Coverage, 1226, 11750 GIR_Done, 11751 // Label 755: @28592 11752 GIM_Try, /*On fail goto*//*Label 756*/ 28648, // Rule ID 1227 // 11753 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11754 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl, 11755 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11756 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11757 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11761 // (intrinsic_w_chain:{ *:[v2i16] } 3407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL_MM, 11763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11766 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11767 GIR_EraseFromParent, /*InsnID*/0, 11768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11769 // GIR_Coverage, 1227, 11770 GIR_Done, 11771 // Label 756: @28648 11772 GIM_Try, /*On fail goto*//*Label 757*/ 28704, // Rule ID 1228 // 11773 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr, 11775 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11777 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11781 // (intrinsic_w_chain:{ *:[v2i16] } 3408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR_MM, 11783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11786 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11787 GIR_EraseFromParent, /*InsnID*/0, 11788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11789 // GIR_Coverage, 1228, 11790 GIR_Done, 11791 // Label 757: @28704 11792 GIM_Try, /*On fail goto*//*Label 758*/ 28760, // Rule ID 1229 // 11793 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph, 11795 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11796 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11797 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11801 // (intrinsic_w_chain:{ *:[v2i16] } 3409:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH_MM, 11803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11806 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11807 GIR_EraseFromParent, /*InsnID*/0, 11808 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11809 // GIR_Coverage, 1229, 11810 GIR_Done, 11811 // Label 758: @28760 11812 GIM_Try, /*On fail goto*//*Label 759*/ 28816, // Rule ID 1232 // 11813 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11814 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph, 11815 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 11816 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11817 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11821 // (intrinsic_w_chain:{ *:[v4i8] } 3466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH_MM, 11823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11826 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11827 GIR_EraseFromParent, /*InsnID*/0, 11828 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11829 // GIR_Coverage, 1232, 11830 GIR_Done, 11831 // Label 759: @28816 11832 GIM_Try, /*On fail goto*//*Label 760*/ 28872, // Rule ID 1233 // 11833 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11834 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w, 11835 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11836 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11837 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 11840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 11841 // (intrinsic_w_chain:{ *:[v2i16] } 3465:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 11842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W_MM, 11843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11846 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11847 GIR_EraseFromParent, /*InsnID*/0, 11848 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11849 // GIR_Coverage, 1233, 11850 GIR_Done, 11851 // Label 760: @28872 11852 GIM_Try, /*On fail goto*//*Label 761*/ 28928, // Rule ID 1251 // 11853 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11854 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph, 11855 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11856 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11857 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11861 // (intrinsic_w_chain:{ *:[v2i16] } 3448:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH_MM, 11863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11866 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11867 GIR_EraseFromParent, /*InsnID*/0, 11868 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11869 // GIR_Coverage, 1251, 11870 GIR_Done, 11871 // Label 761: @28928 11872 GIM_Try, /*On fail goto*//*Label 762*/ 28984, // Rule ID 1252 // 11873 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11874 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb, 11875 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 11876 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11877 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11881 // (intrinsic_w_chain:{ *:[v4i8] } 3449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB_MM, 11883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11886 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11887 GIR_EraseFromParent, /*InsnID*/0, 11888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11889 // GIR_Coverage, 1252, 11890 GIR_Done, 11891 // Label 762: @28984 11892 GIM_Try, /*On fail goto*//*Label 763*/ 29040, // Rule ID 1262 // 11893 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb, 11895 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11896 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11897 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11901 // (intrinsic_w_chain:{ *:[i32] } 3107:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB_MM, 11903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11906 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11907 GIR_EraseFromParent, /*InsnID*/0, 11908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11909 // GIR_Coverage, 1262, 11910 GIR_Done, 11911 // Label 763: @29040 11912 GIM_Try, /*On fail goto*//*Label 764*/ 29096, // Rule ID 1263 // 11913 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11914 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb, 11915 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11916 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11917 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11921 // (intrinsic_w_chain:{ *:[i32] } 3109:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB_MM, 11923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11926 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11927 GIR_EraseFromParent, /*InsnID*/0, 11928 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11929 // GIR_Coverage, 1263, 11930 GIR_Done, 11931 // Label 764: @29096 11932 GIM_Try, /*On fail goto*//*Label 765*/ 29152, // Rule ID 1264 // 11933 GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, 11934 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb, 11935 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11936 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11937 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11941 // (intrinsic_w_chain:{ *:[i32] } 3108:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 11942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB_MM, 11943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11946 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11947 GIR_EraseFromParent, /*InsnID*/0, 11948 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11949 // GIR_Coverage, 1264, 11950 GIR_Done, 11951 // Label 765: @29152 11952 GIM_Try, /*On fail goto*//*Label 766*/ 29208, // Rule ID 1273 // 11953 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 11954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph, 11955 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11956 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11957 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11961 // (intrinsic_w_chain:{ *:[v2i16] } 2959:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH_MMR2, 11963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11966 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11967 GIR_EraseFromParent, /*InsnID*/0, 11968 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11969 // GIR_Coverage, 1273, 11970 GIR_Done, 11971 // Label 766: @29208 11972 GIM_Try, /*On fail goto*//*Label 767*/ 29264, // Rule ID 1274 // 11973 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 11974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph, 11975 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 11976 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 11977 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 11978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 11979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 11980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 11981 // (intrinsic_w_chain:{ *:[v2i16] } 2961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 11982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH_MMR2, 11983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 11985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 11986 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11987 GIR_EraseFromParent, /*InsnID*/0, 11988 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11989 // GIR_Coverage, 1274, 11990 GIR_Done, 11991 // Label 767: @29264 11992 GIM_Try, /*On fail goto*//*Label 768*/ 29320, // Rule ID 1285 // 11993 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 11994 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb, 11995 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11996 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 11997 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 11998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 11999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 12000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 12001 // (intrinsic_w_chain:{ *:[i32] } 3104:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 12002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB_MMR2, 12003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12006 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12007 GIR_EraseFromParent, /*InsnID*/0, 12008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12009 // GIR_Coverage, 1285, 12010 GIR_Done, 12011 // Label 768: @29320 12012 GIM_Try, /*On fail goto*//*Label 769*/ 29376, // Rule ID 1286 // 12013 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 12014 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb, 12015 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12016 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 12017 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 12018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 12020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 12021 // (intrinsic_w_chain:{ *:[i32] } 3106:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 12022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB_MMR2, 12023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12026 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12027 GIR_EraseFromParent, /*InsnID*/0, 12028 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12029 // GIR_Coverage, 1286, 12030 GIR_Done, 12031 // Label 769: @29376 12032 GIM_Try, /*On fail goto*//*Label 770*/ 29432, // Rule ID 1287 // 12033 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 12034 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb, 12035 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12036 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, 12037 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, 12038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 12040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 12041 // (intrinsic_w_chain:{ *:[i32] } 3105:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) 12042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB_MMR2, 12043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12046 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12047 GIR_EraseFromParent, /*InsnID*/0, 12048 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12049 // GIR_Coverage, 1287, 12050 GIR_Done, 12051 // Label 770: @29432 12052 GIM_Try, /*On fail goto*//*Label 771*/ 29488, // Rule ID 1293 // 12053 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 12054 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph, 12055 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 12056 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 12057 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 12058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 12059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 12060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 12061 // (intrinsic_w_chain:{ *:[v2i16] } 3578:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 12062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH_MMR2, 12063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12066 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12067 GIR_EraseFromParent, /*InsnID*/0, 12068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12069 // GIR_Coverage, 1293, 12070 GIR_Done, 12071 // Label 771: @29488 12072 GIM_Try, /*On fail goto*//*Label 772*/ 29544, // Rule ID 1294 // 12073 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 12074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph, 12075 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 12076 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 12077 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 12078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 12079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 12080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 12081 // (intrinsic_w_chain:{ *:[v2i16] } 3580:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 12082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH_MMR2, 12083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12086 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12087 GIR_EraseFromParent, /*InsnID*/0, 12088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12089 // GIR_Coverage, 1294, 12090 GIR_Done, 12091 // Label 772: @29544 12092 GIM_Try, /*On fail goto*//*Label 773*/ 29600, // Rule ID 1301 // 12093 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 12094 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph, 12095 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 12096 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 12097 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 12098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 12099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 12100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 12101 // (intrinsic_w_chain:{ *:[v2i16] } 3404:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 12102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH_MMR2, 12103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12106 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12107 GIR_EraseFromParent, /*InsnID*/0, 12108 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12109 // GIR_Coverage, 1301, 12110 GIR_Done, 12111 // Label 773: @29600 12112 GIM_Try, /*On fail goto*//*Label 774*/ 29656, // Rule ID 1302 // 12113 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 12114 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w, 12115 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12116 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12117 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 12118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 12121 // (intrinsic_w_chain:{ *:[i32] } 3410:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 12122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W_MMR2, 12123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12126 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12127 GIR_EraseFromParent, /*InsnID*/0, 12128 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12129 // GIR_Coverage, 1302, 12130 GIR_Done, 12131 // Label 774: @29656 12132 GIM_Try, /*On fail goto*//*Label 775*/ 29712, // Rule ID 1303 // 12133 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 12134 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph, 12135 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 12136 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 12137 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 12138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 12139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 12140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 12141 // (intrinsic_w_chain:{ *:[v2i16] } 3411:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 12142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH_MMR2, 12143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12146 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12147 GIR_EraseFromParent, /*InsnID*/0, 12148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12149 // GIR_Coverage, 1303, 12150 GIR_Done, 12151 // Label 775: @29712 12152 GIM_Try, /*On fail goto*//*Label 776*/ 29768, // Rule ID 1304 // 12153 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 12154 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w, 12155 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12156 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12157 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 12158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 12161 // (intrinsic_w_chain:{ *:[i32] } 3412:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) 12162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W_MMR2, 12163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12166 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12167 GIR_EraseFromParent, /*InsnID*/0, 12168 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12169 // GIR_Coverage, 1304, 12170 GIR_Done, 12171 // Label 776: @29768 12172 GIM_Try, /*On fail goto*//*Label 777*/ 29824, // Rule ID 1305 // 12173 GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, 12174 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph, 12175 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, 12176 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 12177 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 12178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 12179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, 12180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, 12181 // (intrinsic_w_chain:{ *:[v4i8] } 3460:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) 12182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH_MMR2, 12183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs 12185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt 12186 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12187 GIR_EraseFromParent, /*InsnID*/0, 12188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12189 // GIR_Coverage, 1305, 12190 GIR_Done, 12191 // Label 777: @29824 12192 GIM_Try, /*On fail goto*//*Label 778*/ 29872, // Rule ID 1837 // 12193 GIM_CheckFeatures, GIFBS_HasDSPR2, 12194 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_ph, 12195 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, 12196 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, 12197 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, 12198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, 12199 // (intrinsic_w_chain:{ *:[v2i16] } 3401:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) 12200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_PH, 12201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 12203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b 12204 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12205 GIR_EraseFromParent, /*InsnID*/0, 12206 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12207 // GIR_Coverage, 1837, 12208 GIR_Done, 12209 // Label 778: @29872 12210 GIM_Try, /*On fail goto*//*Label 779*/ 29920, // Rule ID 1843 // 12211 GIM_CheckFeatures, GIFBS_HasDSP, 12212 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addsc, 12213 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12214 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12215 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 12216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12217 // (intrinsic_w_chain:{ *:[i32] } 2958:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) 12218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDSC, 12219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 12221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b 12222 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12223 GIR_EraseFromParent, /*InsnID*/0, 12224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12225 // GIR_Coverage, 1843, 12226 GIR_Done, 12227 // Label 779: @29920 12228 GIM_Try, /*On fail goto*//*Label 780*/ 29968, // Rule ID 1845 // 12229 GIM_CheckFeatures, GIFBS_HasDSP, 12230 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addwc, 12231 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12232 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12233 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 12234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12235 // (intrinsic_w_chain:{ *:[i32] } 2973:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) 12236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDWC, 12237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a 12239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b 12240 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12241 GIR_EraseFromParent, /*InsnID*/0, 12242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12243 // GIR_Coverage, 1845, 12244 GIR_Done, 12245 // Label 780: @29968 12246 GIM_Reject, 12247 // Label 709: @29969 12248 GIM_Reject, 12249 // Label 16: @29970 12250 GIM_Try, /*On fail goto*//*Label 781*/ 30026, // Rule ID 1514 // 12251 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, 12252 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12253 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 12256 // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] }) 12257 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12258 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12259 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12260 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src 12261 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL, 12263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12264 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12265 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 12266 GIR_EraseFromParent, /*InsnID*/0, 12267 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12268 // GIR_Coverage, 1514, 12269 GIR_Done, 12270 // Label 781: @30026 12271 GIM_Reject, 12272 // Label 17: @30027 12273 GIM_Try, /*On fail goto*//*Label 782*/ 30086, 12274 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12275 GIM_Try, /*On fail goto*//*Label 783*/ 30059, // Rule ID 2059 // 12276 GIM_CheckFeatures, GIFBS_InMicroMips, 12277 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_immLi16, 12278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 12279 // MIs[0] Operand 1 12280 // No operand predicates 12281 // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm) 12282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LI16_MM, 12283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12284 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm 12285 GIR_EraseFromParent, /*InsnID*/0, 12286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12287 // GIR_Coverage, 2059, 12288 GIR_Done, 12289 // Label 783: @30059 12290 GIM_Try, /*On fail goto*//*Label 784*/ 30085, // Rule ID 1761 // 12291 GIM_CheckFeatures, GIFBS_InMips16Mode, 12292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 12293 // MIs[0] Operand 1 12294 // No operand predicates 12295 // (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] }) 12296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LwConstant32, 12297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx 12298 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm 12299 GIR_AddImm, /*InsnID*/0, /*Imm*/-1, 12300 GIR_EraseFromParent, /*InsnID*/0, 12301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12302 // GIR_Coverage, 1761, 12303 GIR_Done, 12304 // Label 784: @30085 12305 GIM_Reject, 12306 // Label 782: @30086 12307 GIM_Reject, 12308 // Label 18: @30087 12309 GIM_Try, /*On fail goto*//*Label 785*/ 30114, // Rule ID 1521 // 12310 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, 12311 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 12312 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 12314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12315 // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src) 12316 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL64_32, 12317 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12318 // GIR_Coverage, 1521, 12319 GIR_Done, 12320 // Label 785: @30114 12321 GIM_Reject, 12322 // Label 19: @30115 12323 GIM_Try, /*On fail goto*//*Label 786*/ 30199, 12324 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 12325 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 12327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12328 GIM_Try, /*On fail goto*//*Label 787*/ 30172, // Rule ID 1520 // 12329 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, 12330 // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] }) 12331 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12332 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSLL64_32, 12333 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12334 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 12335 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL, 12337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12338 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12339 GIR_AddImm, /*InsnID*/0, /*Imm*/32, 12340 GIR_EraseFromParent, /*InsnID*/0, 12341 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12342 // GIR_Coverage, 1520, 12343 GIR_Done, 12344 // Label 787: @30172 12345 GIM_Try, /*On fail goto*//*Label 788*/ 30198, // Rule ID 1522 // 12346 GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips, 12347 // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] }) 12348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DEXT64_32, 12349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt 12350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12351 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 12352 GIR_AddImm, /*InsnID*/0, /*Imm*/32, 12353 GIR_EraseFromParent, /*InsnID*/0, 12354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12355 // GIR_Coverage, 1522, 12356 GIR_Done, 12357 // Label 788: @30198 12358 GIM_Reject, 12359 // Label 786: @30199 12360 GIM_Reject, 12361 // Label 20: @30200 12362 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 795*/ 30723, 12363 /*GILLT_s32*//*Label 789*/ 30214, 12364 /*GILLT_s64*//*Label 790*/ 30467, 0, 12365 /*GILLT_v2s64*//*Label 791*/ 30595, 0, 12366 /*GILLT_v4s32*//*Label 792*/ 30627, 12367 /*GILLT_v8s16*//*Label 793*/ 30659, 12368 /*GILLT_v16s8*//*Label 794*/ 30691, 12369 // Label 789: @30214 12370 GIM_Try, /*On fail goto*//*Label 796*/ 30466, 12371 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12372 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12373 GIM_Try, /*On fail goto*//*Label 797*/ 30267, // Rule ID 43 // 12374 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 12375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12377 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12378 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12379 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 12380 // MIs[1] Operand 1 12381 // No operand predicates 12382 GIM_CheckIsSafeToFold, /*InsnID*/1, 12383 // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) 12384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL, 12385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 12387 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 12388 GIR_EraseFromParent, /*InsnID*/0, 12389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12390 // GIR_Coverage, 43, 12391 GIR_Done, 12392 // Label 797: @30267 12393 GIM_Try, /*On fail goto*//*Label 798*/ 30310, // Rule ID 1743 // 12394 GIM_CheckFeatures, GIFBS_InMips16Mode, 12395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 12396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 12397 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12398 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12399 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 12400 // MIs[1] Operand 1 12401 // No operand predicates 12402 GIM_CheckIsSafeToFold, /*InsnID*/1, 12403 // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) 12404 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SllX16, 12405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx 12406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 12407 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 12408 GIR_EraseFromParent, /*InsnID*/0, 12409 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12410 // GIR_Coverage, 1743, 12411 GIR_Done, 12412 // Label 798: @30310 12413 GIM_Try, /*On fail goto*//*Label 799*/ 30353, // Rule ID 2071 // 12414 GIM_CheckFeatures, GIFBS_InMicroMips, 12415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 12416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 12417 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12418 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12419 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift, 12420 // MIs[1] Operand 1 12421 // No operand predicates 12422 GIM_CheckIsSafeToFold, /*InsnID*/1, 12423 // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) 12424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL16_MM, 12425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12427 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 12428 GIR_EraseFromParent, /*InsnID*/0, 12429 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12430 // GIR_Coverage, 2071, 12431 GIR_Done, 12432 // Label 799: @30353 12433 GIM_Try, /*On fail goto*//*Label 800*/ 30396, // Rule ID 2072 // 12434 GIM_CheckFeatures, GIFBS_InMicroMips, 12435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12437 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12438 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12439 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 12440 // MIs[1] Operand 1 12441 // No operand predicates 12442 GIM_CheckIsSafeToFold, /*InsnID*/1, 12443 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) 12444 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_MM, 12445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12447 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 12448 GIR_EraseFromParent, /*InsnID*/0, 12449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12450 // GIR_Coverage, 2072, 12451 GIR_Done, 12452 // Label 800: @30396 12453 GIM_Try, /*On fail goto*//*Label 801*/ 30419, // Rule ID 46 // 12454 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 12455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12458 // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 12459 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV, 12460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12461 // GIR_Coverage, 46, 12462 GIR_Done, 12463 // Label 801: @30419 12464 GIM_Try, /*On fail goto*//*Label 802*/ 30442, // Rule ID 1746 // 12465 GIM_CheckFeatures, GIFBS_InMips16Mode, 12466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 12467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 12468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 12469 // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) 12470 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SllvRxRy16, 12471 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12472 // GIR_Coverage, 1746, 12473 GIR_Done, 12474 // Label 802: @30442 12475 GIM_Try, /*On fail goto*//*Label 803*/ 30465, // Rule ID 2073 // 12476 GIM_CheckFeatures, GIFBS_InMicroMips, 12477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12480 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) 12481 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV_MM, 12482 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12483 // GIR_Coverage, 2073, 12484 GIR_Done, 12485 // Label 803: @30465 12486 GIM_Reject, 12487 // Label 796: @30466 12488 GIM_Reject, 12489 // Label 790: @30467 12490 GIM_Try, /*On fail goto*//*Label 804*/ 30594, 12491 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12492 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 12494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 12495 GIM_Try, /*On fail goto*//*Label 805*/ 30520, // Rule ID 188 // 12496 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, 12497 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12498 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12499 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6, 12500 // MIs[1] Operand 1 12501 // No operand predicates 12502 GIM_CheckIsSafeToFold, /*InsnID*/1, 12503 // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) 12504 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLL, 12505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 12507 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 12508 GIR_EraseFromParent, /*InsnID*/0, 12509 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12510 // GIR_Coverage, 188, 12511 GIR_Done, 12512 // Label 805: @30520 12513 GIM_Try, /*On fail goto*//*Label 806*/ 30578, // Rule ID 1515 // 12514 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, 12515 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12516 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, 12517 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 12518 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 12519 GIM_CheckIsSafeToFold, /*InsnID*/1, 12520 // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) 12521 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12522 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12523 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12524 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs 12525 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV, 12527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 12529 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12530 GIR_EraseFromParent, /*InsnID*/0, 12531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12532 // GIR_Coverage, 1515, 12533 GIR_Done, 12534 // Label 806: @30578 12535 GIM_Try, /*On fail goto*//*Label 807*/ 30593, // Rule ID 191 // 12536 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, 12537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12538 // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 12539 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSLLV, 12540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12541 // GIR_Coverage, 191, 12542 GIR_Done, 12543 // Label 807: @30593 12544 GIM_Reject, 12545 // Label 804: @30594 12546 GIM_Reject, 12547 // Label 791: @30595 12548 GIM_Try, /*On fail goto*//*Label 808*/ 30626, // Rule ID 928 // 12549 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 12550 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 12551 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 12552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 12553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 12554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 12555 // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 12556 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_D, 12557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12558 // GIR_Coverage, 928, 12559 GIR_Done, 12560 // Label 808: @30626 12561 GIM_Reject, 12562 // Label 792: @30627 12563 GIM_Try, /*On fail goto*//*Label 809*/ 30658, // Rule ID 927 // 12564 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 12565 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 12566 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 12568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 12569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 12570 // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 12571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_W, 12572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12573 // GIR_Coverage, 927, 12574 GIR_Done, 12575 // Label 809: @30658 12576 GIM_Reject, 12577 // Label 793: @30659 12578 GIM_Try, /*On fail goto*//*Label 810*/ 30690, // Rule ID 926 // 12579 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 12580 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 12581 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 12583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 12584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 12585 // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 12586 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_H, 12587 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12588 // GIR_Coverage, 926, 12589 GIR_Done, 12590 // Label 810: @30690 12591 GIM_Reject, 12592 // Label 794: @30691 12593 GIM_Try, /*On fail goto*//*Label 811*/ 30722, // Rule ID 925 // 12594 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 12595 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 12596 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 12597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 12598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 12599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 12600 // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 12601 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_B, 12602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12603 // GIR_Coverage, 925, 12604 GIR_Done, 12605 // Label 811: @30722 12606 GIM_Reject, 12607 // Label 795: @30723 12608 GIM_Reject, 12609 // Label 21: @30724 12610 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 818*/ 31247, 12611 /*GILLT_s32*//*Label 812*/ 30738, 12612 /*GILLT_s64*//*Label 813*/ 30991, 0, 12613 /*GILLT_v2s64*//*Label 814*/ 31119, 0, 12614 /*GILLT_v4s32*//*Label 815*/ 31151, 12615 /*GILLT_v8s16*//*Label 816*/ 31183, 12616 /*GILLT_v16s8*//*Label 817*/ 31215, 12617 // Label 812: @30738 12618 GIM_Try, /*On fail goto*//*Label 819*/ 30990, 12619 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12620 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12621 GIM_Try, /*On fail goto*//*Label 820*/ 30791, // Rule ID 44 // 12622 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 12623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12625 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12626 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12627 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 12628 // MIs[1] Operand 1 12629 // No operand predicates 12630 GIM_CheckIsSafeToFold, /*InsnID*/1, 12631 // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) 12632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL, 12633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 12635 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 12636 GIR_EraseFromParent, /*InsnID*/0, 12637 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12638 // GIR_Coverage, 44, 12639 GIR_Done, 12640 // Label 820: @30791 12641 GIM_Try, /*On fail goto*//*Label 821*/ 30834, // Rule ID 1744 // 12642 GIM_CheckFeatures, GIFBS_InMips16Mode, 12643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 12644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 12645 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12646 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12647 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 12648 // MIs[1] Operand 1 12649 // No operand predicates 12650 GIM_CheckIsSafeToFold, /*InsnID*/1, 12651 // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) 12652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SrlX16, 12653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx 12654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 12655 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 12656 GIR_EraseFromParent, /*InsnID*/0, 12657 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12658 // GIR_Coverage, 1744, 12659 GIR_Done, 12660 // Label 821: @30834 12661 GIM_Try, /*On fail goto*//*Label 822*/ 30877, // Rule ID 2074 // 12662 GIM_CheckFeatures, GIFBS_InMicroMips, 12663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, 12664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, 12665 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12666 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12667 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift, 12668 // MIs[1] Operand 1 12669 // No operand predicates 12670 GIM_CheckIsSafeToFold, /*InsnID*/1, 12671 // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) 12672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL16_MM, 12673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12675 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 12676 GIR_EraseFromParent, /*InsnID*/0, 12677 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12678 // GIR_Coverage, 2074, 12679 GIR_Done, 12680 // Label 822: @30877 12681 GIM_Try, /*On fail goto*//*Label 823*/ 30920, // Rule ID 2075 // 12682 GIM_CheckFeatures, GIFBS_InMicroMips, 12683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12685 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12686 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12687 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 12688 // MIs[1] Operand 1 12689 // No operand predicates 12690 GIM_CheckIsSafeToFold, /*InsnID*/1, 12691 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) 12692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_MM, 12693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12695 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 12696 GIR_EraseFromParent, /*InsnID*/0, 12697 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12698 // GIR_Coverage, 2075, 12699 GIR_Done, 12700 // Label 823: @30920 12701 GIM_Try, /*On fail goto*//*Label 824*/ 30943, // Rule ID 47 // 12702 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 12703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12706 // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 12707 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV, 12708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12709 // GIR_Coverage, 47, 12710 GIR_Done, 12711 // Label 824: @30943 12712 GIM_Try, /*On fail goto*//*Label 825*/ 30966, // Rule ID 1748 // 12713 GIM_CheckFeatures, GIFBS_InMips16Mode, 12714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 12715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 12716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 12717 // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) 12718 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SrlvRxRy16, 12719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12720 // GIR_Coverage, 1748, 12721 GIR_Done, 12722 // Label 825: @30966 12723 GIM_Try, /*On fail goto*//*Label 826*/ 30989, // Rule ID 2076 // 12724 GIM_CheckFeatures, GIFBS_InMicroMips, 12725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12728 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) 12729 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV_MM, 12730 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12731 // GIR_Coverage, 2076, 12732 GIR_Done, 12733 // Label 826: @30989 12734 GIM_Reject, 12735 // Label 819: @30990 12736 GIM_Reject, 12737 // Label 813: @30991 12738 GIM_Try, /*On fail goto*//*Label 827*/ 31118, 12739 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12740 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 12742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 12743 GIM_Try, /*On fail goto*//*Label 828*/ 31044, // Rule ID 189 // 12744 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, 12745 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12746 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12747 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6, 12748 // MIs[1] Operand 1 12749 // No operand predicates 12750 GIM_CheckIsSafeToFold, /*InsnID*/1, 12751 // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) 12752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL, 12753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 12755 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 12756 GIR_EraseFromParent, /*InsnID*/0, 12757 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12758 // GIR_Coverage, 189, 12759 GIR_Done, 12760 // Label 828: @31044 12761 GIM_Try, /*On fail goto*//*Label 829*/ 31102, // Rule ID 1516 // 12762 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, 12763 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12764 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, 12765 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 12766 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 12767 GIM_CheckIsSafeToFold, /*InsnID*/1, 12768 // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) 12769 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12770 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12771 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12772 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs 12773 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV, 12775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 12777 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12778 GIR_EraseFromParent, /*InsnID*/0, 12779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12780 // GIR_Coverage, 1516, 12781 GIR_Done, 12782 // Label 829: @31102 12783 GIM_Try, /*On fail goto*//*Label 830*/ 31117, // Rule ID 193 // 12784 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, 12785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12786 // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 12787 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRLV, 12788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12789 // GIR_Coverage, 193, 12790 GIR_Done, 12791 // Label 830: @31117 12792 GIM_Reject, 12793 // Label 827: @31118 12794 GIM_Reject, 12795 // Label 814: @31119 12796 GIM_Try, /*On fail goto*//*Label 831*/ 31150, // Rule ID 960 // 12797 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 12798 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 12799 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 12800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 12801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 12802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 12803 // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 12804 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_D, 12805 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12806 // GIR_Coverage, 960, 12807 GIR_Done, 12808 // Label 831: @31150 12809 GIM_Reject, 12810 // Label 815: @31151 12811 GIM_Try, /*On fail goto*//*Label 832*/ 31182, // Rule ID 959 // 12812 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 12813 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 12814 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 12816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 12817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 12818 // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 12819 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_W, 12820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12821 // GIR_Coverage, 959, 12822 GIR_Done, 12823 // Label 832: @31182 12824 GIM_Reject, 12825 // Label 816: @31183 12826 GIM_Try, /*On fail goto*//*Label 833*/ 31214, // Rule ID 958 // 12827 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 12828 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 12829 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 12831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 12832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 12833 // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 12834 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_H, 12835 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12836 // GIR_Coverage, 958, 12837 GIR_Done, 12838 // Label 833: @31214 12839 GIM_Reject, 12840 // Label 817: @31215 12841 GIM_Try, /*On fail goto*//*Label 834*/ 31246, // Rule ID 957 // 12842 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 12843 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 12844 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 12845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 12846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 12847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 12848 // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 12849 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_B, 12850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12851 // GIR_Coverage, 957, 12852 GIR_Done, 12853 // Label 834: @31246 12854 GIM_Reject, 12855 // Label 818: @31247 12856 GIM_Reject, 12857 // Label 22: @31248 12858 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 841*/ 31728, 12859 /*GILLT_s32*//*Label 835*/ 31262, 12860 /*GILLT_s64*//*Label 836*/ 31472, 0, 12861 /*GILLT_v2s64*//*Label 837*/ 31600, 0, 12862 /*GILLT_v4s32*//*Label 838*/ 31632, 12863 /*GILLT_v8s16*//*Label 839*/ 31664, 12864 /*GILLT_v16s8*//*Label 840*/ 31696, 12865 // Label 835: @31262 12866 GIM_Try, /*On fail goto*//*Label 842*/ 31471, 12867 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12868 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12869 GIM_Try, /*On fail goto*//*Label 843*/ 31315, // Rule ID 45 // 12870 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 12871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12873 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12874 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12875 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 12876 // MIs[1] Operand 1 12877 // No operand predicates 12878 GIM_CheckIsSafeToFold, /*InsnID*/1, 12879 // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) 12880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA, 12881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 12883 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 12884 GIR_EraseFromParent, /*InsnID*/0, 12885 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12886 // GIR_Coverage, 45, 12887 GIR_Done, 12888 // Label 843: @31315 12889 GIM_Try, /*On fail goto*//*Label 844*/ 31358, // Rule ID 1745 // 12890 GIM_CheckFeatures, GIFBS_InMips16Mode, 12891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 12892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 12893 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12894 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12895 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 12896 // MIs[1] Operand 1 12897 // No operand predicates 12898 GIM_CheckIsSafeToFold, /*InsnID*/1, 12899 // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) 12900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SraX16, 12901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx 12902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in 12903 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 12904 GIR_EraseFromParent, /*InsnID*/0, 12905 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12906 // GIR_Coverage, 1745, 12907 GIR_Done, 12908 // Label 844: @31358 12909 GIM_Try, /*On fail goto*//*Label 845*/ 31401, // Rule ID 2077 // 12910 GIM_CheckFeatures, GIFBS_InMicroMips, 12911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12913 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12914 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12915 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5, 12916 // MIs[1] Operand 1 12917 // No operand predicates 12918 GIM_CheckIsSafeToFold, /*InsnID*/1, 12919 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) 12920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_MM, 12921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12923 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 12924 GIR_EraseFromParent, /*InsnID*/0, 12925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12926 // GIR_Coverage, 2077, 12927 GIR_Done, 12928 // Label 845: @31401 12929 GIM_Try, /*On fail goto*//*Label 846*/ 31424, // Rule ID 48 // 12930 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 12931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12934 // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 12935 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV, 12936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12937 // GIR_Coverage, 48, 12938 GIR_Done, 12939 // Label 846: @31424 12940 GIM_Try, /*On fail goto*//*Label 847*/ 31447, // Rule ID 1747 // 12941 GIM_CheckFeatures, GIFBS_InMips16Mode, 12942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 12943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 12944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 12945 // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) 12946 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SravRxRy16, 12947 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12948 // GIR_Coverage, 1747, 12949 GIR_Done, 12950 // Label 847: @31447 12951 GIM_Try, /*On fail goto*//*Label 848*/ 31470, // Rule ID 2078 // 12952 GIM_CheckFeatures, GIFBS_InMicroMips, 12953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 12954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 12955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 12956 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) 12957 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV_MM, 12958 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12959 // GIR_Coverage, 2078, 12960 GIR_Done, 12961 // Label 848: @31470 12962 GIM_Reject, 12963 // Label 842: @31471 12964 GIM_Reject, 12965 // Label 836: @31472 12966 GIM_Try, /*On fail goto*//*Label 849*/ 31599, 12967 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12968 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 12970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 12971 GIM_Try, /*On fail goto*//*Label 850*/ 31525, // Rule ID 190 // 12972 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, 12973 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12974 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12975 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6, 12976 // MIs[1] Operand 1 12977 // No operand predicates 12978 GIM_CheckIsSafeToFold, /*InsnID*/1, 12979 // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) 12980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRA, 12981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12982 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 12983 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 12984 GIR_EraseFromParent, /*InsnID*/0, 12985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12986 // GIR_Coverage, 190, 12987 GIR_Done, 12988 // Label 850: @31525 12989 GIM_Try, /*On fail goto*//*Label 851*/ 31583, // Rule ID 1517 // 12990 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, 12991 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12992 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, 12993 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 12994 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 12995 GIM_CheckIsSafeToFold, /*InsnID*/1, 12996 // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) 12997 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12998 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12999 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13000 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs 13001 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRAV, 13003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt 13005 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13006 GIR_EraseFromParent, /*InsnID*/0, 13007 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13008 // GIR_Coverage, 1517, 13009 GIR_Done, 13010 // Label 851: @31583 13011 GIM_Try, /*On fail goto*//*Label 852*/ 31598, // Rule ID 192 // 13012 GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, 13013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 13014 // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) 13015 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRAV, 13016 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13017 // GIR_Coverage, 192, 13018 GIR_Done, 13019 // Label 852: @31598 13020 GIM_Reject, 13021 // Label 849: @31599 13022 GIM_Reject, 13023 // Label 837: @31600 13024 GIM_Try, /*On fail goto*//*Label 853*/ 31631, // Rule ID 944 // 13025 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 13026 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13027 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 13029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 13030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 13031 // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) 13032 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_D, 13033 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13034 // GIR_Coverage, 944, 13035 GIR_Done, 13036 // Label 853: @31631 13037 GIM_Reject, 13038 // Label 838: @31632 13039 GIM_Try, /*On fail goto*//*Label 854*/ 31663, // Rule ID 943 // 13040 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 13041 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13042 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 13044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 13045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 13046 // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) 13047 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_W, 13048 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13049 // GIR_Coverage, 943, 13050 GIR_Done, 13051 // Label 854: @31663 13052 GIM_Reject, 13053 // Label 839: @31664 13054 GIM_Try, /*On fail goto*//*Label 855*/ 31695, // Rule ID 942 // 13055 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 13056 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 13057 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 13058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, 13059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, 13060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, 13061 // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) 13062 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_H, 13063 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13064 // GIR_Coverage, 942, 13065 GIR_Done, 13066 // Label 855: @31695 13067 GIM_Reject, 13068 // Label 840: @31696 13069 GIM_Try, /*On fail goto*//*Label 856*/ 31727, // Rule ID 941 // 13070 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 13071 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 13072 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 13073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, 13074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, 13075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, 13076 // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) 13077 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_B, 13078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13079 // GIR_Coverage, 941, 13080 GIR_Done, 13081 // Label 856: @31727 13082 GIM_Reject, 13083 // Label 841: @31728 13084 GIM_Reject, 13085 // Label 23: @31729 13086 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 859*/ 33182, 13087 /*GILLT_s32*//*Label 857*/ 31737, 13088 /*GILLT_s64*//*Label 858*/ 32536, 13089 // Label 857: @31737 13090 GIM_Try, /*On fail goto*//*Label 860*/ 31776, // Rule ID 267 // 13091 GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32, 13092 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13093 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13094 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 13096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 13098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 13099 // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) 13100 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I, 13101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13102 // GIR_Coverage, 267, 13103 GIR_Done, 13104 // Label 860: @31776 13105 GIM_Try, /*On fail goto*//*Label 861*/ 31815, // Rule ID 269 // 13106 GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32, 13107 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13108 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13109 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 13111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, 13114 // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) 13115 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_S, 13116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13117 // GIR_Coverage, 269, 13118 GIR_Done, 13119 // Label 861: @31815 13120 GIM_Try, /*On fail goto*//*Label 862*/ 31871, // Rule ID 306 // 13121 GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 13122 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13123 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13124 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 13126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID, 13127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, 13129 // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 13130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S, 13131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in 13133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs 13134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft 13135 GIR_EraseFromParent, /*InsnID*/0, 13136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13137 // GIR_Coverage, 306, 13138 GIR_Done, 13139 // Label 862: @31871 13140 GIM_Try, /*On fail goto*//*Label 863*/ 31927, // Rule ID 1170 // 13141 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 13142 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13143 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13144 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 13146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID, 13147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, 13149 // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 13150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S_MMR6, 13151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in 13153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs 13154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft 13155 GIR_EraseFromParent, /*InsnID*/0, 13156 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13157 // GIR_Coverage, 1170, 13158 GIR_Done, 13159 // Label 863: @31927 13160 GIM_Try, /*On fail goto*//*Label 864*/ 31983, // Rule ID 1567 // 13161 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, 13162 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13163 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13164 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 13166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 13168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 13169 // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F) 13170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I, 13171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13175 GIR_EraseFromParent, /*InsnID*/0, 13176 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13177 // GIR_Coverage, 1567, 13178 GIR_Done, 13179 // Label 864: @31983 13180 GIM_Try, /*On fail goto*//*Label 865*/ 32039, // Rule ID 1606 // 13181 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 13182 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13183 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13184 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 13186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 13187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 13188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 13189 // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F) 13190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I, 13191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13195 GIR_EraseFromParent, /*InsnID*/0, 13196 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13197 // GIR_Coverage, 1606, 13198 GIR_Done, 13199 // Label 865: @32039 13200 GIM_Try, /*On fail goto*//*Label 866*/ 32095, // Rule ID 1622 // 13201 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, 13202 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13203 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13204 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 13206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, 13209 // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F) 13210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S, 13211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13215 GIR_EraseFromParent, /*InsnID*/0, 13216 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13217 // GIR_Coverage, 1622, 13218 GIR_Done, 13219 // Label 866: @32095 13220 GIM_Try, /*On fail goto*//*Label 867*/ 32151, // Rule ID 1635 // 13221 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 13222 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13223 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13224 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 13226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 13227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, 13229 // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F) 13230 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S, 13231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13235 GIR_EraseFromParent, /*InsnID*/0, 13236 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13237 // GIR_Coverage, 1635, 13238 GIR_Done, 13239 // Label 867: @32151 13240 GIM_Try, /*On fail goto*//*Label 868*/ 32207, // Rule ID 1792 // 13241 GIM_CheckFeatures, GIFBS_InMips16Mode, 13242 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13243 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13244 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, 13246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, 13247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, 13248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, 13249 // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a) 13250 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ, 13251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ 13252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x 13253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y 13254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a 13255 GIR_EraseFromParent, /*InsnID*/0, 13256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13257 // GIR_Coverage, 1792, 13258 GIR_Done, 13259 // Label 868: @32207 13260 GIM_Try, /*On fail goto*//*Label 869*/ 32263, // Rule ID 2128 // 13261 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, 13262 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13263 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13264 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 13266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 13268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 13269 // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F) 13270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, 13271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13275 GIR_EraseFromParent, /*InsnID*/0, 13276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13277 // GIR_Coverage, 2128, 13278 GIR_Done, 13279 // Label 869: @32263 13280 GIM_Try, /*On fail goto*//*Label 870*/ 32319, // Rule ID 2142 // 13281 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 13282 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13283 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13284 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 13286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, 13288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, 13289 // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F) 13290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, 13291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13295 GIR_EraseFromParent, /*InsnID*/0, 13296 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13297 // GIR_Coverage, 2142, 13298 GIR_Done, 13299 // Label 870: @32319 13300 GIM_Try, /*On fail goto*//*Label 871*/ 32375, // Rule ID 2170 // 13301 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, 13302 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13303 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13304 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 13306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, 13309 // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F) 13310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM, 13311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13315 GIR_EraseFromParent, /*InsnID*/0, 13316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13317 // GIR_Coverage, 2170, 13318 GIR_Done, 13319 // Label 871: @32375 13320 GIM_Try, /*On fail goto*//*Label 872*/ 32455, // Rule ID 1704 // 13321 GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, 13322 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13323 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13324 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 13326 // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)) 13327 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13328 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 13329 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ, 13330 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13331 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f 13332 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond 13333 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 13334 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ, 13335 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13336 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t 13337 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond 13338 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR, 13340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13341 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13342 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 13343 GIR_EraseFromParent, /*InsnID*/0, 13344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13345 // GIR_Coverage, 1704, 13346 GIR_Done, 13347 // Label 872: @32455 13348 GIM_Try, /*On fail goto*//*Label 873*/ 32535, // Rule ID 2187 // 13349 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 13350 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13351 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13352 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 13354 // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)) 13355 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13356 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 13357 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ_MMR6, 13358 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13359 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f 13360 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond 13361 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 13362 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ_MMR6, 13363 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13364 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t 13365 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond 13366 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR_MM, 13368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13369 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13370 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 13371 GIR_EraseFromParent, /*InsnID*/0, 13372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13373 // GIR_Coverage, 2187, 13374 GIR_Done, 13375 // Label 873: @32535 13376 GIM_Reject, 13377 // Label 858: @32536 13378 GIM_Try, /*On fail goto*//*Label 874*/ 32575, // Rule ID 268 // 13379 GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32, 13380 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13381 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13382 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 13384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 13386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, 13387 // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) 13388 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I64, 13389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13390 // GIR_Coverage, 268, 13391 GIR_Done, 13392 // Label 874: @32575 13393 GIM_Try, /*On fail goto*//*Label 875*/ 32614, // Rule ID 270 // 13394 GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotMips4_32, 13395 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13396 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13397 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 13399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 13401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, 13402 // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) 13403 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D32, 13404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13405 // GIR_Coverage, 270, 13406 GIR_Done, 13407 // Label 875: @32614 13408 GIM_Try, /*On fail goto*//*Label 876*/ 32653, // Rule ID 271 // 13409 GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotMips4_32, 13410 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13411 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13412 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 13414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 13416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, 13417 // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) 13418 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D64, 13419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13420 // GIR_Coverage, 271, 13421 GIR_Done, 13422 // Label 876: @32653 13423 GIM_Try, /*On fail goto*//*Label 877*/ 32709, // Rule ID 1603 // 13424 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 13425 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13426 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13427 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 13429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 13431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, 13432 // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F) 13433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64, 13434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13438 GIR_EraseFromParent, /*InsnID*/0, 13439 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13440 // GIR_Coverage, 1603, 13441 GIR_Done, 13442 // Label 877: @32709 13443 GIM_Try, /*On fail goto*//*Label 878*/ 32765, // Rule ID 1609 // 13444 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 13445 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13446 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13447 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 13449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 13450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, 13451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, 13452 // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F) 13453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64, 13454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13458 GIR_EraseFromParent, /*InsnID*/0, 13459 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13460 // GIR_Coverage, 1609, 13461 GIR_Done, 13462 // Label 878: @32765 13463 GIM_Try, /*On fail goto*//*Label 879*/ 32821, // Rule ID 1648 // 13464 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 13465 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13466 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13467 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 13469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 13471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, 13472 // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F) 13473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32, 13474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13478 GIR_EraseFromParent, /*InsnID*/0, 13479 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13480 // GIR_Coverage, 1648, 13481 GIR_Done, 13482 // Label 879: @32821 13483 GIM_Try, /*On fail goto*//*Label 880*/ 32877, // Rule ID 1671 // 13484 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 13485 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13486 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13487 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 13489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 13491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, 13492 // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F) 13493 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64, 13494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13498 GIR_EraseFromParent, /*InsnID*/0, 13499 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13500 // GIR_Coverage, 1671, 13501 GIR_Done, 13502 // Label 880: @32877 13503 GIM_Try, /*On fail goto*//*Label 881*/ 32933, // Rule ID 1674 // 13504 GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 13505 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13506 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13507 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 13509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 13510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 13511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, 13512 // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F) 13513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64, 13514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13518 GIR_EraseFromParent, /*InsnID*/0, 13519 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13520 // GIR_Coverage, 1674, 13521 GIR_Done, 13522 // Label 881: @32933 13523 GIM_Try, /*On fail goto*//*Label 882*/ 32989, // Rule ID 2183 // 13524 GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, 13525 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13526 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13527 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 13529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 13530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 13531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, 13532 // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F) 13533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM, 13534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T 13536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond 13537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F 13538 GIR_EraseFromParent, /*InsnID*/0, 13539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13540 // GIR_Coverage, 2183, 13541 GIR_Done, 13542 // Label 882: @32989 13543 GIM_Try, /*On fail goto*//*Label 883*/ 33069, // Rule ID 1707 // 13544 GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, 13545 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13546 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13547 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 13549 // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond)) 13550 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 13551 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 13552 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ64, 13553 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13554 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f 13555 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond 13556 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 13557 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64, 13558 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13559 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t 13560 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond 13561 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64, 13563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13564 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13565 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 13566 GIR_EraseFromParent, /*InsnID*/0, 13567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13568 // GIR_Coverage, 1707, 13569 GIR_Done, 13570 // Label 883: @33069 13571 GIM_Try, /*On fail goto*//*Label 884*/ 33181, // Rule ID 1718 // 13572 GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, 13573 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13574 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13575 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 13576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 13577 // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond))) 13578 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 13579 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 13580 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 13581 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, 13582 GIR_BuildMI, /*InsnID*/4, /*Opcode*/Mips::SLL64_32, 13583 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 13584 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond 13585 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 13586 GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SELEQZ64, 13587 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 13588 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f 13589 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, 13590 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 13591 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL64_32, 13592 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13593 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond 13594 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 13595 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64, 13596 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13597 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t 13598 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 13599 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64, 13601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 13602 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13603 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, 13604 GIR_EraseFromParent, /*InsnID*/0, 13605 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13606 // GIR_Coverage, 1718, 13607 GIR_Done, 13608 // Label 884: @33181 13609 GIM_Reject, 13610 // Label 859: @33182 13611 GIM_Reject, 13612 // Label 24: @33183 13613 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 889*/ 34061, 13614 /*GILLT_s32*//*Label 885*/ 33195, 13615 /*GILLT_s64*//*Label 886*/ 33395, 0, 13616 /*GILLT_v2s64*//*Label 887*/ 33743, 0, 13617 /*GILLT_v4s32*//*Label 888*/ 33902, 13618 // Label 885: @33195 13619 GIM_Try, /*On fail goto*//*Label 890*/ 33394, 13620 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13621 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 13623 GIM_Try, /*On fail goto*//*Label 891*/ 33266, // Rule ID 145 // 13624 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, 13625 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 13626 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13627 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 13628 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 13629 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 13630 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13632 GIM_CheckIsSafeToFold, /*InsnID*/1, 13633 // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 13634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S, 13635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr 13637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs 13638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft 13639 GIR_EraseFromParent, /*InsnID*/0, 13640 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13641 // GIR_Coverage, 145, 13642 GIR_Done, 13643 // Label 891: @33266 13644 GIM_Try, /*On fail goto*//*Label 892*/ 33323, // Rule ID 2241 // 13645 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, 13646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 13647 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 13648 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13649 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 13650 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 13651 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 13652 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13653 GIM_CheckIsSafeToFold, /*InsnID*/1, 13654 // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 13655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S, 13656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr 13658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs 13659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft 13660 GIR_EraseFromParent, /*InsnID*/0, 13661 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13662 // GIR_Coverage, 2241, 13663 GIR_Done, 13664 // Label 892: @33323 13665 GIM_Try, /*On fail goto*//*Label 893*/ 33342, // Rule ID 133 // 13666 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 13667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 13668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13669 // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 13670 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S, 13671 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13672 // GIR_Coverage, 133, 13673 GIR_Done, 13674 // Label 893: @33342 13675 GIM_Try, /*On fail goto*//*Label 894*/ 33361, // Rule ID 1089 // 13676 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, 13677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 13678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13679 // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 13680 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S_MM, 13681 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13682 // GIR_Coverage, 1089, 13683 GIR_Done, 13684 // Label 894: @33361 13685 GIM_Try, /*On fail goto*//*Label 895*/ 33393, // Rule ID 1145 // 13686 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, 13687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 13688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13689 // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) 13690 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FADD_S_MMR6, 13691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft 13693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs 13694 GIR_EraseFromParent, /*InsnID*/0, 13695 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13696 // GIR_Coverage, 1145, 13697 GIR_Done, 13698 // Label 895: @33393 13699 GIM_Reject, 13700 // Label 890: @33394 13701 GIM_Reject, 13702 // Label 886: @33395 13703 GIM_Try, /*On fail goto*//*Label 896*/ 33742, 13704 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13705 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13706 GIM_Try, /*On fail goto*//*Label 897*/ 33466, // Rule ID 147 // 13707 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 13708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 13709 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 13710 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13711 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 13712 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 13713 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 13714 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 13715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 13716 GIM_CheckIsSafeToFold, /*InsnID*/1, 13717 // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 13718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32, 13719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr 13721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs 13722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft 13723 GIR_EraseFromParent, /*InsnID*/0, 13724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13725 // GIR_Coverage, 147, 13726 GIR_Done, 13727 // Label 897: @33466 13728 GIM_Try, /*On fail goto*//*Label 898*/ 33527, // Rule ID 149 // 13729 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, 13730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 13731 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 13732 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13733 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 13734 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 13735 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 13736 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 13737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 13738 GIM_CheckIsSafeToFold, /*InsnID*/1, 13739 // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 13740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64, 13741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr 13743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs 13744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft 13745 GIR_EraseFromParent, /*InsnID*/0, 13746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13747 // GIR_Coverage, 149, 13748 GIR_Done, 13749 // Label 898: @33527 13750 GIM_Try, /*On fail goto*//*Label 899*/ 33588, // Rule ID 2242 // 13751 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 13752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 13753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 13754 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 13755 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13756 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 13757 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 13758 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 13759 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 13760 GIM_CheckIsSafeToFold, /*InsnID*/1, 13761 // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 13762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32, 13763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr 13765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs 13766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft 13767 GIR_EraseFromParent, /*InsnID*/0, 13768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13769 // GIR_Coverage, 2242, 13770 GIR_Done, 13771 // Label 899: @33588 13772 GIM_Try, /*On fail goto*//*Label 900*/ 33649, // Rule ID 2243 // 13773 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, 13774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 13775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 13776 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 13777 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13778 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 13779 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 13780 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 13781 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 13782 GIM_CheckIsSafeToFold, /*InsnID*/1, 13783 // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 13784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64, 13785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr 13787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs 13788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft 13789 GIR_EraseFromParent, /*InsnID*/0, 13790 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13791 // GIR_Coverage, 2243, 13792 GIR_Done, 13793 // Label 900: @33649 13794 GIM_Try, /*On fail goto*//*Label 901*/ 33672, // Rule ID 134 // 13795 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, 13796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 13797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 13798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 13799 // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 13800 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32, 13801 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13802 // GIR_Coverage, 134, 13803 GIR_Done, 13804 // Label 901: @33672 13805 GIM_Try, /*On fail goto*//*Label 902*/ 33695, // Rule ID 135 // 13806 GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, 13807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 13808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 13809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 13810 // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 13811 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64, 13812 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13813 // GIR_Coverage, 135, 13814 GIR_Done, 13815 // Label 902: @33695 13816 GIM_Try, /*On fail goto*//*Label 903*/ 33718, // Rule ID 1093 // 13817 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, 13818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 13819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 13820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 13821 // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 13822 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32_MM, 13823 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13824 // GIR_Coverage, 1093, 13825 GIR_Done, 13826 // Label 903: @33718 13827 GIM_Try, /*On fail goto*//*Label 904*/ 33741, // Rule ID 1094 // 13828 GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, 13829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 13830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 13831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 13832 // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 13833 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64_MM, 13834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13835 // GIR_Coverage, 1094, 13836 GIR_Done, 13837 // Label 904: @33741 13838 GIM_Reject, 13839 // Label 896: @33742 13840 GIM_Reject, 13841 // Label 887: @33743 13842 GIM_Try, /*On fail goto*//*Label 905*/ 33901, 13843 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13844 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13845 GIM_Try, /*On fail goto*//*Label 906*/ 33815, // Rule ID 2348 // 13846 GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, 13847 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, 13848 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 13849 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13850 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 13851 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 13852 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 13853 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 13854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 13855 GIM_CheckIsSafeToFold, /*InsnID*/1, 13856 // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 13857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D, 13858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd 13859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd 13860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 13861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 13862 GIR_EraseFromParent, /*InsnID*/0, 13863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13864 // GIR_Coverage, 2348, 13865 GIR_Done, 13866 // Label 906: @33815 13867 GIM_Try, /*On fail goto*//*Label 907*/ 33877, // Rule ID 1901 // 13868 GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, 13869 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, 13870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 13871 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 13872 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13873 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 13874 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 13875 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 13876 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 13877 GIM_CheckIsSafeToFold, /*InsnID*/1, 13878 // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 13879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D, 13880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd 13881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd 13882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 13883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 13884 GIR_EraseFromParent, /*InsnID*/0, 13885 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13886 // GIR_Coverage, 1901, 13887 GIR_Done, 13888 // Label 907: @33877 13889 GIM_Try, /*On fail goto*//*Label 908*/ 33900, // Rule ID 639 // 13890 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 13891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 13892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 13893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 13894 // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 13895 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D, 13896 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13897 // GIR_Coverage, 639, 13898 GIR_Done, 13899 // Label 908: @33900 13900 GIM_Reject, 13901 // Label 905: @33901 13902 GIM_Reject, 13903 // Label 888: @33902 13904 GIM_Try, /*On fail goto*//*Label 909*/ 34060, 13905 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13906 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13907 GIM_Try, /*On fail goto*//*Label 910*/ 33974, // Rule ID 2347 // 13908 GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, 13909 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, 13910 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 13911 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13912 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 13913 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 13914 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 13915 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 13916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 13917 GIM_CheckIsSafeToFold, /*InsnID*/1, 13918 // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 13919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W, 13920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd 13921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd 13922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 13923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 13924 GIR_EraseFromParent, /*InsnID*/0, 13925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13926 // GIR_Coverage, 2347, 13927 GIR_Done, 13928 // Label 910: @33974 13929 GIM_Try, /*On fail goto*//*Label 911*/ 34036, // Rule ID 1900 // 13930 GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, 13931 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, 13932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 13933 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 13934 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13935 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 13936 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 13937 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 13938 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 13939 GIM_CheckIsSafeToFold, /*InsnID*/1, 13940 // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 13941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W, 13942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd 13943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd 13944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 13945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 13946 GIR_EraseFromParent, /*InsnID*/0, 13947 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13948 // GIR_Coverage, 1900, 13949 GIR_Done, 13950 // Label 911: @34036 13951 GIM_Try, /*On fail goto*//*Label 912*/ 34059, // Rule ID 638 // 13952 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 13953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 13954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 13955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 13956 // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 13957 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_W, 13958 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13959 // GIR_Coverage, 638, 13960 GIR_Done, 13961 // Label 912: @34059 13962 GIM_Reject, 13963 // Label 909: @34060 13964 GIM_Reject, 13965 // Label 889: @34061 13966 GIM_Reject, 13967 // Label 25: @34062 13968 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 917*/ 34637, 13969 /*GILLT_s32*//*Label 913*/ 34074, 13970 /*GILLT_s64*//*Label 914*/ 34217, 0, 13971 /*GILLT_v2s64*//*Label 915*/ 34443, 0, 13972 /*GILLT_v4s32*//*Label 916*/ 34540, 13973 // Label 913: @34074 13974 GIM_Try, /*On fail goto*//*Label 918*/ 34216, 13975 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13976 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 13978 GIM_Try, /*On fail goto*//*Label 919*/ 34145, // Rule ID 146 // 13979 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, 13980 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 13981 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 13982 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 13983 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 13984 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 13985 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 13987 GIM_CheckIsSafeToFold, /*InsnID*/1, 13988 // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 13989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_S, 13990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 13991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr 13992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs 13993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft 13994 GIR_EraseFromParent, /*InsnID*/0, 13995 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13996 // GIR_Coverage, 146, 13997 GIR_Done, 13998 // Label 919: @34145 13999 GIM_Try, /*On fail goto*//*Label 920*/ 34164, // Rule ID 142 // 14000 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 14001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14003 // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14004 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S, 14005 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14006 // GIR_Coverage, 142, 14007 GIR_Done, 14008 // Label 920: @34164 14009 GIM_Try, /*On fail goto*//*Label 921*/ 34183, // Rule ID 1092 // 14010 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, 14011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14013 // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14014 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S_MM, 14015 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14016 // GIR_Coverage, 1092, 14017 GIR_Done, 14018 // Label 921: @34183 14019 GIM_Try, /*On fail goto*//*Label 922*/ 34215, // Rule ID 1146 // 14020 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, 14021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14023 // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) 14024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUB_S_MMR6, 14025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft 14027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs 14028 GIR_EraseFromParent, /*InsnID*/0, 14029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14030 // GIR_Coverage, 1146, 14031 GIR_Done, 14032 // Label 922: @34215 14033 GIM_Reject, 14034 // Label 918: @34216 14035 GIM_Reject, 14036 // Label 914: @34217 14037 GIM_Try, /*On fail goto*//*Label 923*/ 34442, 14038 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14039 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 14040 GIM_Try, /*On fail goto*//*Label 924*/ 34288, // Rule ID 148 // 14041 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 14042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14043 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14044 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 14045 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14046 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14047 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14048 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14050 GIM_CheckIsSafeToFold, /*InsnID*/1, 14051 // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14052 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D32, 14053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr 14055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs 14056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft 14057 GIR_EraseFromParent, /*InsnID*/0, 14058 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14059 // GIR_Coverage, 148, 14060 GIR_Done, 14061 // Label 924: @34288 14062 GIM_Try, /*On fail goto*//*Label 925*/ 34349, // Rule ID 150 // 14063 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, 14064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 14065 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14066 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 14067 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14068 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14069 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14070 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14072 GIM_CheckIsSafeToFold, /*InsnID*/1, 14073 // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 14074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D64, 14075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr 14077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs 14078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft 14079 GIR_EraseFromParent, /*InsnID*/0, 14080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14081 // GIR_Coverage, 150, 14082 GIR_Done, 14083 // Label 925: @34349 14084 GIM_Try, /*On fail goto*//*Label 926*/ 34372, // Rule ID 143 // 14085 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, 14086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14089 // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14090 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32, 14091 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14092 // GIR_Coverage, 143, 14093 GIR_Done, 14094 // Label 926: @34372 14095 GIM_Try, /*On fail goto*//*Label 927*/ 34395, // Rule ID 144 // 14096 GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, 14097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 14098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14100 // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 14101 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64, 14102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14103 // GIR_Coverage, 144, 14104 GIR_Done, 14105 // Label 927: @34395 14106 GIM_Try, /*On fail goto*//*Label 928*/ 34418, // Rule ID 1099 // 14107 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, 14108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14111 // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14112 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32_MM, 14113 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14114 // GIR_Coverage, 1099, 14115 GIR_Done, 14116 // Label 928: @34418 14117 GIM_Try, /*On fail goto*//*Label 929*/ 34441, // Rule ID 1100 // 14118 GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, 14119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 14120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14122 // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 14123 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64_MM, 14124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14125 // GIR_Coverage, 1100, 14126 GIR_Done, 14127 // Label 929: @34441 14128 GIM_Reject, 14129 // Label 923: @34442 14130 GIM_Reject, 14131 // Label 915: @34443 14132 GIM_Try, /*On fail goto*//*Label 930*/ 34539, 14133 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14134 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 14135 GIM_Try, /*On fail goto*//*Label 931*/ 34515, // Rule ID 1899 // 14136 GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, 14137 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, 14138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14139 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 14140 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 14141 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 14142 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, 14143 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14144 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 14145 GIM_CheckIsSafeToFold, /*InsnID*/1, 14146 // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 14147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_D, 14148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd 14149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd 14150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 14151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 14152 GIR_EraseFromParent, /*InsnID*/0, 14153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14154 // GIR_Coverage, 1899, 14155 GIR_Done, 14156 // Label 931: @34515 14157 GIM_Try, /*On fail goto*//*Label 932*/ 34538, // Rule ID 727 // 14158 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 14160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 14162 // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 14163 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D, 14164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14165 // GIR_Coverage, 727, 14166 GIR_Done, 14167 // Label 932: @34538 14168 GIM_Reject, 14169 // Label 930: @34539 14170 GIM_Reject, 14171 // Label 916: @34540 14172 GIM_Try, /*On fail goto*//*Label 933*/ 34636, 14173 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14174 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 14175 GIM_Try, /*On fail goto*//*Label 934*/ 34612, // Rule ID 1898 // 14176 GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, 14177 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, 14178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14179 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 14180 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 14181 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 14182 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 14183 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14184 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 14185 GIM_CheckIsSafeToFold, /*InsnID*/1, 14186 // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 14187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_W, 14188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd 14189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd 14190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws 14191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt 14192 GIR_EraseFromParent, /*InsnID*/0, 14193 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14194 // GIR_Coverage, 1898, 14195 GIR_Done, 14196 // Label 934: @34612 14197 GIM_Try, /*On fail goto*//*Label 935*/ 34635, // Rule ID 726 // 14198 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 14200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 14202 // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 14203 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_W, 14204 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14205 // GIR_Coverage, 726, 14206 GIR_Done, 14207 // Label 935: @34635 14208 GIM_Reject, 14209 // Label 933: @34636 14210 GIM_Reject, 14211 // Label 917: @34637 14212 GIM_Reject, 14213 // Label 26: @34638 14214 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 940*/ 35074, 14215 /*GILLT_s32*//*Label 936*/ 34650, 14216 /*GILLT_s64*//*Label 937*/ 34720, 0, 14217 /*GILLT_v2s64*//*Label 938*/ 34824, 0, 14218 /*GILLT_v4s32*//*Label 939*/ 34949, 14219 // Label 936: @34650 14220 GIM_Try, /*On fail goto*//*Label 941*/ 34719, 14221 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14222 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 14223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 14224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14226 GIM_Try, /*On fail goto*//*Label 942*/ 34683, // Rule ID 139 // 14227 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 14228 // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14229 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S, 14230 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14231 // GIR_Coverage, 139, 14232 GIR_Done, 14233 // Label 942: @34683 14234 GIM_Try, /*On fail goto*//*Label 943*/ 34694, // Rule ID 1091 // 14235 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, 14236 // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14237 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S_MM, 14238 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14239 // GIR_Coverage, 1091, 14240 GIR_Done, 14241 // Label 943: @34694 14242 GIM_Try, /*On fail goto*//*Label 944*/ 34718, // Rule ID 1147 // 14243 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, 14244 // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) 14245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMUL_S_MMR6, 14246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft 14248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs 14249 GIR_EraseFromParent, /*InsnID*/0, 14250 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14251 // GIR_Coverage, 1147, 14252 GIR_Done, 14253 // Label 944: @34718 14254 GIM_Reject, 14255 // Label 941: @34719 14256 GIM_Reject, 14257 // Label 937: @34720 14258 GIM_Try, /*On fail goto*//*Label 945*/ 34823, 14259 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14260 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 14261 GIM_Try, /*On fail goto*//*Label 946*/ 34753, // Rule ID 140 // 14262 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, 14263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14266 // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14267 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32, 14268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14269 // GIR_Coverage, 140, 14270 GIR_Done, 14271 // Label 946: @34753 14272 GIM_Try, /*On fail goto*//*Label 947*/ 34776, // Rule ID 141 // 14273 GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, 14274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 14275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14277 // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 14278 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64, 14279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14280 // GIR_Coverage, 141, 14281 GIR_Done, 14282 // Label 947: @34776 14283 GIM_Try, /*On fail goto*//*Label 948*/ 34799, // Rule ID 1097 // 14284 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, 14285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14288 // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14289 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32_MM, 14290 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14291 // GIR_Coverage, 1097, 14292 GIR_Done, 14293 // Label 948: @34799 14294 GIM_Try, /*On fail goto*//*Label 949*/ 34822, // Rule ID 1098 // 14295 GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, 14296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 14297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14299 // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 14300 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64_MM, 14301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14302 // GIR_Coverage, 1098, 14303 GIR_Done, 14304 // Label 949: @34822 14305 GIM_Reject, 14306 // Label 945: @34823 14307 GIM_Reject, 14308 // Label 938: @34824 14309 GIM_Try, /*On fail goto*//*Label 950*/ 34948, 14310 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14311 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 14312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 14313 GIM_Try, /*On fail goto*//*Label 951*/ 34883, // Rule ID 2289 // 14314 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14315 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14316 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, 14317 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 14318 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 14320 GIM_CheckIsSafeToFold, /*InsnID*/1, 14321 // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 14322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D, 14323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 14324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 14325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt 14326 GIR_EraseFromParent, /*InsnID*/0, 14327 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14328 // GIR_Coverage, 2289, 14329 GIR_Done, 14330 // Label 951: @34883 14331 GIM_Try, /*On fail goto*//*Label 952*/ 34928, // Rule ID 669 // 14332 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14334 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 14335 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, 14336 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 14337 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14338 GIM_CheckIsSafeToFold, /*InsnID*/1, 14339 // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 14340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D, 14341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 14342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws 14343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt 14344 GIR_EraseFromParent, /*InsnID*/0, 14345 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14346 // GIR_Coverage, 669, 14347 GIR_Done, 14348 // Label 952: @34928 14349 GIM_Try, /*On fail goto*//*Label 953*/ 34947, // Rule ID 705 // 14350 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 14353 // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 14354 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D, 14355 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14356 // GIR_Coverage, 705, 14357 GIR_Done, 14358 // Label 953: @34947 14359 GIM_Reject, 14360 // Label 950: @34948 14361 GIM_Reject, 14362 // Label 939: @34949 14363 GIM_Try, /*On fail goto*//*Label 954*/ 35073, 14364 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14365 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 14366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 14367 GIM_Try, /*On fail goto*//*Label 955*/ 35008, // Rule ID 2288 // 14368 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14369 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14370 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, 14371 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 14372 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 14374 GIM_CheckIsSafeToFold, /*InsnID*/1, 14375 // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 14376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W, 14377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 14378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws 14379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt 14380 GIR_EraseFromParent, /*InsnID*/0, 14381 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14382 // GIR_Coverage, 2288, 14383 GIR_Done, 14384 // Label 955: @35008 14385 GIM_Try, /*On fail goto*//*Label 956*/ 35053, // Rule ID 668 // 14386 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14388 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 14389 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, 14390 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 14391 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14392 GIM_CheckIsSafeToFold, /*InsnID*/1, 14393 // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 14394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W, 14395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd 14396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws 14397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt 14398 GIR_EraseFromParent, /*InsnID*/0, 14399 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14400 // GIR_Coverage, 668, 14401 GIR_Done, 14402 // Label 956: @35053 14403 GIM_Try, /*On fail goto*//*Label 957*/ 35072, // Rule ID 704 // 14404 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 14407 // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 14408 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_W, 14409 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14410 // GIR_Coverage, 704, 14411 GIR_Done, 14412 // Label 957: @35072 14413 GIM_Reject, 14414 // Label 954: @35073 14415 GIM_Reject, 14416 // Label 940: @35074 14417 GIM_Reject, 14418 // Label 27: @35075 14419 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 960*/ 35164, 14420 /*GILLT_v2s64*//*Label 958*/ 35084, 0, 14421 /*GILLT_v4s32*//*Label 959*/ 35124, 14422 // Label 958: @35084 14423 GIM_Try, /*On fail goto*//*Label 961*/ 35123, // Rule ID 693 // 14424 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14425 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14426 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 14427 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 14428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 14429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 14431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, 14432 // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 14433 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_D, 14434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14435 // GIR_Coverage, 693, 14436 GIR_Done, 14437 // Label 961: @35123 14438 GIM_Reject, 14439 // Label 959: @35124 14440 GIM_Try, /*On fail goto*//*Label 962*/ 35163, // Rule ID 692 // 14441 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14442 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14443 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 14444 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 14445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 14446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 14448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, 14449 // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 14450 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_W, 14451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14452 // GIR_Coverage, 692, 14453 GIR_Done, 14454 // Label 962: @35163 14455 GIM_Reject, 14456 // Label 960: @35164 14457 GIM_Reject, 14458 // Label 28: @35165 14459 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 967*/ 35415, 14460 /*GILLT_s32*//*Label 963*/ 35177, 14461 /*GILLT_s64*//*Label 964*/ 35247, 0, 14462 /*GILLT_v2s64*//*Label 965*/ 35351, 0, 14463 /*GILLT_v4s32*//*Label 966*/ 35383, 14464 // Label 963: @35177 14465 GIM_Try, /*On fail goto*//*Label 968*/ 35246, 14466 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14467 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 14468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 14469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14471 GIM_Try, /*On fail goto*//*Label 969*/ 35210, // Rule ID 136 // 14472 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 14473 // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14474 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S, 14475 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14476 // GIR_Coverage, 136, 14477 GIR_Done, 14478 // Label 969: @35210 14479 GIM_Try, /*On fail goto*//*Label 970*/ 35221, // Rule ID 1090 // 14480 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, 14481 // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14482 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S_MM, 14483 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14484 // GIR_Coverage, 1090, 14485 GIR_Done, 14486 // Label 970: @35221 14487 GIM_Try, /*On fail goto*//*Label 971*/ 35245, // Rule ID 1148 // 14488 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, 14489 // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) 14490 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FDIV_S_MMR6, 14491 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft 14493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs 14494 GIR_EraseFromParent, /*InsnID*/0, 14495 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14496 // GIR_Coverage, 1148, 14497 GIR_Done, 14498 // Label 971: @35245 14499 GIM_Reject, 14500 // Label 968: @35246 14501 GIM_Reject, 14502 // Label 964: @35247 14503 GIM_Try, /*On fail goto*//*Label 972*/ 35350, 14504 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14505 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 14506 GIM_Try, /*On fail goto*//*Label 973*/ 35280, // Rule ID 137 // 14507 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, 14508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14511 // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14512 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32, 14513 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14514 // GIR_Coverage, 137, 14515 GIR_Done, 14516 // Label 973: @35280 14517 GIM_Try, /*On fail goto*//*Label 974*/ 35303, // Rule ID 138 // 14518 GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, 14519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 14520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14522 // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 14523 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64, 14524 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14525 // GIR_Coverage, 138, 14526 GIR_Done, 14527 // Label 974: @35303 14528 GIM_Try, /*On fail goto*//*Label 975*/ 35326, // Rule ID 1095 // 14529 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, 14530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14533 // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14534 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32_MM, 14535 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14536 // GIR_Coverage, 1095, 14537 GIR_Done, 14538 // Label 975: @35326 14539 GIM_Try, /*On fail goto*//*Label 976*/ 35349, // Rule ID 1096 // 14540 GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, 14541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 14542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14544 // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 14545 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64_MM, 14546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14547 // GIR_Coverage, 1096, 14548 GIR_Done, 14549 // Label 976: @35349 14550 GIM_Reject, 14551 // Label 972: @35350 14552 GIM_Reject, 14553 // Label 965: @35351 14554 GIM_Try, /*On fail goto*//*Label 977*/ 35382, // Rule ID 665 // 14555 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14556 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14557 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 14558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 14559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, 14561 // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) 14562 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D, 14563 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14564 // GIR_Coverage, 665, 14565 GIR_Done, 14566 // Label 977: @35382 14567 GIM_Reject, 14568 // Label 966: @35383 14569 GIM_Try, /*On fail goto*//*Label 978*/ 35414, // Rule ID 664 // 14570 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14571 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14572 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 14573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 14574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, 14576 // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) 14577 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_W, 14578 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14579 // GIR_Coverage, 664, 14580 GIR_Done, 14581 // Label 978: @35414 14582 GIM_Reject, 14583 // Label 967: @35415 14584 GIM_Reject, 14585 // Label 29: @35416 14586 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 981*/ 35473, 14587 /*GILLT_v2s64*//*Label 979*/ 35425, 0, 14588 /*GILLT_v4s32*//*Label 980*/ 35449, 14589 // Label 979: @35425 14590 GIM_Try, /*On fail goto*//*Label 982*/ 35448, // Rule ID 671 // 14591 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14592 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 14594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14595 // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) 14596 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_D_1_PSEUDO, 14597 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14598 // GIR_Coverage, 671, 14599 GIR_Done, 14600 // Label 982: @35448 14601 GIM_Reject, 14602 // Label 980: @35449 14603 GIM_Try, /*On fail goto*//*Label 983*/ 35472, // Rule ID 670 // 14604 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14605 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 14607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14608 // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) 14609 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_W_1_PSEUDO, 14610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14611 // GIR_Coverage, 670, 14612 GIR_Done, 14613 // Label 983: @35472 14614 GIM_Reject, 14615 // Label 981: @35473 14616 GIM_Reject, 14617 // Label 30: @35474 14618 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 986*/ 35531, 14619 /*GILLT_v2s64*//*Label 984*/ 35483, 0, 14620 /*GILLT_v4s32*//*Label 985*/ 35507, 14621 // Label 984: @35483 14622 GIM_Try, /*On fail goto*//*Label 987*/ 35506, // Rule ID 691 // 14623 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14624 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 14626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 14627 // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) 14628 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_D, 14629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14630 // GIR_Coverage, 691, 14631 GIR_Done, 14632 // Label 987: @35506 14633 GIM_Reject, 14634 // Label 985: @35507 14635 GIM_Try, /*On fail goto*//*Label 988*/ 35530, // Rule ID 690 // 14636 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 14637 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 14639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 14640 // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) 14641 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_W, 14642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14643 // GIR_Coverage, 690, 14644 GIR_Done, 14645 // Label 988: @35530 14646 GIM_Reject, 14647 // Label 986: @35531 14648 GIM_Reject, 14649 // Label 31: @35532 14650 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 991*/ 36827, 14651 /*GILLT_s32*//*Label 989*/ 35540, 14652 /*GILLT_s64*//*Label 990*/ 36041, 14653 // Label 989: @35540 14654 GIM_Try, /*On fail goto*//*Label 992*/ 36040, 14655 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 14657 GIM_Try, /*On fail goto*//*Label 993*/ 35624, // Rule ID 1414 // 14658 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, 14659 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14660 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14661 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14662 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14663 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 14664 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14665 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14666 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 14667 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14668 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14669 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14670 GIM_CheckIsSafeToFold, /*InsnID*/1, 14671 GIM_CheckIsSafeToFold, /*InsnID*/2, 14672 // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S, 14674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 14676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14678 GIR_EraseFromParent, /*InsnID*/0, 14679 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14680 // GIR_Coverage, 1414, 14681 GIR_Done, 14682 // Label 993: @35624 14683 GIM_Try, /*On fail goto*//*Label 994*/ 35698, // Rule ID 2144 // 14684 GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6, 14685 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14686 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14687 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14688 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14689 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 14690 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14691 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14692 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 14693 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14694 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14695 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14696 GIM_CheckIsSafeToFold, /*InsnID*/1, 14697 GIM_CheckIsSafeToFold, /*InsnID*/2, 14698 // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM, 14700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 14702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14704 GIR_EraseFromParent, /*InsnID*/0, 14705 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14706 // GIR_Coverage, 2144, 14707 GIR_Done, 14708 // Label 994: @35698 14709 GIM_Try, /*On fail goto*//*Label 995*/ 35772, // Rule ID 2323 // 14710 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, 14711 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14712 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14713 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14714 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14715 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14716 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 14717 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14718 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14719 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 14720 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14721 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14722 GIM_CheckIsSafeToFold, /*InsnID*/1, 14723 GIM_CheckIsSafeToFold, /*InsnID*/2, 14724 // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S, 14726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr 14728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14730 GIR_EraseFromParent, /*InsnID*/0, 14731 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14732 // GIR_Coverage, 2323, 14733 GIR_Done, 14734 // Label 995: @35772 14735 GIM_Try, /*On fail goto*//*Label 996*/ 35846, // Rule ID 2420 // 14736 GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6, 14737 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14738 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14739 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14740 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14741 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14742 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 14743 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14744 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14745 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 14746 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14747 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14748 GIM_CheckIsSafeToFold, /*InsnID*/1, 14749 GIM_CheckIsSafeToFold, /*InsnID*/2, 14750 // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM, 14752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr 14754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14756 GIR_EraseFromParent, /*InsnID*/0, 14757 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14758 // GIR_Coverage, 2420, 14759 GIR_Done, 14760 // Label 996: @35846 14761 GIM_Try, /*On fail goto*//*Label 997*/ 35920, // Rule ID 1415 // 14762 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, 14763 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14764 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, 14765 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14766 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14767 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 14768 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14769 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14770 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 14771 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14772 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14773 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14774 GIM_CheckIsSafeToFold, /*InsnID*/1, 14775 GIM_CheckIsSafeToFold, /*InsnID*/2, 14776 // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S, 14778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 14780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14782 GIR_EraseFromParent, /*InsnID*/0, 14783 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14784 // GIR_Coverage, 1415, 14785 GIR_Done, 14786 // Label 997: @35920 14787 GIM_Try, /*On fail goto*//*Label 998*/ 35994, // Rule ID 2145 // 14788 GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6, 14789 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14790 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, 14791 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 14792 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 14793 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 14794 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14795 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 14796 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 14797 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14798 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14799 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, 14800 GIM_CheckIsSafeToFold, /*InsnID*/1, 14801 GIM_CheckIsSafeToFold, /*InsnID*/2, 14802 // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) 14803 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S_MM, 14804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 14806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14808 GIR_EraseFromParent, /*InsnID*/0, 14809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14810 // GIR_Coverage, 2145, 14811 GIR_Done, 14812 // Label 998: @35994 14813 GIM_Try, /*On fail goto*//*Label 999*/ 36009, // Rule ID 111 // 14814 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat, 14815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14816 // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) 14817 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S, 14818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14819 // GIR_Coverage, 111, 14820 GIR_Done, 14821 // Label 999: @36009 14822 GIM_Try, /*On fail goto*//*Label 1000*/ 36024, // Rule ID 1112 // 14823 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, 14824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14825 // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) 14826 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MM, 14827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14828 // GIR_Coverage, 1112, 14829 GIR_Done, 14830 // Label 1000: @36024 14831 GIM_Try, /*On fail goto*//*Label 1001*/ 36039, // Rule ID 1149 // 14832 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, 14833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 14834 // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) 14835 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MMR6, 14836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14837 // GIR_Coverage, 1149, 14838 GIR_Done, 14839 // Label 1001: @36039 14840 GIM_Reject, 14841 // Label 992: @36040 14842 GIM_Reject, 14843 // Label 990: @36041 14844 GIM_Try, /*On fail goto*//*Label 1002*/ 36826, 14845 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14846 GIM_Try, /*On fail goto*//*Label 1003*/ 36125, // Rule ID 1416 // 14847 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 14848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14849 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14850 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14851 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14852 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14853 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 14854 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14855 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14856 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 14857 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14858 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14859 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14860 GIM_CheckIsSafeToFold, /*InsnID*/1, 14861 GIM_CheckIsSafeToFold, /*InsnID*/2, 14862 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32, 14864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 14866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14868 GIR_EraseFromParent, /*InsnID*/0, 14869 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14870 // GIR_Coverage, 1416, 14871 GIR_Done, 14872 // Label 1003: @36125 14873 GIM_Try, /*On fail goto*//*Label 1004*/ 36203, // Rule ID 1418 // 14874 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, 14875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 14876 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14877 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14878 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14879 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14880 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 14881 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14882 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14883 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 14884 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14885 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14886 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14887 GIM_CheckIsSafeToFold, /*InsnID*/1, 14888 GIM_CheckIsSafeToFold, /*InsnID*/2, 14889 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 14890 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64, 14891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 14893 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14895 GIR_EraseFromParent, /*InsnID*/0, 14896 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14897 // GIR_Coverage, 1418, 14898 GIR_Done, 14899 // Label 1004: @36203 14900 GIM_Try, /*On fail goto*//*Label 1005*/ 36281, // Rule ID 2146 // 14901 GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6, 14902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14903 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14904 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14905 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14906 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14907 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 14908 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14909 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14910 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 14911 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14912 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14913 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14914 GIM_CheckIsSafeToFold, /*InsnID*/1, 14915 GIM_CheckIsSafeToFold, /*InsnID*/2, 14916 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM, 14918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 14920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14922 GIR_EraseFromParent, /*InsnID*/0, 14923 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14924 // GIR_Coverage, 2146, 14925 GIR_Done, 14926 // Label 1005: @36281 14927 GIM_Try, /*On fail goto*//*Label 1006*/ 36359, // Rule ID 2324 // 14928 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 14929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14930 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14931 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14932 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14933 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14934 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14935 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 14936 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14937 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14938 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 14939 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14940 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14941 GIM_CheckIsSafeToFold, /*InsnID*/1, 14942 GIM_CheckIsSafeToFold, /*InsnID*/2, 14943 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32, 14945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr 14947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14949 GIR_EraseFromParent, /*InsnID*/0, 14950 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14951 // GIR_Coverage, 2324, 14952 GIR_Done, 14953 // Label 1006: @36359 14954 GIM_Try, /*On fail goto*//*Label 1007*/ 36437, // Rule ID 2325 // 14955 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, 14956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 14957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14958 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14959 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14960 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14961 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14962 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 14963 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14964 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14965 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 14966 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 14967 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 14968 GIM_CheckIsSafeToFold, /*InsnID*/1, 14969 GIM_CheckIsSafeToFold, /*InsnID*/2, 14970 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 14971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64, 14972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 14973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr 14974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 14975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 14976 GIR_EraseFromParent, /*InsnID*/0, 14977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14978 // GIR_Coverage, 2325, 14979 GIR_Done, 14980 // Label 1007: @36437 14981 GIM_Try, /*On fail goto*//*Label 1008*/ 36515, // Rule ID 2421 // 14982 GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6, 14983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 14984 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14985 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, 14986 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 14987 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 14988 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14989 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 14990 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 14991 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 14992 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 14993 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 14994 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 14995 GIM_CheckIsSafeToFold, /*InsnID*/1, 14996 GIM_CheckIsSafeToFold, /*InsnID*/2, 14997 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 14998 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM, 14999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 15000 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr 15001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 15002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 15003 GIR_EraseFromParent, /*InsnID*/0, 15004 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15005 // GIR_Coverage, 2421, 15006 GIR_Done, 15007 // Label 1008: @36515 15008 GIM_Try, /*On fail goto*//*Label 1009*/ 36593, // Rule ID 1417 // 15009 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, 15010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 15011 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15012 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, 15013 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 15014 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 15015 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 15016 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 15017 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 15018 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 15019 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 15020 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 15021 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 15022 GIM_CheckIsSafeToFold, /*InsnID*/1, 15023 GIM_CheckIsSafeToFold, /*InsnID*/2, 15024 // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 15025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32, 15026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 15027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 15028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 15029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 15030 GIR_EraseFromParent, /*InsnID*/0, 15031 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15032 // GIR_Coverage, 1417, 15033 GIR_Done, 15034 // Label 1009: @36593 15035 GIM_Try, /*On fail goto*//*Label 1010*/ 36671, // Rule ID 1419 // 15036 GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, 15037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 15038 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15039 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, 15040 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 15041 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 15042 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 15043 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 15044 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 15045 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 15046 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 15047 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 15048 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, 15049 GIM_CheckIsSafeToFold, /*InsnID*/1, 15050 GIM_CheckIsSafeToFold, /*InsnID*/2, 15051 // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) 15052 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D64, 15053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 15054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 15055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 15056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 15057 GIR_EraseFromParent, /*InsnID*/0, 15058 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15059 // GIR_Coverage, 1419, 15060 GIR_Done, 15061 // Label 1010: @36671 15062 GIM_Try, /*On fail goto*//*Label 1011*/ 36749, // Rule ID 2147 // 15063 GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6, 15064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 15065 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 15066 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, 15067 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 15068 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 15069 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 15070 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, 15071 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 15072 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 15073 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 15074 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 15075 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, 15076 GIM_CheckIsSafeToFold, /*InsnID*/1, 15077 GIM_CheckIsSafeToFold, /*InsnID*/2, 15078 // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) 15079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32_MM, 15080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd 15081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr 15082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs 15083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft 15084 GIR_EraseFromParent, /*InsnID*/0, 15085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15086 // GIR_Coverage, 2147, 15087 GIR_Done, 15088 // Label 1011: @36749 15089 GIM_Try, /*On fail goto*//*Label 1012*/ 36768, // Rule ID 112 // 15090 GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, 15091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 15092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 15093 // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) 15094 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32, 15095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15096 // GIR_Coverage, 112, 15097 GIR_Done, 15098 // Label 1012: @36768 15099 GIM_Try, /*On fail goto*//*Label 1013*/ 36787, // Rule ID 113 // 15100 GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, 15101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 15102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 15103 // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) 15104 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64, 15105 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15106 // GIR_Coverage, 113, 15107 GIR_Done, 15108 // Label 1013: @36787 15109 GIM_Try, /*On fail goto*//*Label 1014*/ 36806, // Rule ID 1113 // 15110 GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, 15111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 15112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 15113 // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) 15114 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32_MM, 15115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15116 // GIR_Coverage, 1113, 15117 GIR_Done, 15118 // Label 1014: @36806 15119 GIM_Try, /*On fail goto*//*Label 1015*/ 36825, // Rule ID 1114 // 15120 GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, 15121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 15122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 15123 // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) 15124 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64_MM, 15125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15126 // GIR_Coverage, 1114, 15127 GIR_Done, 15128 // Label 1015: @36825 15129 GIM_Reject, 15130 // Label 1002: @36826 15131 GIM_Reject, 15132 // Label 991: @36827 15133 GIM_Reject, 15134 // Label 32: @36828 15135 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1018*/ 36976, 15136 /*GILLT_s32*//*Label 1016*/ 36836, 15137 /*GILLT_s64*//*Label 1017*/ 36860, 15138 // Label 1016: @36836 15139 GIM_Try, /*On fail goto*//*Label 1019*/ 36859, // Rule ID 1024 // 15140 GIM_CheckFeatures, GIFBS_HasMSA, 15141 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 15142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 15143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID, 15144 // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) 15145 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_W_PSEUDO, 15146 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15147 // GIR_Coverage, 1024, 15148 GIR_Done, 15149 // Label 1019: @36859 15150 GIM_Reject, 15151 // Label 1017: @36860 15152 GIM_Try, /*On fail goto*//*Label 1020*/ 36883, // Rule ID 1026 // 15153 GIM_CheckFeatures, GIFBS_HasMSA, 15154 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 15155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 15156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID, 15157 // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) 15158 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_D_PSEUDO, 15159 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15160 // GIR_Coverage, 1026, 15161 GIR_Done, 15162 // Label 1020: @36883 15163 GIM_Try, /*On fail goto*//*Label 1021*/ 36906, // Rule ID 1403 // 15164 GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips, 15165 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 15167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 15168 // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) 15169 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S, 15170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15171 // GIR_Coverage, 1403, 15172 GIR_Done, 15173 // Label 1021: @36906 15174 GIM_Try, /*On fail goto*//*Label 1022*/ 36929, // Rule ID 1413 // 15175 GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips, 15176 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 15178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 15179 // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) 15180 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S, 15181 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15182 // GIR_Coverage, 1413, 15183 GIR_Done, 15184 // Label 1022: @36929 15185 GIM_Try, /*On fail goto*//*Label 1023*/ 36952, // Rule ID 2155 // 15186 GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit, 15187 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 15189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 15190 // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) 15191 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S_MM, 15192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15193 // GIR_Coverage, 2155, 15194 GIR_Done, 15195 // Label 1023: @36952 15196 GIM_Try, /*On fail goto*//*Label 1024*/ 36975, // Rule ID 2157 // 15197 GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit, 15198 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 15200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 15201 // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) 15202 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S_MM, 15203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15204 // GIR_Coverage, 2157, 15205 GIR_Done, 15206 // Label 1024: @36975 15207 GIM_Reject, 15208 // Label 1018: @36976 15209 GIM_Reject, 15210 // Label 33: @36977 15211 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1027*/ 37104, 15212 /*GILLT_s16*//*Label 1025*/ 36985, 15213 /*GILLT_s32*//*Label 1026*/ 37032, 15214 // Label 1025: @36985 15215 GIM_Try, /*On fail goto*//*Label 1028*/ 37008, // Rule ID 1025 // 15216 GIM_CheckFeatures, GIFBS_HasMSA, 15217 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID, 15219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, 15220 // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) 15221 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_W_PSEUDO, 15222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15223 // GIR_Coverage, 1025, 15224 GIR_Done, 15225 // Label 1028: @37008 15226 GIM_Try, /*On fail goto*//*Label 1029*/ 37031, // Rule ID 1027 // 15227 GIM_CheckFeatures, GIFBS_HasMSA, 15228 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID, 15230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 15231 // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) 15232 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_D_PSEUDO, 15233 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15234 // GIR_Coverage, 1027, 15235 GIR_Done, 15236 // Label 1029: @37031 15237 GIM_Reject, 15238 // Label 1026: @37032 15239 GIM_Try, /*On fail goto*//*Label 1030*/ 37103, 15240 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 15242 GIM_Try, /*On fail goto*//*Label 1031*/ 37057, // Rule ID 1402 // 15243 GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips, 15244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 15245 // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) 15246 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32, 15247 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15248 // GIR_Coverage, 1402, 15249 GIR_Done, 15250 // Label 1031: @37057 15251 GIM_Try, /*On fail goto*//*Label 1032*/ 37072, // Rule ID 1412 // 15252 GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips, 15253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 15254 // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) 15255 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64, 15256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15257 // GIR_Coverage, 1412, 15258 GIR_Done, 15259 // Label 1032: @37072 15260 GIM_Try, /*On fail goto*//*Label 1033*/ 37087, // Rule ID 2154 // 15261 GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit, 15262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, 15263 // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) 15264 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64_MM, 15265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15266 // GIR_Coverage, 2154, 15267 GIR_Done, 15268 // Label 1033: @37087 15269 GIM_Try, /*On fail goto*//*Label 1034*/ 37102, // Rule ID 2156 // 15270 GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit, 15271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, 15272 // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) 15273 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32_MM, 15274 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15275 // GIR_Coverage, 2156, 15276 GIR_Done, 15277 // Label 1034: @37102 15278 GIM_Reject, 15279 // Label 1030: @37103 15280 GIM_Reject, 15281 // Label 1027: @37104 15282 GIM_Reject, 15283 // Label 34: @37105 15284 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1037*/ 37162, 15285 /*GILLT_v2s64*//*Label 1035*/ 37114, 0, 15286 /*GILLT_v4s32*//*Label 1036*/ 37138, 15287 // Label 1035: @37114 15288 GIM_Try, /*On fail goto*//*Label 1038*/ 37137, // Rule ID 745 // 15289 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 15290 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 15292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 15293 // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) 15294 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_D, 15295 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15296 // GIR_Coverage, 745, 15297 GIR_Done, 15298 // Label 1038: @37137 15299 GIM_Reject, 15300 // Label 1036: @37138 15301 GIM_Try, /*On fail goto*//*Label 1039*/ 37161, // Rule ID 744 // 15302 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 15303 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 15305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 15306 // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) 15307 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_W, 15308 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15309 // GIR_Coverage, 744, 15310 GIR_Done, 15311 // Label 1039: @37161 15312 GIM_Reject, 15313 // Label 1037: @37162 15314 GIM_Reject, 15315 // Label 35: @37163 15316 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1042*/ 37220, 15317 /*GILLT_v2s64*//*Label 1040*/ 37172, 0, 15318 /*GILLT_v4s32*//*Label 1041*/ 37196, 15319 // Label 1040: @37172 15320 GIM_Try, /*On fail goto*//*Label 1043*/ 37195, // Rule ID 747 // 15321 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 15322 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 15324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 15325 // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) 15326 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_D, 15327 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15328 // GIR_Coverage, 747, 15329 GIR_Done, 15330 // Label 1043: @37195 15331 GIM_Reject, 15332 // Label 1041: @37196 15333 GIM_Try, /*On fail goto*//*Label 1044*/ 37219, // Rule ID 746 // 15334 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 15335 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 15337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 15338 // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) 15339 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_W, 15340 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15341 // GIR_Coverage, 746, 15342 GIR_Done, 15343 // Label 1044: @37219 15344 GIM_Reject, 15345 // Label 1042: @37220 15346 GIM_Reject, 15347 // Label 36: @37221 15348 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1049*/ 37373, 15349 /*GILLT_s32*//*Label 1045*/ 37233, 15350 /*GILLT_s64*//*Label 1046*/ 37255, 0, 15351 /*GILLT_v2s64*//*Label 1047*/ 37325, 0, 15352 /*GILLT_v4s32*//*Label 1048*/ 37349, 15353 // Label 1045: @37233 15354 GIM_Try, /*On fail goto*//*Label 1050*/ 37254, // Rule ID 1397 // 15355 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, 15357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 15358 // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) 15359 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_S_W, 15360 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15361 // GIR_Coverage, 1397, 15362 GIR_Done, 15363 // Label 1050: @37254 15364 GIM_Reject, 15365 // Label 1046: @37255 15366 GIM_Try, /*On fail goto*//*Label 1051*/ 37278, // Rule ID 1400 // 15367 GIM_CheckFeatures, GIFBS_NotFP64bit, 15368 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, 15370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 15371 // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) 15372 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D32_W, 15373 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15374 // GIR_Coverage, 1400, 15375 GIR_Done, 15376 // Label 1051: @37278 15377 GIM_Try, /*On fail goto*//*Label 1052*/ 37301, // Rule ID 1406 // 15378 GIM_CheckFeatures, GIFBS_IsFP64bit, 15379 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 15381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 15382 // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) 15383 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_W, 15384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15385 // GIR_Coverage, 1406, 15386 GIR_Done, 15387 // Label 1052: @37301 15388 GIM_Try, /*On fail goto*//*Label 1053*/ 37324, // Rule ID 1408 // 15389 GIM_CheckFeatures, GIFBS_IsFP64bit, 15390 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, 15392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 15393 // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) 15394 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_L, 15395 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15396 // GIR_Coverage, 1408, 15397 GIR_Done, 15398 // Label 1053: @37324 15399 GIM_Reject, 15400 // Label 1047: @37325 15401 GIM_Try, /*On fail goto*//*Label 1054*/ 37348, // Rule ID 677 // 15402 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 15403 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 15405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 15406 // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) 15407 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_D, 15408 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15409 // GIR_Coverage, 677, 15410 GIR_Done, 15411 // Label 1054: @37348 15412 GIM_Reject, 15413 // Label 1048: @37349 15414 GIM_Try, /*On fail goto*//*Label 1055*/ 37372, // Rule ID 676 // 15415 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 15416 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 15418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 15419 // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) 15420 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_W, 15421 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15422 // GIR_Coverage, 676, 15423 GIR_Done, 15424 // Label 1055: @37372 15425 GIM_Reject, 15426 // Label 1049: @37373 15427 GIM_Reject, 15428 // Label 37: @37374 15429 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1058*/ 37431, 15430 /*GILLT_v2s64*//*Label 1056*/ 37383, 0, 15431 /*GILLT_v4s32*//*Label 1057*/ 37407, 15432 // Label 1056: @37383 15433 GIM_Try, /*On fail goto*//*Label 1059*/ 37406, // Rule ID 679 // 15434 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 15435 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, 15437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, 15438 // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) 15439 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_D, 15440 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15441 // GIR_Coverage, 679, 15442 GIR_Done, 15443 // Label 1059: @37406 15444 GIM_Reject, 15445 // Label 1057: @37407 15446 GIM_Try, /*On fail goto*//*Label 1060*/ 37430, // Rule ID 678 // 15447 GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, 15448 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, 15450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, 15451 // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) 15452 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_W, 15453 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15454 // GIR_Coverage, 678, 15455 GIR_Done, 15456 // Label 1060: @37430 15457 GIM_Reject, 15458 // Label 1058: @37431 15459 GIM_Reject, 15460 // Label 38: @37432 15461 GIM_Try, /*On fail goto*//*Label 1061*/ 37516, 15462 GIM_CheckIsMBB, /*MI*/0, /*Op*/0, 15463 GIM_Try, /*On fail goto*//*Label 1062*/ 37451, // Rule ID 73 // 15464 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC, 15465 // (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target) 15466 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J, 15467 GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, 15468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15469 // GIR_Coverage, 73, 15470 GIR_Done, 15471 // Label 1062: @37451 15472 GIM_Try, /*On fail goto*//*Label 1063*/ 37465, // Rule ID 80 // 15473 GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, 15474 // (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset) 15475 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B, 15476 GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, 15477 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15478 // GIR_Coverage, 80, 15479 GIR_Done, 15480 // Label 1063: @37465 15481 GIM_Try, /*On fail goto*//*Label 1064*/ 37479, // Rule ID 1072 // 15482 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocNotPIC, 15483 // (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target) 15484 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J_MM, 15485 GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, 15486 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15487 // GIR_Coverage, 1072, 15488 GIR_Done, 15489 // Label 1064: @37479 15490 GIM_Try, /*On fail goto*//*Label 1065*/ 37493, // Rule ID 1081 // 15491 GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocPIC, 15492 // (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset) 15493 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B_MM, 15494 GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, 15495 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15496 // GIR_Coverage, 1081, 15497 GIR_Done, 15498 // Label 1065: @37493 15499 GIM_Try, /*On fail goto*//*Label 1066*/ 37504, // Rule ID 1128 // 15500 GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, 15501 // (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset) 15502 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BC_MMR6, 15503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15504 // GIR_Coverage, 1128, 15505 GIR_Done, 15506 // Label 1066: @37504 15507 GIM_Try, /*On fail goto*//*Label 1067*/ 37515, // Rule ID 1775 // 15508 GIM_CheckFeatures, GIFBS_InMips16Mode, 15509 // (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16) 15510 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::Bimm16, 15511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15512 // GIR_Coverage, 1775, 15513 GIR_Done, 15514 // Label 1067: @37515 15515 GIM_Reject, 15516 // Label 1061: @37516 15517 GIM_Reject, 15518 // Label 39: @37517 15519 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1070*/ 37668, 15520 /*GILLT_s32*//*Label 1068*/ 37525, 15521 /*GILLT_s64*//*Label 1069*/ 37619, 15522 // Label 1068: @37525 15523 GIM_Try, /*On fail goto*//*Label 1071*/ 37618, 15524 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, 15526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, 15527 GIM_Try, /*On fail goto*//*Label 1072*/ 37578, // Rule ID 1383 // 15528 GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, 15529 // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] }) 15530 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 15531 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH, 15532 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15533 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt 15534 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 15535 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR, 15536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 15537 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15538 GIR_AddImm, /*InsnID*/0, /*Imm*/16, 15539 GIR_EraseFromParent, /*InsnID*/0, 15540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15541 // GIR_Coverage, 1383, 15542 GIR_Done, 15543 // Label 1072: @37578 15544 GIM_Try, /*On fail goto*//*Label 1073*/ 37617, // Rule ID 2088 // 15545 GIM_CheckFeatures, GIFBS_InMicroMips, 15546 // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] }) 15547 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 15548 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH_MM, 15549 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15550 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt 15551 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 15552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM, 15553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 15554 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15555 GIR_AddImm, /*InsnID*/0, /*Imm*/16, 15556 GIR_EraseFromParent, /*InsnID*/0, 15557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15558 // GIR_Coverage, 2088, 15559 GIR_Done, 15560 // Label 1073: @37617 15561 GIM_Reject, 15562 // Label 1071: @37618 15563 GIM_Reject, 15564 // Label 1069: @37619 15565 GIM_Try, /*On fail goto*//*Label 1074*/ 37667, // Rule ID 1525 // 15566 GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc, 15567 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, 15569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, 15570 // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt)) 15571 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 15572 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSBH, 15573 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15574 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt 15575 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 15576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSHD, 15577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 15578 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15579 GIR_EraseFromParent, /*InsnID*/0, 15580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15581 // GIR_Coverage, 1525, 15582 GIR_Done, 15583 // Label 1074: @37667 15584 GIM_Reject, 15585 // Label 1070: @37668 15586 GIM_Reject, 15587 // Label 40: @37669 15588 GIM_Reject, 15589 }; 15590 return MatchTable0; 15591} 15592#endif // ifdef GET_GLOBALISEL_IMPL 15593#ifdef GET_GLOBALISEL_PREDICATES_DECL 15594PredicateBitset AvailableModuleFeatures; 15595mutable PredicateBitset AvailableFunctionFeatures; 15596PredicateBitset getAvailableFeatures() const { 15597 return AvailableModuleFeatures | AvailableFunctionFeatures; 15598} 15599PredicateBitset 15600computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const; 15601PredicateBitset 15602computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, 15603 const MachineFunction *MF) const; 15604#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL 15605#ifdef GET_GLOBALISEL_PREDICATES_INIT 15606AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), 15607AvailableFunctionFeatures() 15608#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT 15609