1//===-- Nios2InstrFormats.td - Nios2 Instruction Formats ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe NIOS2 instructions format 12// 13// 14//===----------------------------------------------------------------------===// 15 16// Format specifies the encoding used by the instruction. This is part of the 17// ad-hoc solution used to emit machine instruction encodings by our machine 18// code emitter. 19class Format<bits<6> val> { 20 bits<6> Value = val; 21} 22 23def Pseudo : Format<0>; 24// Nios2 R1 instr formats: 25def FrmI : Format<1>; 26def FrmR : Format<2>; 27def FrmJ : Format<3>; 28def FrmOther : Format<4>; // Instruction w/ a custom format 29// Nios2 R2 instr 32-bit formats: 30def FrmL26 : Format<5>; // corresponds to J format in R1 31def FrmF2I16 : Format<6>; // corresponds to I format in R1 32def FrmF2X4I12 : Format<7>; 33def FrmF1X4I12 : Format<8>; 34def FrmF1X4L17 : Format<9>; 35def FrmF3X6L5 : Format<10>; // corresponds to R format in R1 36def FrmF2X6L10 : Format<11>; 37def FrmF3X6 : Format<12>; // corresponds to R format in R1 38def FrmF3X8 : Format<13>; // corresponds to custom format in R1 39// Nios2 R2 instr 16-bit formats: 40def FrmI10 : Format<14>; 41def FrmT1I7 : Format<15>; 42def FrmT2I4 : Format<16>; 43def FrmT1X1I6 : Format<17>; 44def FrmX1I7 : Format<18>; 45def FrmL5I4X1 : Format<19>; 46def FrmT2X1L3 : Format<20>; 47def FrmT2X1I3 : Format<21>; 48def FrmT3X1 : Format<22>; 49def FrmT2X3 : Format<23>; 50def FrmF1X1 : Format<24>; 51def FrmX2L5 : Format<25>; 52def FrmF1I5 : Format<26>; 53def FrmF2 : Format<27>; 54 55//===----------------------------------------------------------------------===// 56// Instruction Predicates: 57//===----------------------------------------------------------------------===// 58 59def isNios2r1 : Predicate<"Subtarget->isNios2r1()">; 60def isNios2r2 : Predicate<"Subtarget->isNios2r2()">; 61 62class PredicateControl { 63 // Predicates related to specific target CPU features 64 list<Predicate> FeaturePredicates = []; 65 // Predicates for the instruction group membership in given ISA 66 list<Predicate> InstrPredicates = []; 67 68 list<Predicate> Predicates = !listconcat(FeaturePredicates, InstrPredicates); 69} 70 71//===----------------------------------------------------------------------===// 72// Base classes for 32-bit, 16-bit and pseudo instructions 73//===----------------------------------------------------------------------===// 74 75class Nios2Inst32<dag outs, dag ins, string asmstr, list<dag> pattern, 76 InstrItinClass itin, Format f>: Instruction, 77 PredicateControl { 78 field bits<32> Inst; 79 Format Form = f; 80 81 let Namespace = "Nios2"; 82 let Size = 4; 83 84 bits<6> Opcode = 0; 85 86 // Bottom 6 bits are the 'opcode' field 87 let Inst{5-0} = Opcode; 88 89 let OutOperandList = outs; 90 let InOperandList = ins; 91 92 let AsmString = asmstr; 93 let Pattern = pattern; 94 let Itinerary = itin; 95 96 // Attributes specific to Nios2 instructions: 97 98 // TSFlags layout should be kept in sync with Nios2InstrInfo.h. 99 let TSFlags{5-0} = Form.Value; 100 let DecoderNamespace = "Nios2"; 101 field bits<32> SoftFail = 0; 102} 103 104class Nios2Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern, 105 InstrItinClass Itin = IIPseudo>: 106 Nios2Inst32<outs, ins, asmstr, pattern, Itin, Pseudo> { 107 108 let isCodeGenOnly = 1; 109 let isPseudo = 1; 110} 111 112//===----------------------------------------------------------------------===// 113// Base classes for R1 and R2 instructions 114//===----------------------------------------------------------------------===// 115 116class Nios2R1Inst32<dag outs, dag ins, string asmstr, list<dag> pattern, 117 InstrItinClass itin, Format f>: 118 Nios2Inst32<outs, ins, asmstr, pattern, itin, f> { 119 let DecoderNamespace = "Nios2"; 120 let InstrPredicates = [isNios2r1]; 121} 122 123class Nios2R2Inst32<dag outs, dag ins, string asmstr, list<dag> pattern, 124 InstrItinClass itin, Format f>: 125 Nios2Inst32<outs, ins, asmstr, pattern, itin, f> { 126 let DecoderNamespace = "Nios2r2"; 127 let InstrPredicates = [isNios2r2]; 128} 129 130//===----------------------------------------------------------------------===// 131// Format I instruction class in Nios2 : <|A|B|immediate|opcode|> 132//===----------------------------------------------------------------------===// 133 134class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 135 InstrItinClass itin>: Nios2R1Inst32<outs, ins, asmstr, 136 pattern, itin, FrmI> { 137 138 bits<5> rA; 139 bits<5> rB; 140 bits<16> imm; 141 142 let Opcode = op; 143 144 let Inst{31-27} = rA; 145 let Inst{26-22} = rB; 146 let Inst{21-6} = imm; 147} 148 149 150//===----------------------------------------------------------------------===// 151// Format R instruction : <|A|B|C|opx|imm|opcode|> 152//===----------------------------------------------------------------------===// 153 154class FR<bits<6> opx, dag outs, dag ins, string asmstr, list<dag> pattern, 155 InstrItinClass itin>: Nios2R1Inst32<outs, ins, asmstr, 156 pattern, itin, FrmR> { 157 bits<5> rA; 158 bits<5> rB; 159 bits<5> rC; 160 bits<5> imm = 0; 161 162 let Opcode = 0x3a; /* opcode is always 0x3a for R instr. */ 163 164 let Inst{31-27} = rA; 165 let Inst{26-22} = rB; 166 let Inst{21-17} = rC; 167 let Inst{16-11} = opx; /* opx stands for opcode extension */ 168 let Inst{10-6} = imm; /* optional 5-bit immediate value */ 169} 170 171//===----------------------------------------------------------------------===// 172// Format J instruction class in Nios2 : <|address|opcode|> 173//===----------------------------------------------------------------------===// 174 175class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 176 InstrItinClass itin>: 177 Nios2R1Inst32<outs, ins, asmstr, pattern, itin, FrmJ> { 178 bits<26> addr; 179 let Opcode = op; 180 let Inst{31-6} = addr; 181} 182 183//===----------------------------------------------------------------------===// 184// Format F3X6 (R2) instruction : <|opx|RSV|C|B|A|opcode|> 185//===----------------------------------------------------------------------===// 186 187class F3X6<bits<6> opx, dag outs, dag ins, string asmstr, list<dag> pattern, 188 InstrItinClass itin>: 189 Nios2R2Inst32<outs, ins, asmstr, pattern, itin, FrmF3X6> { 190 bits<5> rC; 191 bits<5> rB; 192 bits<5> rA; 193 bits<5> rsv = 0; 194 195 let Opcode = 0x20; /* opcode is always 0x20 (OPX group) for F3X6 instr. */ 196 197 let Inst{31-26} = opx; /* opx stands for opcode extension */ 198 let Inst{25-21} = rsv; 199 let Inst{20-16} = rC; 200 let Inst{15-11} = rB; 201 let Inst{10-6} = rA; 202} 203 204//===----------------------------------------------------------------------===// 205// Multiclasses for common instructions of both R1 and R2: 206//===----------------------------------------------------------------------===// 207 208// Multiclass for instructions that have R format in R1 and F3X6 format in R2 209// and their opx values differ between R1 and R2 210multiclass CommonInstr_R_F3X6_opx<bits<6> opxR1, bits<6> opxR2, dag outs, 211 dag ins, string asmstr, list<dag> pattern, 212 InstrItinClass itin> { 213 def NAME#_R1 : FR<opxR1, outs, ins, asmstr, pattern, itin>; 214 def NAME#_R2 : F3X6<opxR2, outs, ins, asmstr, pattern, itin>; 215} 216 217// Multiclass for instructions that have R format in R1 and F3X6 format in R2 218// and their opx values are the same in R1 and R2 219multiclass CommonInstr_R_F3X6<bits<6> opx, dag outs, dag ins, string asmstr, 220 list<dag> pattern, InstrItinClass itin> : 221 CommonInstr_R_F3X6_opx<opx, opx, outs, ins, asmstr, pattern, itin>; 222 223// Multiclass for instructions that have I format in R1 and F2I16 format in R2 224// and their op code values differ between R1 and R2 225multiclass CommonInstr_I_F2I16_op<bits<6> opR1, bits<6> opR2, dag outs, dag ins, 226 string asmstr, list<dag> pattern, 227 InstrItinClass itin> { 228 def NAME#_R1 : FI<opR1, outs, ins, asmstr, pattern, itin>; 229} 230 231// Multiclass for instructions that have I format in R1 and F2I16 format in R2 232// and their op code values are the same in R1 and R2 233multiclass CommonInstr_I_F2I16<bits<6> op, dag outs, dag ins, string asmstr, 234 list<dag> pattern, InstrItinClass itin> : 235 CommonInstr_I_F2I16_op<op, op, outs, ins, asmstr, pattern, itin>; 236