1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the RISCV implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 15 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 16 17 #include "RISCVRegisterInfo.h" 18 #include "llvm/CodeGen/TargetInstrInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "RISCVGenInstrInfo.inc" 22 23 namespace llvm { 24 25 class RISCVInstrInfo : public RISCVGenInstrInfo { 26 27 public: 28 RISCVInstrInfo(); 29 30 unsigned isLoadFromStackSlot(const MachineInstr &MI, 31 int &FrameIndex) const override; 32 unsigned isStoreToStackSlot(const MachineInstr &MI, 33 int &FrameIndex) const override; 34 35 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 36 const DebugLoc &DL, unsigned DstReg, unsigned SrcReg, 37 bool KillSrc) const override; 38 39 void storeRegToStackSlot(MachineBasicBlock &MBB, 40 MachineBasicBlock::iterator MBBI, unsigned SrcReg, 41 bool IsKill, int FrameIndex, 42 const TargetRegisterClass *RC, 43 const TargetRegisterInfo *TRI) const override; 44 45 void loadRegFromStackSlot(MachineBasicBlock &MBB, 46 MachineBasicBlock::iterator MBBI, unsigned DstReg, 47 int FrameIndex, const TargetRegisterClass *RC, 48 const TargetRegisterInfo *TRI) const override; 49 50 // Materializes the given int32 Val into DstReg. 51 void movImm32(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 52 const DebugLoc &DL, unsigned DstReg, uint64_t Val, 53 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 54 55 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 56 57 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 58 MachineBasicBlock *&FBB, 59 SmallVectorImpl<MachineOperand> &Cond, 60 bool AllowModify) const override; 61 62 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 63 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 64 const DebugLoc &dl, 65 int *BytesAdded = nullptr) const override; 66 67 unsigned insertIndirectBranch(MachineBasicBlock &MBB, 68 MachineBasicBlock &NewDestBB, 69 const DebugLoc &DL, int64_t BrOffset, 70 RegScavenger *RS = nullptr) const override; 71 72 unsigned removeBranch(MachineBasicBlock &MBB, 73 int *BytesRemoved = nullptr) const override; 74 75 bool 76 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 77 78 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 79 80 bool isBranchOffsetInRange(unsigned BranchOpc, 81 int64_t BrOffset) const override; 82 }; 83 } 84 #endif 85