1 //===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 /* Capstone Disassembly Engine */
11 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
12
13 #ifdef CAPSTONE_HAS_XCORE
14
15 #include <stdio.h> // DEBUG
16 #include <stdlib.h>
17 #include <string.h>
18
19 #include "../../cs_priv.h"
20 #include "../../utils.h"
21
22 #include "../../MCInst.h"
23 #include "../../MCInstrDesc.h"
24 #include "../../MCFixedLenDisassembler.h"
25 #include "../../MCRegisterInfo.h"
26 #include "../../MCDisassembler.h"
27 #include "../../MathExtras.h"
28
getFeatureBits(int mode)29 static uint64_t getFeatureBits(int mode)
30 {
31 // support everything
32 return (uint64_t)-1;
33 }
34
readInstruction16(const uint8_t * code,size_t code_len,uint16_t * insn)35 static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn)
36 {
37 if (code_len < 2)
38 // insufficient data
39 return false;
40
41 // Encoded as a little-endian 16-bit word in the stream.
42 *insn = (code[0] << 0) | (code[1] << 8);
43 return true;
44 }
45
readInstruction32(const uint8_t * code,size_t code_len,uint32_t * insn)46 static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn)
47 {
48 if (code_len < 4)
49 // insufficient data
50 return false;
51
52 // Encoded as a little-endian 32-bit word in the stream.
53 *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | (code[3] << 24);
54 return true;
55 }
56
getReg(MCRegisterInfo * MRI,unsigned RC,unsigned RegNo)57 static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
58 {
59 MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
60 return rc->RegsBegin[RegNo];
61 }
62
63 static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
64 uint64_t Address, void *Decoder);
65
66 static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
67 uint64_t Address, void *Decoder);
68
69 static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
70 uint64_t Address, void *Decoder);
71
72 static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
73 uint64_t Address, void *Decoder);
74
75 static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
76 uint64_t Address, void *Decoder);
77
78 static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
79 uint64_t Address, void *Decoder);
80
81 static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
82 uint64_t Address, void *Decoder);
83
84 static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
85 uint64_t Address, void *Decoder);
86
87 static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
88 uint64_t Address, void *Decoder);
89
90 static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
91 uint64_t Address, void *Decoder);
92
93 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn,
94 uint64_t Address, void *Decoder);
95
96 static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn,
97 uint64_t Address, void *Decoder);
98
99 static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn,
100 uint64_t Address, void *Decoder);
101
102 static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn,
103 uint64_t Address, void *Decoder);
104
105 static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn,
106 uint64_t Address, void *Decoder);
107
108 static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn,
109 uint64_t Address, void *Decoder);
110
111 static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
112 uint64_t Address, void *Decoder);
113
114 static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn,
115 uint64_t Address, void *Decoder);
116
117 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn,
118 uint64_t Address, void *Decoder);
119
120 static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn,
121 uint64_t Address, void *Decoder);
122
123 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
124 uint64_t Address, void *Decoder);
125
126 static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn,
127 uint64_t Address, void *Decoder);
128
129 static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn,
130 uint64_t Address, void *Decoder);
131
132 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn,
133 uint64_t Address, void *Decoder);
134
135 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn,
136 uint64_t Address, void *Decoder);
137
138 #include "XCoreGenDisassemblerTables.inc"
139
140 #define GET_REGINFO_ENUM
141 #define GET_REGINFO_MC_DESC
142 #include "XCoreGenRegisterInfo.inc"
143
DecodeGRRegsRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,void * Decoder)144 static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
145 uint64_t Address, void *Decoder)
146 {
147 unsigned Reg;
148
149 if (RegNo > 11)
150 return MCDisassembler_Fail;
151
152 Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo);
153 MCOperand_CreateReg0(Inst, Reg);
154
155 return MCDisassembler_Success;
156 }
157
DecodeRRegsRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,void * Decoder)158 static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
159 uint64_t Address, void *Decoder)
160 {
161 unsigned Reg;
162 if (RegNo > 15)
163 return MCDisassembler_Fail;
164
165 Reg = getReg(Decoder, XCore_RRegsRegClassID, RegNo);
166 MCOperand_CreateReg0(Inst, Reg);
167
168 return MCDisassembler_Success;
169 }
170
DecodeBitpOperand(MCInst * Inst,unsigned Val,uint64_t Address,void * Decoder)171 static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
172 uint64_t Address, void *Decoder)
173 {
174 static unsigned Values[] = {
175 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
176 };
177
178 if (Val > 11)
179 return MCDisassembler_Fail;
180
181 MCOperand_CreateImm0(Inst, Values[Val]);
182 return MCDisassembler_Success;
183 }
184
DecodeNegImmOperand(MCInst * Inst,unsigned Val,uint64_t Address,void * Decoder)185 static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
186 uint64_t Address, void *Decoder)
187 {
188 MCOperand_CreateImm0(Inst, -(int64_t)Val);
189 return MCDisassembler_Success;
190 }
191
Decode2OpInstruction(unsigned Insn,unsigned * Op1,unsigned * Op2)192 static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2)
193 {
194 unsigned Op1High, Op2High;
195 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
196
197 if (Combined < 27)
198 return MCDisassembler_Fail;
199
200 if (fieldFromInstruction_4(Insn, 5, 1)) {
201 if (Combined == 31)
202 return MCDisassembler_Fail;
203 Combined += 5;
204 }
205
206 Combined -= 27;
207 Op1High = Combined % 3;
208 Op2High = Combined / 3;
209 *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2);
210 *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2);
211
212 return MCDisassembler_Success;
213 }
214
Decode3OpInstruction(unsigned Insn,unsigned * Op1,unsigned * Op2,unsigned * Op3)215 static DecodeStatus Decode3OpInstruction(unsigned Insn,
216 unsigned *Op1, unsigned *Op2, unsigned *Op3)
217 {
218 unsigned Op1High, Op2High, Op3High;
219 unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
220 if (Combined >= 27)
221 return MCDisassembler_Fail;
222
223 Op1High = Combined % 3;
224 Op2High = (Combined / 3) % 3;
225 Op3High = Combined / 9;
226 *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2);
227 *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2);
228 *Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2);
229
230 return MCDisassembler_Success;
231 }
232
233 #define GET_INSTRINFO_ENUM
234 #include "XCoreGenInstrInfo.inc"
Decode2OpInstructionFail(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)235 static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
236 void *Decoder)
237 {
238 // Try and decode as a 3R instruction.
239 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5);
240 switch (Opcode) {
241 case 0x0:
242 MCInst_setOpcode(Inst, XCore_STW_2rus);
243 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
244 case 0x1:
245 MCInst_setOpcode(Inst, XCore_LDW_2rus);
246 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
247 case 0x2:
248 MCInst_setOpcode(Inst, XCore_ADD_3r);
249 return Decode3RInstruction(Inst, Insn, Address, Decoder);
250 case 0x3:
251 MCInst_setOpcode(Inst, XCore_SUB_3r);
252 return Decode3RInstruction(Inst, Insn, Address, Decoder);
253 case 0x4:
254 MCInst_setOpcode(Inst, XCore_SHL_3r);
255 return Decode3RInstruction(Inst, Insn, Address, Decoder);
256 case 0x5:
257 MCInst_setOpcode(Inst, XCore_SHR_3r);
258 return Decode3RInstruction(Inst, Insn, Address, Decoder);
259 case 0x6:
260 MCInst_setOpcode(Inst, XCore_EQ_3r);
261 return Decode3RInstruction(Inst, Insn, Address, Decoder);
262 case 0x7:
263 MCInst_setOpcode(Inst, XCore_AND_3r);
264 return Decode3RInstruction(Inst, Insn, Address, Decoder);
265 case 0x8:
266 MCInst_setOpcode(Inst, XCore_OR_3r);
267 return Decode3RInstruction(Inst, Insn, Address, Decoder);
268 case 0x9:
269 MCInst_setOpcode(Inst, XCore_LDW_3r);
270 return Decode3RInstruction(Inst, Insn, Address, Decoder);
271 case 0x10:
272 MCInst_setOpcode(Inst, XCore_LD16S_3r);
273 return Decode3RInstruction(Inst, Insn, Address, Decoder);
274 case 0x11:
275 MCInst_setOpcode(Inst, XCore_LD8U_3r);
276 return Decode3RInstruction(Inst, Insn, Address, Decoder);
277 case 0x12:
278 MCInst_setOpcode(Inst, XCore_ADD_2rus);
279 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
280 case 0x13:
281 MCInst_setOpcode(Inst, XCore_SUB_2rus);
282 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
283 case 0x14:
284 MCInst_setOpcode(Inst, XCore_SHL_2rus);
285 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
286 case 0x15:
287 MCInst_setOpcode(Inst, XCore_SHR_2rus);
288 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
289 case 0x16:
290 MCInst_setOpcode(Inst, XCore_EQ_2rus);
291 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
292 case 0x17:
293 MCInst_setOpcode(Inst, XCore_TSETR_3r);
294 return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
295 case 0x18:
296 MCInst_setOpcode(Inst, XCore_LSS_3r);
297 return Decode3RInstruction(Inst, Insn, Address, Decoder);
298 case 0x19:
299 MCInst_setOpcode(Inst, XCore_LSU_3r);
300 return Decode3RInstruction(Inst, Insn, Address, Decoder);
301 }
302
303 return MCDisassembler_Fail;
304 }
305
Decode2RInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)306 static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
307 void *Decoder)
308 {
309 unsigned Op1, Op2;
310 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
311 if (S != MCDisassembler_Success)
312 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
313
314 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
315 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
316
317 return S;
318 }
319
Decode2RImmInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)320 static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
321 void *Decoder)
322 {
323 unsigned Op1, Op2;
324 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
325 if (S != MCDisassembler_Success)
326 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
327
328 MCOperand_CreateImm0(Inst, Op1);
329 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
330
331 return S;
332 }
333
DecodeR2RInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)334 static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
335 void *Decoder)
336 {
337 unsigned Op1, Op2;
338 DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1);
339 if (S != MCDisassembler_Success)
340 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
341
342 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
343 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
344
345 return S;
346 }
347
Decode2RSrcDstInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)348 static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
349 void *Decoder)
350 {
351 unsigned Op1, Op2;
352 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
353 if (S != MCDisassembler_Success)
354 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
355
356 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
357 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
358 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
359
360 return S;
361 }
362
DecodeRUSInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)363 static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
364 void *Decoder)
365 {
366 unsigned Op1, Op2;
367 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
368 if (S != MCDisassembler_Success)
369 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
370
371 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
372 MCOperand_CreateImm0(Inst, Op2);
373
374 return S;
375 }
376
DecodeRUSBitpInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)377 static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
378 void *Decoder)
379 {
380 unsigned Op1, Op2;
381 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
382 if (S != MCDisassembler_Success)
383 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
384
385 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
386 DecodeBitpOperand(Inst, Op2, Address, Decoder);
387
388 return S;
389 }
390
DecodeRUSSrcDstBitpInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)391 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
392 void *Decoder)
393 {
394 unsigned Op1, Op2;
395 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
396 if (S != MCDisassembler_Success)
397 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
398
399 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
400 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
401 DecodeBitpOperand(Inst, Op2, Address, Decoder);
402
403 return S;
404 }
405
DecodeL2OpInstructionFail(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)406 static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
407 void *Decoder)
408 {
409 // Try and decode as a L3R / L2RUS instruction.
410 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) |
411 fieldFromInstruction_4(Insn, 27, 5) << 4;
412 switch (Opcode) {
413 case 0x0c:
414 MCInst_setOpcode(Inst, XCore_STW_l3r);
415 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
416 case 0x1c:
417 MCInst_setOpcode(Inst, XCore_XOR_l3r);
418 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
419 case 0x2c:
420 MCInst_setOpcode(Inst, XCore_ASHR_l3r);
421 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
422 case 0x3c:
423 MCInst_setOpcode(Inst, XCore_LDAWF_l3r);
424 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
425 case 0x4c:
426 MCInst_setOpcode(Inst, XCore_LDAWB_l3r);
427 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
428 case 0x5c:
429 MCInst_setOpcode(Inst, XCore_LDA16F_l3r);
430 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
431 case 0x6c:
432 MCInst_setOpcode(Inst, XCore_LDA16B_l3r);
433 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
434 case 0x7c:
435 MCInst_setOpcode(Inst, XCore_MUL_l3r);
436 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
437 case 0x8c:
438 MCInst_setOpcode(Inst, XCore_DIVS_l3r);
439 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
440 case 0x9c:
441 MCInst_setOpcode(Inst, XCore_DIVU_l3r);
442 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
443 case 0x10c:
444 MCInst_setOpcode(Inst, XCore_ST16_l3r);
445 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
446 case 0x11c:
447 MCInst_setOpcode(Inst, XCore_ST8_l3r);
448 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
449 case 0x12c:
450 MCInst_setOpcode(Inst, XCore_ASHR_l2rus);
451 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
452 case 0x12d:
453 MCInst_setOpcode(Inst, XCore_OUTPW_l2rus);
454 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
455 case 0x12e:
456 MCInst_setOpcode(Inst, XCore_INPW_l2rus);
457 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
458 case 0x13c:
459 MCInst_setOpcode(Inst, XCore_LDAWF_l2rus);
460 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
461 case 0x14c:
462 MCInst_setOpcode(Inst, XCore_LDAWB_l2rus);
463 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
464 case 0x15c:
465 MCInst_setOpcode(Inst, XCore_CRC_l3r);
466 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
467 case 0x18c:
468 MCInst_setOpcode(Inst, XCore_REMS_l3r);
469 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
470 case 0x19c:
471 MCInst_setOpcode(Inst, XCore_REMU_l3r);
472 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
473 }
474
475 return MCDisassembler_Fail;
476 }
477
DecodeL2RInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)478 static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
479 void *Decoder)
480 {
481 unsigned Op1, Op2;
482 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
483 if (S != MCDisassembler_Success)
484 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
485
486 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
487 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
488
489 return S;
490 }
491
DecodeLR2RInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)492 static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
493 void *Decoder)
494 {
495 unsigned Op1, Op2;
496 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
497 if (S != MCDisassembler_Success)
498 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
499
500 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
501 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
502
503 return S;
504 }
505
Decode3RInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)506 static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
507 void *Decoder)
508 {
509 unsigned Op1, Op2, Op3;
510 DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
511 if (S == MCDisassembler_Success) {
512 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
513 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
514 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
515 }
516
517 return S;
518 }
519
Decode3RImmInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)520 static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
521 void *Decoder)
522 {
523 unsigned Op1, Op2, Op3;
524 DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
525 if (S == MCDisassembler_Success) {
526 MCOperand_CreateImm0(Inst, Op1);
527 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
528 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
529 }
530
531 return S;
532 }
533
Decode2RUSInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)534 static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
535 void *Decoder)
536 {
537 unsigned Op1, Op2, Op3;
538 DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
539 if (S == MCDisassembler_Success) {
540 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
541 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
542 MCOperand_CreateImm0(Inst, Op3);
543 }
544
545 return S;
546 }
547
Decode2RUSBitpInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)548 static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
549 void *Decoder)
550 {
551 unsigned Op1, Op2, Op3;
552 DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
553 if (S == MCDisassembler_Success) {
554 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
555 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
556 DecodeBitpOperand(Inst, Op3, Address, Decoder);
557 }
558
559 return S;
560 }
561
DecodeL3RInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)562 static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
563 void *Decoder)
564 {
565 unsigned Op1, Op2, Op3;
566 DecodeStatus S =
567 Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
568 if (S == MCDisassembler_Success) {
569 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
570 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
571 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
572 }
573
574 return S;
575 }
576
DecodeL3RSrcDstInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)577 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
578 void *Decoder)
579 {
580 unsigned Op1, Op2, Op3;
581 DecodeStatus S =
582 Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
583 if (S == MCDisassembler_Success) {
584 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
585 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
586 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
587 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
588 }
589
590 return S;
591 }
592
DecodeL2RUSInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)593 static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
594 void *Decoder)
595 {
596 unsigned Op1, Op2, Op3;
597 DecodeStatus S =
598 Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
599 if (S == MCDisassembler_Success) {
600 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
601 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
602 MCOperand_CreateImm0(Inst, Op3);
603 }
604
605 return S;
606 }
607
DecodeL2RUSBitpInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)608 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
609 void *Decoder)
610 {
611 unsigned Op1, Op2, Op3;
612 DecodeStatus S =
613 Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
614 if (S == MCDisassembler_Success) {
615 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
616 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
617 DecodeBitpOperand(Inst, Op3, Address, Decoder);
618 }
619
620 return S;
621 }
622
DecodeL6RInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)623 static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
624 void *Decoder)
625 {
626 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
627 DecodeStatus S =
628 Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
629 if (S != MCDisassembler_Success)
630 return S;
631
632 S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6);
633 if (S != MCDisassembler_Success)
634 return S;
635
636 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
637 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
638 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
639 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
640 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
641 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
642 return S;
643 }
644
DecodeL5RInstructionFail(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)645 static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
646 void *Decoder)
647 {
648 unsigned Opcode;
649
650 // Try and decode as a L6R instruction.
651 MCInst_clear(Inst);
652 Opcode = fieldFromInstruction_4(Insn, 27, 5);
653 switch (Opcode) {
654 default:
655 break;
656 case 0x00:
657 MCInst_setOpcode(Inst, XCore_LMUL_l6r);
658 return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
659 }
660
661 return MCDisassembler_Fail;
662 }
663
DecodeL5RInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)664 static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
665 void *Decoder)
666 {
667 unsigned Op1, Op2, Op3, Op4, Op5;
668 DecodeStatus S =
669 Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
670 if (S != MCDisassembler_Success)
671 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
672
673 S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5);
674 if (S != MCDisassembler_Success)
675 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
676
677 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
678 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
679 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
680 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
681 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
682 return S;
683 }
684
DecodeL4RSrcDstInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)685 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
686 void *Decoder)
687 {
688 unsigned Op1, Op2, Op3;
689 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
690 DecodeStatus S =
691 Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
692 if (S == MCDisassembler_Success) {
693 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
694 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
695 }
696
697 if (S == MCDisassembler_Success) {
698 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
699 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
700 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
701 }
702 return S;
703 }
704
DecodeL4RSrcDstSrcDstInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,void * Decoder)705 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
706 void *Decoder)
707 {
708 unsigned Op1, Op2, Op3;
709 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
710 DecodeStatus S =
711 Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
712 if (S == MCDisassembler_Success) {
713 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
714 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
715 }
716
717 if (S == MCDisassembler_Success) {
718 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
719 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
720 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
721 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
722 }
723
724 return S;
725 }
726
727 #define GET_SUBTARGETINFO_ENUM
728 #include "XCoreGenInstrInfo.inc"
XCore_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * MI,uint16_t * size,uint64_t address,void * info)729 bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
730 uint16_t *size, uint64_t address, void *info)
731 {
732 uint16_t insn16;
733 uint32_t insn32;
734 DecodeStatus Result;
735
736 if (!readInstruction16(code, code_len, &insn16)) {
737 return false;
738 }
739
740 if (MI->flat_insn->detail) {
741 memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
742 }
743
744 // Calling the auto-generated decoder function.
745 Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0);
746 if (Result != MCDisassembler_Fail) {
747 *size = 2;
748 return true;
749 }
750
751 if (!readInstruction32(code, code_len, &insn32)) {
752 return false;
753 }
754
755 // Calling the auto-generated decoder function.
756 Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0);
757 if (Result != MCDisassembler_Fail) {
758 *size = 4;
759 return true;
760 }
761
762 return false;
763 }
764
XCore_init(MCRegisterInfo * MRI)765 void XCore_init(MCRegisterInfo *MRI)
766 {
767 /*
768 InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC,
769 XCoreMCRegisterClasses, 2,
770 XCoreRegUnitRoots,
771 16,
772 XCoreRegDiffLists,
773 XCoreRegStrings,
774 XCoreSubRegIdxLists,
775 1,
776 XCoreSubRegIdxRanges,
777 XCoreRegEncodingTable);
778 */
779
780
781 MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17,
782 0, 0,
783 XCoreMCRegisterClasses, 2,
784 0, 0,
785 XCoreRegDiffLists,
786 0,
787 XCoreSubRegIdxLists, 1,
788 0);
789 }
790
791 #endif
792