1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_prim.h"
33
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
36
37 #include "fd2_draw.h"
38 #include "fd2_context.h"
39 #include "fd2_emit.h"
40 #include "fd2_program.h"
41 #include "fd2_util.h"
42 #include "fd2_zsa.h"
43
44
45 static void
emit_cacheflush(struct fd_ringbuffer * ring)46 emit_cacheflush(struct fd_ringbuffer *ring)
47 {
48 unsigned i;
49
50 for (i = 0; i < 12; i++) {
51 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
52 OUT_RING(ring, CACHE_FLUSH);
53 }
54 }
55
56 static void
emit_vertexbufs(struct fd_context * ctx)57 emit_vertexbufs(struct fd_context *ctx)
58 {
59 struct fd_vertex_stateobj *vtx = ctx->vtx.vtx;
60 struct fd_vertexbuf_stateobj *vertexbuf = &ctx->vtx.vertexbuf;
61 struct fd2_vertex_buf bufs[PIPE_MAX_ATTRIBS];
62 unsigned i;
63
64 if (!vtx->num_elements)
65 return;
66
67 for (i = 0; i < vtx->num_elements; i++) {
68 struct pipe_vertex_element *elem = &vtx->pipe[i];
69 struct pipe_vertex_buffer *vb =
70 &vertexbuf->vb[elem->vertex_buffer_index];
71 bufs[i].offset = vb->buffer_offset;
72 bufs[i].size = fd_bo_size(fd_resource(vb->buffer.resource)->bo);
73 bufs[i].prsc = vb->buffer.resource;
74 }
75
76 // NOTE I believe the 0x78 (or 0x9c in solid_vp) relates to the
77 // CONST(20,0) (or CONST(26,0) in soliv_vp)
78
79 fd2_emit_vertex_bufs(ctx->batch->draw, 0x78, bufs, vtx->num_elements);
80 }
81
82 static bool
fd2_draw_vbo(struct fd_context * ctx,const struct pipe_draw_info * info,unsigned index_offset)83 fd2_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
84 unsigned index_offset)
85 {
86 struct fd_ringbuffer *ring = ctx->batch->draw;
87
88 if (ctx->dirty & FD_DIRTY_VTXBUF)
89 emit_vertexbufs(ctx);
90
91 fd2_emit_state(ctx, ctx->dirty);
92
93 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
94 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
95 OUT_RING(ring, info->start);
96
97 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
98 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
99 OUT_RING(ring, 0x0000003b);
100
101 OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
102 OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
103
104 OUT_WFI (ring);
105
106 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
107 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
108 OUT_RING(ring, info->max_index); /* VGT_MAX_VTX_INDX */
109 OUT_RING(ring, info->min_index); /* VGT_MIN_VTX_INDX */
110
111 fd_draw_emit(ctx->batch, ring, ctx->primtypes[info->mode],
112 IGNORE_VISIBILITY, info, index_offset);
113
114 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
115 OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
116 OUT_RING(ring, 0x00000000);
117
118 emit_cacheflush(ring);
119
120 fd_context_all_clean(ctx);
121
122 return true;
123 }
124
125
126 static bool
fd2_clear(struct fd_context * ctx,unsigned buffers,const union pipe_color_union * color,double depth,unsigned stencil)127 fd2_clear(struct fd_context *ctx, unsigned buffers,
128 const union pipe_color_union *color, double depth, unsigned stencil)
129 {
130 struct fd2_context *fd2_ctx = fd2_context(ctx);
131 struct fd_ringbuffer *ring = ctx->batch->draw;
132 struct pipe_framebuffer_state *fb = &ctx->batch->framebuffer;
133 uint32_t reg, colr = 0;
134
135 if ((buffers & PIPE_CLEAR_COLOR) && fb->nr_cbufs)
136 colr = pack_rgba(fb->cbufs[0]->format, color->f);
137
138 /* emit generic state now: */
139 fd2_emit_state(ctx, ctx->dirty &
140 (FD_DIRTY_BLEND | FD_DIRTY_VIEWPORT |
141 FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR));
142
143 fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
144 { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
145 }, 1);
146
147 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
148 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
149 OUT_RING(ring, 0);
150
151 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
152 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
153 OUT_RING(ring, 0x0000028f);
154
155 fd2_program_emit(ring, &ctx->solid_prog);
156
157 OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
158 OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
159
160 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
161 OUT_RING(ring, CP_REG(REG_A2XX_CLEAR_COLOR));
162 OUT_RING(ring, colr);
163
164 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
165 OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
166 OUT_RING(ring, 0x00000084);
167
168 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
169 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
170 reg = 0;
171 if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
172 reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
173 switch (fd_pipe2depth(fb->zsbuf->format)) {
174 case DEPTHX_24_8:
175 if (buffers & PIPE_CLEAR_DEPTH)
176 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe);
177 if (buffers & PIPE_CLEAR_STENCIL)
178 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1);
179 break;
180 case DEPTHX_16:
181 if (buffers & PIPE_CLEAR_DEPTH)
182 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf);
183 break;
184 default:
185 debug_assert(0);
186 break;
187 }
188 }
189 OUT_RING(ring, reg);
190
191 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
192 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTH_CLEAR));
193 reg = 0;
194 if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
195 switch (fd_pipe2depth(fb->zsbuf->format)) {
196 case DEPTHX_24_8:
197 reg = (((uint32_t)(0xffffff * depth)) << 8) |
198 (stencil & 0xff);
199 break;
200 case DEPTHX_16:
201 reg = (uint32_t)(0xffffffff * depth);
202 break;
203 default:
204 debug_assert(0);
205 break;
206 }
207 }
208 OUT_RING(ring, reg);
209
210 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
211 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
212 reg = 0;
213 if (buffers & PIPE_CLEAR_DEPTH) {
214 reg |= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS) |
215 A2XX_RB_DEPTHCONTROL_Z_ENABLE |
216 A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE |
217 A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
218 }
219 if (buffers & PIPE_CLEAR_STENCIL) {
220 reg |= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS) |
221 A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
222 A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
223 }
224 OUT_RING(ring, reg);
225
226 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
227 OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
228 OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
229 OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
230
231 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
232 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
233 OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(FUNC_ALWAYS) |
234 A2XX_RB_COLORCONTROL_BLEND_DISABLE |
235 A2XX_RB_COLORCONTROL_ROP_CODE(12) |
236 A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
237 A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
238
239 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
240 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
241 OUT_RING(ring, 0x00000000); /* PA_CL_CLIP_CNTL */
242 OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */
243 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
244 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
245
246 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
247 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
248 OUT_RING(ring, 0x0000ffff);
249
250 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
251 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
252 OUT_RING(ring, xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */
253 OUT_RING(ring, xy2d(fb->width, /* PA_SC_WINDOW_SCISSOR_BR */
254 fb->height));
255
256 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
257 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
258 if (buffers & PIPE_CLEAR_COLOR) {
259 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
260 A2XX_RB_COLOR_MASK_WRITE_GREEN |
261 A2XX_RB_COLOR_MASK_WRITE_BLUE |
262 A2XX_RB_COLOR_MASK_WRITE_ALPHA);
263 } else {
264 OUT_RING(ring, 0x0);
265 }
266
267 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
268 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
269 OUT_RING(ring, 3); /* VGT_MAX_VTX_INDX */
270 OUT_RING(ring, 0); /* VGT_MIN_VTX_INDX */
271
272 fd_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
273 DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
274
275 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
276 OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
277 OUT_RING(ring, 0x00000000);
278
279 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
280 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
281 OUT_RING(ring, 0x00000000);
282
283 ctx->dirty |= FD_DIRTY_ZSA |
284 FD_DIRTY_VIEWPORT |
285 FD_DIRTY_RASTERIZER |
286 FD_DIRTY_SAMPLE_MASK |
287 FD_DIRTY_PROG |
288 FD_DIRTY_CONST |
289 FD_DIRTY_BLEND |
290 FD_DIRTY_FRAMEBUFFER;
291
292 ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
293 ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST;
294
295 return true;
296 }
297
298 void
fd2_draw_init(struct pipe_context * pctx)299 fd2_draw_init(struct pipe_context *pctx)
300 {
301 struct fd_context *ctx = fd_context(pctx);
302 ctx->draw_vbo = fd2_draw_vbo;
303 ctx->clear = fd2_clear;
304 }
305