1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28
29 #include "freedreno_resource.h"
30
31 #include "fd5_compute.h"
32 #include "fd5_context.h"
33 #include "fd5_emit.h"
34
35 struct fd5_compute_stateobj {
36 struct ir3_shader *shader;
37 };
38
39
40 static void *
fd5_create_compute_state(struct pipe_context * pctx,const struct pipe_compute_state * cso)41 fd5_create_compute_state(struct pipe_context *pctx,
42 const struct pipe_compute_state *cso)
43 {
44 struct fd_context *ctx = fd_context(pctx);
45 struct ir3_compiler *compiler = ctx->screen->compiler;
46 struct fd5_compute_stateobj *so = CALLOC_STRUCT(fd5_compute_stateobj);
47 so->shader = ir3_shader_create_compute(compiler, cso, &ctx->debug);
48 return so;
49 }
50
51 static void
fd5_delete_compute_state(struct pipe_context * pctx,void * hwcso)52 fd5_delete_compute_state(struct pipe_context *pctx, void *hwcso)
53 {
54 struct fd5_compute_stateobj *so = hwcso;
55 ir3_shader_destroy(so->shader);
56 free(so);
57 }
58
59 /* maybe move to fd5_program? */
60 static void
cs_program_emit(struct fd_ringbuffer * ring,struct ir3_shader_variant * v)61 cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
62 {
63 const struct ir3_info *i = &v->info;
64 enum a3xx_threadsize thrsz;
65
66 /* note: blob uses local_size_x/y/z threshold to choose threadsize: */
67 thrsz = FOUR_QUADS;
68
69 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
70 OUT_RING(ring, 0x00000000); /* SP_SP_CNTL */
71
72 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 1);
73 OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS) |
74 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(thrsz) |
75 0x00000880 /* XXX */);
76
77 OUT_PKT4(ring, REG_A5XX_SP_CS_CTRL_REG0, 1);
78 OUT_RING(ring, A5XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
79 A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
80 A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
81 A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
82 0x6 /* XXX */);
83
84 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
85 OUT_RING(ring, A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(0) |
86 A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(0) |
87 A5XX_HLSQ_CS_CONFIG_ENABLED);
88
89 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL, 1);
90 OUT_RING(ring, A5XX_HLSQ_CS_CNTL_INSTRLEN(v->instrlen) |
91 COND(v->has_ssbo, A5XX_HLSQ_CS_CNTL_SSBO_ENABLE));
92
93 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
94 OUT_RING(ring, A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(0) |
95 A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(0) |
96 A5XX_SP_CS_CONFIG_ENABLED);
97
98 unsigned constlen = align(v->constlen, 4) / 4;
99 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
100 OUT_RING(ring, constlen); /* HLSQ_CS_CONSTLEN */
101 OUT_RING(ring, v->instrlen); /* HLSQ_CS_INSTRLEN */
102
103 OUT_PKT4(ring, REG_A5XX_SP_CS_OBJ_START_LO, 2);
104 OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
105
106 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
107 OUT_RING(ring, 0x1f00000);
108
109 uint32_t local_invocation_id, work_group_id;
110 local_invocation_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
111 work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
112
113 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL_0, 2);
114 OUT_RING(ring, A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
115 A5XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
116 A5XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
117 A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
118 OUT_RING(ring, 0x1); /* HLSQ_CS_CNTL_1 */
119
120 fd5_emit_shader(ring, v);
121 }
122
123 static void
emit_setup(struct fd_context * ctx)124 emit_setup(struct fd_context *ctx)
125 {
126 struct fd_ringbuffer *ring = ctx->batch->draw;
127
128 fd5_emit_restore(ctx->batch, ring);
129 fd5_emit_lrz_flush(ring);
130
131 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
132 OUT_RING(ring, 0x0);
133
134 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
135 OUT_RING(ring, UNK_19);
136
137 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
138 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
139
140 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
141 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
142
143 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
144 fd_wfi(ctx->batch, ring);
145 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
146 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
147
148 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
149 OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
150 }
151
152 static void
fd5_launch_grid(struct fd_context * ctx,const struct pipe_grid_info * info)153 fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
154 {
155 struct fd5_compute_stateobj *so = ctx->compute;
156 struct ir3_shader_key key = {0};
157 struct ir3_shader_variant *v;
158 struct fd_ringbuffer *ring = ctx->batch->draw;
159
160 emit_setup(ctx);
161
162 v = ir3_shader_variant(so->shader, key, &ctx->debug);
163
164 if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
165 cs_program_emit(ring, v);
166
167 fd5_emit_cs_state(ctx, ring, v);
168 ir3_emit_cs_consts(v, ring, ctx, info);
169
170 const unsigned *local_size = info->block; // v->shader->nir->info->cs.local_size;
171 const unsigned *num_groups = info->grid;
172 /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
173 const unsigned work_dim = info->work_dim ? info->work_dim : 3;
174 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_NDRANGE_0, 7);
175 OUT_RING(ring, A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim) |
176 A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
177 A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
178 A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
179 OUT_RING(ring, A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(local_size[0] * num_groups[0]));
180 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_2 */
181 OUT_RING(ring, A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(local_size[1] * num_groups[1]));
182 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_4 */
183 OUT_RING(ring, A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(local_size[2] * num_groups[2]));
184 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_6 */
185
186 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_KERNEL_GROUP_X, 3);
187 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_X */
188 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
189 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
190
191 if (info->indirect) {
192 struct fd_resource *rsc = fd_resource(info->indirect);
193
194 fd5_emit_flush(ctx, ring);
195
196 OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4);
197 OUT_RING(ring, 0x00000000);
198 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */
199 OUT_RING(ring, A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
200 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
201 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
202 } else {
203 OUT_PKT7(ring, CP_EXEC_CS, 4);
204 OUT_RING(ring, 0x00000000);
205 OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0]));
206 OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1]));
207 OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2]));
208 }
209 }
210
211 void
fd5_compute_init(struct pipe_context * pctx)212 fd5_compute_init(struct pipe_context *pctx)
213 {
214 struct fd_context *ctx = fd_context(pctx);
215 ctx->launch_grid = fd5_launch_grid;
216 pctx->create_compute_state = fd5_create_compute_state;
217 pctx->delete_compute_state = fd5_delete_compute_state;
218 }
219