1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_prim.h"
31
32 #include "freedreno_state.h"
33 #include "freedreno_resource.h"
34
35 #include "fd5_draw.h"
36 #include "fd5_context.h"
37 #include "fd5_emit.h"
38 #include "fd5_program.h"
39 #include "fd5_format.h"
40 #include "fd5_zsa.h"
41
42
43 static void
draw_impl(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd5_emit * emit,unsigned index_offset)44 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
45 struct fd5_emit *emit, unsigned index_offset)
46 {
47 const struct pipe_draw_info *info = emit->info;
48 enum pc_di_primtype primtype = ctx->primtypes[info->mode];
49
50 fd5_emit_state(ctx, ring, emit);
51
52 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
53 fd5_emit_vertex_bufs(ring, emit);
54
55 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
56 OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
57 OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
58
59 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
60 OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
61 info->restart_index : 0xffffffff);
62
63 fd5_emit_render_cntl(ctx, false, emit->key.binning_pass);
64 fd5_draw_emit(ctx->batch, ring, primtype,
65 emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
66 info, index_offset);
67 }
68
69 /* fixup dirty shader state in case some "unrelated" (from the state-
70 * tracker's perspective) state change causes us to switch to a
71 * different variant.
72 */
73 static void
fixup_shader_state(struct fd_context * ctx,struct ir3_shader_key * key)74 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
75 {
76 struct fd5_context *fd5_ctx = fd5_context(ctx);
77 struct ir3_shader_key *last_key = &fd5_ctx->last_key;
78
79 if (!ir3_shader_key_equal(last_key, key)) {
80 if (ir3_shader_key_changes_fs(last_key, key)) {
81 ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
82 ctx->dirty |= FD_DIRTY_PROG;
83 }
84
85 if (ir3_shader_key_changes_vs(last_key, key)) {
86 ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
87 ctx->dirty |= FD_DIRTY_PROG;
88 }
89
90 fd5_ctx->last_key = *key;
91 }
92 }
93
94 static bool
fd5_draw_vbo(struct fd_context * ctx,const struct pipe_draw_info * info,unsigned index_offset)95 fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
96 unsigned index_offset)
97 {
98 struct fd5_context *fd5_ctx = fd5_context(ctx);
99 struct fd5_emit emit = {
100 .debug = &ctx->debug,
101 .vtx = &ctx->vtx,
102 .prog = &ctx->prog,
103 .info = info,
104 .key = {
105 .color_two_side = ctx->rasterizer->light_twoside,
106 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
107 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
108 .rasterflat = ctx->rasterizer->flatshade,
109 .half_precision = ctx->in_blit &&
110 fd_half_precision(&ctx->batch->framebuffer),
111 .ucp_enables = ctx->rasterizer->clip_plane_enable,
112 .has_per_samp = (fd5_ctx->fsaturate || fd5_ctx->vsaturate ||
113 fd5_ctx->fastc_srgb || fd5_ctx->vastc_srgb),
114 .vsaturate_s = fd5_ctx->vsaturate_s,
115 .vsaturate_t = fd5_ctx->vsaturate_t,
116 .vsaturate_r = fd5_ctx->vsaturate_r,
117 .fsaturate_s = fd5_ctx->fsaturate_s,
118 .fsaturate_t = fd5_ctx->fsaturate_t,
119 .fsaturate_r = fd5_ctx->fsaturate_r,
120 .vastc_srgb = fd5_ctx->vastc_srgb,
121 .fastc_srgb = fd5_ctx->fastc_srgb,
122 },
123 .rasterflat = ctx->rasterizer->flatshade,
124 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
125 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
126 };
127
128 fixup_shader_state(ctx, &emit.key);
129
130 unsigned dirty = ctx->dirty;
131 const struct ir3_shader_variant *vp = fd5_emit_get_vp(&emit);
132 const struct ir3_shader_variant *fp = fd5_emit_get_fp(&emit);
133
134 /* do regular pass first, since that is more likely to fail compiling: */
135
136 if (!vp || !fp)
137 return false;
138
139 /* figure out whether we need to disable LRZ write for binning
140 * pass using draw pass's fp:
141 */
142 emit.no_lrz_write = fp->writes_pos || fp->has_kill;
143
144 emit.key.binning_pass = false;
145 emit.dirty = dirty;
146
147 draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
148
149 /* and now binning pass: */
150 emit.key.binning_pass = true;
151 emit.dirty = dirty & ~(FD_DIRTY_BLEND);
152 emit.vp = NULL; /* we changed key so need to refetch vp */
153 emit.fp = NULL;
154 draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
155
156 if (emit.streamout_mask) {
157 struct fd_ringbuffer *ring = ctx->batch->draw;
158
159 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
160 if (emit.streamout_mask & (1 << i)) {
161 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
162 OUT_RING(ring, FLUSH_SO_0 + i);
163 }
164 }
165 }
166
167 fd_context_all_clean(ctx);
168
169 return true;
170 }
171
is_z32(enum pipe_format format)172 static bool is_z32(enum pipe_format format)
173 {
174 switch (format) {
175 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
176 case PIPE_FORMAT_Z32_UNORM:
177 case PIPE_FORMAT_Z32_FLOAT:
178 return true;
179 default:
180 return false;
181 }
182 }
183
184 static void
fd5_clear_lrz(struct fd_batch * batch,struct fd_resource * zsbuf,double depth)185 fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
186 {
187 struct fd_ringbuffer *ring;
188 uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
189
190 // TODO mid-frame clears (ie. app doing crazy stuff)?? Maybe worth
191 // splitting both clear and lrz clear out into their own rb's. And
192 // just throw away any draws prior to clear. (Anything not fullscreen
193 // clear, just fallback to generic path that treats it as a normal
194 // draw
195
196 if (!batch->lrz_clear) {
197 batch->lrz_clear = fd_ringbuffer_new(batch->ctx->pipe, 0x1000);
198 fd_ringbuffer_set_parent(batch->lrz_clear, batch->gmem);
199 }
200
201 ring = batch->lrz_clear;
202
203 OUT_WFI5(ring);
204
205 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
206 OUT_RING(ring, 0x10000000);
207
208 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
209 OUT_RING(ring, 0x20fffff);
210
211 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
212 OUT_RING(ring, A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0));
213
214 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
215 OUT_RING(ring, 0x00000000);
216
217 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
218 OUT_RING(ring, 0x00000181);
219
220 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
221 OUT_RING(ring, 0x00000000);
222
223 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
224 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
225 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
226 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
227 OUT_RING(ring, A5XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
228 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
229 OUT_RELOCW(ring, zsbuf->lrz, 0x1000, 0, 0);
230
231 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
232 OUT_RING(ring, 0x00000000);
233
234 OUT_PKT4(ring, REG_A5XX_RB_DEST_MSAA_CNTL, 1);
235 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
236
237 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
238 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
239
240 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
241 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
242 A5XX_RB_CLEAR_CNTL_MASK(0xf));
243
244 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
245 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
246
247 OUT_PKT4(ring, REG_A5XX_VSC_RESOLVE_CNTL, 2);
248 OUT_RING(ring, A5XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
249 A5XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
250 OUT_RING(ring, 0x00000000); // XXX UNKNOWN_0CDE
251
252 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
253 OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
254
255 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
256 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) |
257 A5XX_RB_RESOLVE_CNTL_1_Y(0));
258 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
259 A5XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
260
261 fd5_emit_blit(batch->ctx, ring);
262 }
263
264 static bool
fd5_clear(struct fd_context * ctx,unsigned buffers,const union pipe_color_union * color,double depth,unsigned stencil)265 fd5_clear(struct fd_context *ctx, unsigned buffers,
266 const union pipe_color_union *color, double depth, unsigned stencil)
267 {
268 struct fd_ringbuffer *ring = ctx->batch->draw;
269 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
270 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
271
272 if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
273 is_z32(pfb->zsbuf->format))
274 return false;
275
276 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
277 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
278 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
279 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
280
281 fd5_emit_render_cntl(ctx, true, false);
282
283 if (buffers & PIPE_CLEAR_COLOR) {
284 for (int i = 0; i < pfb->nr_cbufs; i++) {
285 union util_color uc = {0};
286
287 if (!pfb->cbufs[i])
288 continue;
289
290 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
291 continue;
292
293 enum pipe_format pfmt = pfb->cbufs[i]->format;
294
295 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
296 union pipe_color_union swapped;
297 switch (fd5_pipe2swap(pfmt)) {
298 case WZYX:
299 swapped.ui[0] = color->ui[0];
300 swapped.ui[1] = color->ui[1];
301 swapped.ui[2] = color->ui[2];
302 swapped.ui[3] = color->ui[3];
303 break;
304 case WXYZ:
305 swapped.ui[2] = color->ui[0];
306 swapped.ui[1] = color->ui[1];
307 swapped.ui[0] = color->ui[2];
308 swapped.ui[3] = color->ui[3];
309 break;
310 case ZYXW:
311 swapped.ui[3] = color->ui[0];
312 swapped.ui[0] = color->ui[1];
313 swapped.ui[1] = color->ui[2];
314 swapped.ui[2] = color->ui[3];
315 break;
316 case XYZW:
317 swapped.ui[3] = color->ui[0];
318 swapped.ui[2] = color->ui[1];
319 swapped.ui[1] = color->ui[2];
320 swapped.ui[0] = color->ui[3];
321 break;
322 }
323
324 if (util_format_is_pure_uint(pfmt)) {
325 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
326 } else if (util_format_is_pure_sint(pfmt)) {
327 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
328 } else {
329 util_pack_color(swapped.f, pfmt, &uc);
330 }
331
332 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
333 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i));
334
335 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
336 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
337 A5XX_RB_CLEAR_CNTL_MASK(0xf));
338
339 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4);
340 OUT_RING(ring, uc.ui[0]); /* RB_CLEAR_COLOR_DW0 */
341 OUT_RING(ring, uc.ui[1]); /* RB_CLEAR_COLOR_DW1 */
342 OUT_RING(ring, uc.ui[2]); /* RB_CLEAR_COLOR_DW2 */
343 OUT_RING(ring, uc.ui[3]); /* RB_CLEAR_COLOR_DW3 */
344
345 fd5_emit_blit(ctx, ring);
346 }
347 }
348
349 if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
350 uint32_t clear =
351 util_pack_z_stencil(pfb->zsbuf->format, depth, stencil);
352 uint32_t mask = 0;
353
354 if (buffers & PIPE_CLEAR_DEPTH)
355 mask |= 0x1;
356
357 if (buffers & PIPE_CLEAR_STENCIL)
358 mask |= 0x2;
359
360 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
361 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS));
362
363 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
364 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
365 A5XX_RB_CLEAR_CNTL_MASK(mask));
366
367 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
368 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
369
370 fd5_emit_blit(ctx, ring);
371
372 if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
373 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
374 if (zsbuf->lrz) {
375 zsbuf->lrz_valid = true;
376 fd5_clear_lrz(ctx->batch, zsbuf, depth);
377 }
378 }
379 }
380
381 /* disable fast clear to not interfere w/ gmem->mem, etc.. */
382 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
383 OUT_RING(ring, 0x00000000); /* RB_CLEAR_CNTL */
384
385 return true;
386 }
387
388 void
fd5_draw_init(struct pipe_context * pctx)389 fd5_draw_init(struct pipe_context *pctx)
390 {
391 struct fd_context *ctx = fd_context(pctx);
392 ctx->draw_vbo = fd5_draw_vbo;
393 ctx->clear = fd5_clear;
394 }
395