1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28
29 #include "freedreno_resource.h"
30 #include "fd5_image.h"
31 #include "fd5_format.h"
32 #include "fd5_texture.h"
33
34 static enum a4xx_state_block texsb[] = {
35 [PIPE_SHADER_COMPUTE] = SB4_CS_TEX,
36 [PIPE_SHADER_FRAGMENT] = SB4_FS_TEX,
37 };
38
39 static enum a4xx_state_block imgsb[] = {
40 [PIPE_SHADER_COMPUTE] = SB4_CS_SSBO,
41 [PIPE_SHADER_FRAGMENT] = SB4_SSBO,
42 };
43
44 struct fd5_image {
45 enum pipe_format pfmt;
46 enum a5xx_tex_fmt fmt;
47 enum a5xx_tex_fetchsize fetchsize;
48 enum a5xx_tex_type type;
49 bool srgb;
50 uint32_t cpp;
51 uint32_t width;
52 uint32_t height;
53 uint32_t depth;
54 uint32_t pitch;
55 uint32_t array_pitch;
56 struct fd_bo *bo;
57 uint32_t offset;
58 };
59
translate_image(struct fd5_image * img,struct pipe_image_view * pimg)60 static void translate_image(struct fd5_image *img, struct pipe_image_view *pimg)
61 {
62 enum pipe_format format = pimg->format;
63 struct pipe_resource *prsc = pimg->resource;
64 struct fd_resource *rsc = fd_resource(prsc);
65 unsigned lvl;
66
67 if (!pimg->resource) {
68 memset(img, 0, sizeof(*img));
69 return;
70 }
71
72 img->pfmt = format;
73 img->fmt = fd5_pipe2tex(format);
74 img->fetchsize = fd5_pipe2fetchsize(format);
75 img->type = fd5_tex_type(prsc->target);
76 img->srgb = util_format_is_srgb(format);
77 img->cpp = rsc->cpp;
78 img->bo = rsc->bo;
79
80 if (prsc->target == PIPE_BUFFER) {
81 lvl = 0;
82 img->offset = pimg->u.buf.offset;
83 img->pitch = pimg->u.buf.size;
84 img->array_pitch = 0;
85 } else {
86 lvl = pimg->u.tex.level;
87 img->offset = rsc->slices[lvl].offset;
88 img->pitch = rsc->slices[lvl].pitch * rsc->cpp;
89 img->array_pitch = rsc->layer_size;
90 }
91
92 img->width = u_minify(prsc->width0, lvl);
93 img->height = u_minify(prsc->height0, lvl);
94 img->depth = u_minify(prsc->depth0, lvl);
95 }
96
emit_image_tex(struct fd_ringbuffer * ring,unsigned slot,struct fd5_image * img,enum pipe_shader_type shader)97 static void emit_image_tex(struct fd_ringbuffer *ring, unsigned slot,
98 struct fd5_image *img, enum pipe_shader_type shader)
99 {
100 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 12);
101 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(slot) |
102 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
103 CP_LOAD_STATE4_0_STATE_BLOCK(texsb[shader]) |
104 CP_LOAD_STATE4_0_NUM_UNIT(1));
105 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
106 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
107 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
108
109 OUT_RING(ring, A5XX_TEX_CONST_0_FMT(img->fmt) |
110 fd5_tex_swiz(img->pfmt, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
111 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W) |
112 COND(img->srgb, A5XX_TEX_CONST_0_SRGB));
113 OUT_RING(ring, A5XX_TEX_CONST_1_WIDTH(img->width) |
114 A5XX_TEX_CONST_1_HEIGHT(img->height));
115 OUT_RING(ring, A5XX_TEX_CONST_2_FETCHSIZE(img->fetchsize) |
116 A5XX_TEX_CONST_2_TYPE(img->type) |
117 A5XX_TEX_CONST_2_PITCH(img->pitch));
118 OUT_RING(ring, A5XX_TEX_CONST_3_ARRAY_PITCH(img->array_pitch));
119 if (img->bo) {
120 OUT_RELOC(ring, img->bo, img->offset,
121 (uint64_t)A5XX_TEX_CONST_5_DEPTH(img->depth) << 32, 0);
122 } else {
123 OUT_RING(ring, 0x00000000);
124 OUT_RING(ring, A5XX_TEX_CONST_5_DEPTH(img->depth));
125 }
126 OUT_RING(ring, 0x00000000);
127 OUT_RING(ring, 0x00000000);
128 OUT_RING(ring, 0x00000000);
129 OUT_RING(ring, 0x00000000);
130 OUT_RING(ring, 0x00000000);
131 OUT_RING(ring, 0x00000000);
132 }
133
emit_image_ssbo(struct fd_ringbuffer * ring,unsigned slot,struct fd5_image * img,enum pipe_shader_type shader)134 static void emit_image_ssbo(struct fd_ringbuffer *ring, unsigned slot,
135 struct fd5_image *img, enum pipe_shader_type shader)
136 {
137 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 4);
138 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(slot) |
139 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
140 CP_LOAD_STATE4_0_STATE_BLOCK(imgsb[shader]) |
141 CP_LOAD_STATE4_0_NUM_UNIT(1));
142 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(0) |
143 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
144 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
145 OUT_RING(ring, A5XX_SSBO_0_0_BASE_LO(0));
146 OUT_RING(ring, A5XX_SSBO_0_1_PITCH(img->pitch));
147 OUT_RING(ring, A5XX_SSBO_0_2_ARRAY_PITCH(img->array_pitch));
148 OUT_RING(ring, A5XX_SSBO_0_3_CPP(img->cpp));
149
150 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 2);
151 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(slot) |
152 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
153 CP_LOAD_STATE4_0_STATE_BLOCK(imgsb[shader]) |
154 CP_LOAD_STATE4_0_NUM_UNIT(1));
155 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
156 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
157 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
158 OUT_RING(ring, A5XX_SSBO_1_0_FMT(img->fmt) |
159 A5XX_SSBO_1_0_WIDTH(img->width));
160 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(img->height) |
161 A5XX_SSBO_1_1_DEPTH(img->depth));
162
163 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 2);
164 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(slot) |
165 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
166 CP_LOAD_STATE4_0_STATE_BLOCK(imgsb[shader]) |
167 CP_LOAD_STATE4_0_NUM_UNIT(1));
168 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
169 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
170 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
171 if (img->bo) {
172 OUT_RELOCW(ring, img->bo, img->offset, 0, 0);
173 } else {
174 OUT_RING(ring, 0x00000000);
175 OUT_RING(ring, 0x00000000);
176 }
177 }
178
179 /* Note that to avoid conflicts with textures and non-image "SSBO"s, images
180 * are placedd, in reverse order, at the end of the state block, so for
181 * example the sampler state:
182 *
183 * 0: first texture
184 * 1: second texture
185 * ....
186 * N-1: second image
187 * N: first image
188 */
189 static unsigned
get_image_slot(unsigned index)190 get_image_slot(unsigned index)
191 {
192 /* TODO figure out real limit per generation, and don't hardcode.
193 * This needs to match get_image_slot() in ir3_compiler_nir.
194 * Possibly should be factored out into shared helper?
195 */
196 const unsigned max_samplers = 16;
197 return max_samplers - index - 1;
198 }
199
200 /* Emit required "SSBO" and sampler state. The sampler state is used by the
201 * hw for imageLoad(), and "SSBO" state for imageStore(). Returns max sampler
202 * used.
203 */
204 void
fd5_emit_images(struct fd_context * ctx,struct fd_ringbuffer * ring,enum pipe_shader_type shader)205 fd5_emit_images(struct fd_context *ctx, struct fd_ringbuffer *ring,
206 enum pipe_shader_type shader)
207 {
208 struct fd_shaderimg_stateobj *so = &ctx->shaderimg[shader];
209
210 so->dirty_mask &= so->enabled_mask;
211
212 while (so->dirty_mask) {
213 unsigned index = u_bit_scan(&so->dirty_mask);
214 unsigned slot = get_image_slot(index);
215 struct fd5_image img;
216
217 translate_image(&img, &so->si[index]);
218
219 emit_image_tex(ring, slot, &img, shader);
220 emit_image_ssbo(ring, slot, &img, shader);
221 }
222 }
223
224