1 /*
2 * Copyright © 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef _AMDGPU_INTERNAL_H_
26 #define _AMDGPU_INTERNAL_H_
27
28 #include <assert.h>
29 #include <pthread.h>
30
31 #include "libdrm_macros.h"
32 #include "xf86atomic.h"
33 #include "amdgpu.h"
34 #include "util_double_list.h"
35
36 #define AMDGPU_CS_MAX_RINGS 8
37 /* do not use below macro if b is not power of 2 aligned value */
38 #define __round_mask(x, y) ((__typeof__(x))((y)-1))
39 #define ROUND_UP(x, y) ((((x)-1) | __round_mask(x, y))+1)
40 #define ROUND_DOWN(x, y) ((x) & ~__round_mask(x, y))
41
42 #define AMDGPU_INVALID_VA_ADDRESS 0xffffffffffffffff
43 #define AMDGPU_NULL_SUBMIT_SEQ 0
44
45 struct amdgpu_bo_va_hole {
46 struct list_head list;
47 uint64_t offset;
48 uint64_t size;
49 };
50
51 struct amdgpu_bo_va_mgr {
52 uint64_t va_max;
53 struct list_head va_holes;
54 pthread_mutex_t bo_va_mutex;
55 uint32_t va_alignment;
56 };
57
58 struct amdgpu_va {
59 amdgpu_device_handle dev;
60 uint64_t address;
61 uint64_t size;
62 enum amdgpu_gpu_va_range range;
63 struct amdgpu_bo_va_mgr *vamgr;
64 };
65
66 struct amdgpu_device {
67 atomic_t refcount;
68 int fd;
69 int flink_fd;
70 unsigned major_version;
71 unsigned minor_version;
72
73 char *marketing_name;
74 /** List of buffer handles. Protected by bo_table_mutex. */
75 struct util_hash_table *bo_handles;
76 /** List of buffer GEM flink names. Protected by bo_table_mutex. */
77 struct util_hash_table *bo_flink_names;
78 /** This protects all hash tables. */
79 pthread_mutex_t bo_table_mutex;
80 struct drm_amdgpu_info_device dev_info;
81 struct amdgpu_gpu_info info;
82 /** The VA manager for the lower virtual address space */
83 struct amdgpu_bo_va_mgr vamgr;
84 /** The VA manager for the 32bit address space */
85 struct amdgpu_bo_va_mgr vamgr_32;
86 /** The VA manager for the high virtual address space */
87 struct amdgpu_bo_va_mgr vamgr_high;
88 /** The VA manager for the 32bit high address space */
89 struct amdgpu_bo_va_mgr vamgr_high_32;
90 };
91
92 struct amdgpu_bo {
93 atomic_t refcount;
94 struct amdgpu_device *dev;
95
96 uint64_t alloc_size;
97
98 uint32_t handle;
99 uint32_t flink_name;
100
101 pthread_mutex_t cpu_access_mutex;
102 void *cpu_ptr;
103 int cpu_map_count;
104 };
105
106 struct amdgpu_bo_list {
107 struct amdgpu_device *dev;
108
109 uint32_t handle;
110 };
111
112 struct amdgpu_context {
113 struct amdgpu_device *dev;
114 /** Mutex for accessing fences and to maintain command submissions
115 in good sequence. */
116 pthread_mutex_t sequence_mutex;
117 /* context id*/
118 uint32_t id;
119 uint64_t last_seq[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
120 struct list_head sem_list[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
121 };
122
123 /**
124 * Structure describing sw semaphore based on scheduler
125 *
126 */
127 struct amdgpu_semaphore {
128 atomic_t refcount;
129 struct list_head list;
130 struct amdgpu_cs_fence signal_fence;
131 };
132
133 /**
134 * Functions.
135 */
136
137 drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start,
138 uint64_t max, uint64_t alignment);
139
140 drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr);
141
142 drm_private void amdgpu_parse_asic_ids(struct amdgpu_device *dev);
143
144 drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
145
146 drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);
147
148 /**
149 * Inline functions.
150 */
151
152 /**
153 * Increment src and decrement dst as if we were updating references
154 * for an assignment between 2 pointers of some objects.
155 *
156 * \return true if dst is 0
157 */
update_references(atomic_t * dst,atomic_t * src)158 static inline bool update_references(atomic_t *dst, atomic_t *src)
159 {
160 if (dst != src) {
161 /* bump src first */
162 if (src) {
163 assert(atomic_read(src) > 0);
164 atomic_inc(src);
165 }
166 if (dst) {
167 assert(atomic_read(dst) > 0);
168 return atomic_dec_and_test(dst);
169 }
170 }
171 return false;
172 }
173
174 #endif
175